CN108540364A - A kind of decoding of MVB bus data and collection method based on CPLD technologies - Google Patents
A kind of decoding of MVB bus data and collection method based on CPLD technologies Download PDFInfo
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- CN108540364A CN108540364A CN201810234274.5A CN201810234274A CN108540364A CN 108540364 A CN108540364 A CN 108540364A CN 201810234274 A CN201810234274 A CN 201810234274A CN 108540364 A CN108540364 A CN 108540364A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/40293—Bus for use in transportation systems the transportation system being a train
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Abstract
The present invention provide it is a kind of based on CPLD technologies MVB bus data decoding and collection method, the present invention follows TCN standards regulation, MVB bus data are decoded using CPLD chips, and decoded data collection is stored in FIFO (First Input First Output fifo queues) chip.It include following logic functional block in CPLD chips：Digital signal filter module, start bit judgment module, digit it is judged that module, main frame sequence judgment module, from frame sequence judgment module, serial data turn parallel data module, frame data terminate judgment module, data storage control module, error in data judgment module.Digital signal filter function is added in method, improves the accuracy of decoding data, realizes to MVB bus online data, real-time decoding and the function of storage.
Description
Technical field
The present invention relates to train network communication field more particularly to a kind of MVB bus data decodings based on CPLD technologies
And collection method
Technical background
MVB (Multifunction Vehicle Bus, multifunctional vehicle bus) is that one kind being mainly used for having interoperability
Serial data communications busses between the InterWorking Equipment of interchangeability requirement are TCN (Train Communication Net, row
Vehicle communication network) a part, it then follows IEC61375-1《Train Communication Network》(abbreviation TCN standards) standard.With China's high ferro
With the fast development of urban track traffic, the MVB products for meeting TCN standards are more and more applied in Train Control.
Efficiently, reliably MVB bus data are decoded and collected using TCN agreements, to train network data analysis, breakdown judge, control
System testing and debugging processed are crucial.
Existing MVB bus data decoding process has following two：1, it is decoded using oscillograph, oscillograph crawl is total
Line waveform, and low and high level analysis is carried out to waveform using software, finally realize bus encoding/decoding；2, logic analyser solution is utilized
Code, logic analyser obtains bus low and high level, and is decoded to low and high level using software.It can be seen that existing decoding
Mode does not have real-time, to the online real-time decoding of bus data and cannot collect.
Invention content
The technical problem to be solved by the present invention is to provide a kind of online, real-time decoding MVB bus data using CPLD technologies
And to method that decoded data is collected storage.
In order to solve the above technical problems, the present invention is provided according to TCN standards, using CPLD chips to MVB bus data solution
Code, and decoded data collection is stored in FIFO (First Input First Output fifo queues) chip
It is interior.It include following logic functional block in CPLD chips：Digital signal filter module, start bit judgment module, digit it is judged that
Module, main frame sequence judgment module, turn parallel data module from frame sequence judgment module, serial data, frame data terminate to judge
Module, data storage control module, error in data judgment module.
The digital signal filter module samples 1.5 megahertzs of MVB bus signals as defined in TCN standards, signal
Processing, bus signals reduction；
The start bit judgment module according to TCN standards regulation MVB bus communication data start bit is judged, simultaneously
Trigger decoding operate；
The digit is it is judged that module provides number of bits according to " 0 ", position data " 1 ", position data " NH " and position according to TCN standards
Data " NL " decoding judges；
The main frame sequence judgment module starts delimiter multilevel iudge according to TCN standards regulation to prime frame data, triggers
Prime frame data decode；
It is described to be provided from frame sequence judgment module to the delimiter multilevel iudge since frame data, triggering according to TCN standards
It is decoded from frame data；
The serial data turns parallel data module according to the digit it is judged that module, by every 8 bit-serial bus data
Be converted to parallel data；
The frame data terminate judgment module and are provided according to TCN standards, while according to the digit it is judged that module is to frame
The data transfer ends judge, and trigger data transmission monitoring operation next time；
The serial data is turned the parallel data of parallel data module output by the data storage control module, according to elder generation
Into in the principle storage to fifo chip first gone out；
The error in data judgment module is provided according to TCN standards, and according to the digit it is judged that module, the frame number
MVB bus data transmission fault is judged according to end judgment module and from the frame response time.
MVB bus data decoding provided by the present invention and collection method, which is characterized in that include the following steps：
Step 1 carries out reset initialization operation to each logic functional block in CPLD chips；
Step 2, the digital signal filter module are filtered the MVB bus digital signal of input；
Step 3, treated that bus signals monitor in real time to step 2 for the start bit judgment module, meets when having
After the signal that beginning position requires, the decoding operate of triggering following；
Step 4, the main frame sequence judgment module and described from frame sequence judgment module, while to total after start bit
Line sequence row carry out principal and subordinate's frame sequence judgement, the decoding of prime frame data are triggered when prime frame starts delimiter when sequence meets, when sequence is full
Triggering decodes foot from frame data when delimiter since frame.
Step 5, the decoding of principal and subordinate's frame data, the serial data turn parallel data module and turn every 8 bit-serial bus data
Changing parallel bus data into, parallel bus data are 16, wherein：1 to 8th is bus communication data, and the 9 to 15th is frame
Sequence number, the 16th is principal and subordinate's flag of frame.Meanwhile error in data judgment module contraposition error in data is judged, when having
When bit-errors occur, terminates this decoding and return to step 1, and provide fault interrupt；
Step 6, every 8 bit-serial bus data turn the parallel bus data-triggered once data storage control module behaviour
Make, 16 bit parallel datas are written in fifo chip；
Step 7, when the frame data terminate to stop this frame transmission decoding behaviour after judgment module monitors frame end mark
Make, each logic module is reset into init state, starts frame decoding operation next time, restart from step 1.Together
When, the error in data judgment module judges terminating bit-errors, when there is end bit-errors to occur, in making mistake
It is disconnected；
Step 8, after prime frame the data transfer ends, the error in data judgment module triggers timer, and to following
The slave frame response time judged, if time-out if provide from frame response timeout fault interrupt.
The positive effect of the present invention is：It is disclosed in this invention that MVB bus data are decoded and received using CPLD technologies
Set method, logical functional structure include digital signal filter module, start bit judgment module, digit it is judged that module, master
Frame sequence judgment module, from frame sequence judgment module, serial data turn parallel data module, frame data terminate judgment module, number
According to storage control module, error in data judgment module.Digital signal filter function is added in method, improves the standard of decoding data
True property, and realize according to TCN standards to MVB bus online data, real-time decoding and the function of storage.For train network data
Analysis, breakdown judge, control system test and debugging provide online, real-time operation ways and means.
Description of the drawings
A kind of illustrative view of functional configuration of the decoding of MVB bus data and collection method based on CPLD technologies of Fig. 1 present invention
A kind of workflow schematic diagram of the decoding of MVB bus data and collection method based on CPLD technologies of Fig. 2 present invention
Fig. 3 digital signal filter module principle schematic diagrames of the present invention
Fig. 4 start bit judgment module principle schematics of the present invention
Fig. 5 digits of the present invention it is judged that, stop bits judge, dislocation erroneous judgement and stop bits false judgment principle schematic
Fig. 6 principal and subordinate's frame sequences of the present invention judge principle schematic
Fig. 7 serial datas of the present invention turn parallel data module principle schematic diagram
Specific implementation mode
To keep the purpose of the present invention, technical solution and method clearer, below in conjunction with the attached drawing in the present invention, to this
Technical solution in invention is clearly and completely described, it is clear that and described embodiments are some of the embodiments of the present invention,
Instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative labor
The every other embodiment obtained under the premise of dynamic, shall fall within the protection scope of the present invention.
As shown in Figure 1：A kind of decoding of MVB bus data and collection method based on CPLD technologies, logic functional block
Including digital signal filter module, start bit judgment module, digit it is judged that module, main frame sequence judgment module, from frame sequence
Judgment module, serial data turn parallel data module, frame data terminate judgment module, data storage control module, error in data
Judgment module.
The workflow of the implementation case is as shown in Figure 2：System obtains each logic functional block initialization of reset, and system is real
When acquire MVB bus signal, bus digital signal be 1.5 megahertzs, sample frequency be 48 megahertzs；Bus digital signal is passed through
Signal enters start bit judgment module after being filtered, and is judged start bit according to the regulation of TCN standards, start bit success
It receives and indicates there are data to start to transmit in bus；Subsequent 8 data of start bit are principal and subordinate's frame delimiter, according to TCN standards
Regulation judges the data of this time transmission as prime frame or from frame；After the completion of the judgement of principal and subordinate's frame, start the decoding of frame data, by frame data
In every 8 Bits Serial data conversion at parallel data, parallel data is 16, and the 1 to 8th is frame data, and the 9 to 15th is frame sequence
Row number, the 16th is principal and subordinate's flag of frame, will be in 16 data deposit fifo chips after conversion end；According to the rule of TCN standards
There is 1 end bit flag after determining MVB bus the data transfer ends, when monitoring stop bits, terminates this decoding and will decode
Each logic functional block is resetted after data deposit FIFO, starts data decoding operate next time；MVB bus is added in the present invention
Data transmission fault arbitration functions, according to TCN standards regulation to data bit-errors, terminate bit-errors and from frame response timeout into
Row judges, wherein 42.7 microseconds are limited to from frame response timeout, when monitoring any one mistake in three of the above, system knot
Shu Dangqian decoding operates reset each logic functional block, start data decoding operate next time, and provide fault interrupt prompt letter
Number.
Specifically：
As shown in figure 3, digital signal filter module uses 48 megahertzs of sample frequency, to 1.5 megahertzs of MVB bus
Signal carry out sampling processing, using d type flip flop sampling clock rising edge to MVB bus signal sampling, every 3 sampling clocks
For a sampling unit, builds counter using JK flip-flop and sampling clock is counted, to 3 samplings in each sampling unit
Signal carries out 3 taking 2 processing, takes the output of identical 2 signal levels in 3 sampled signals as sampling unit, and then realize
MVB bus signal is filtered.
Start bit judgment module principle as shown in figure 4, in decoding process working clock frequency be 24 megahertzs, MVB signals
Failing edge triggering start bit judgement, build counter using JK flip-flop, MVB failing edge flip-flop numbers are started to work,
MVB rising edge flip-flop numbers suspend, and the width of MVB signal level "0"s are counted using counter, when width works at 7 to 9
It is considered as effective start bit, triggering following decoding effort during clock cycle, invalid start bit makes system reset.
As shown in figure 5, the decoding of data is triggered by the rising edge of start bit signal after frame data transmission start bit, MVB letters
Number working frequency is 1.5 megahertzs, and working clock frequency is 24 megahertzs in decoding process.Every 16 operating clock cycles are one
One MVB data is divided into preceding subluxation and rear subluxation by position MVB data, is 8 clock cycle per subluxation.Half-and-half using d type flip flop
Position data sampling, the counter built using JK flip-flop is to clock cycle count.Take the 4th and the 5th in 8 clock cycle
The sampled level of clock takes the level that it is subluxation MVB data when the 4th is identical with the sampled level of the 5th clock；When the 4th
When different with the 5th sampled level of clock, trigger bit error signal stops decoding and resets each logic module.Current subluxation MVB
The level of data is " 0 ", and when the level of rear subluxation MVB data is " 1 ", this MVB data are decoded as " 0 "；Current subluxation MVB numbers
According to level be " 1 ", when the level of rear subluxation MVB data is " 0 ", this MVB data are decoded as " 1 "；Current subluxation MVB data
Level be " 0 ", when the level of rear subluxation MVB data is " 0 ", this MVB data are decoded as end mark signal, stop decoding
Operation resets each logic module, restarts to monitor start bit；The level of current subluxation MVB data is " 1 ", rear subluxation MVB numbers
According to level be " 1 " when, triggering terminates error signal, stops decoding operate and resets each logic module, restarts monitoring starting
Position.
Principal and subordinate's frame sequence judges principle as shown in fig. 6, starting for 8 principal and subordinate's frames behind MVB bus data transmission start bit
Delimiter, the data for being used to refer to this transmission are prime frame data or from frame data.8 principal and subordinate's frames are started delimiter to be divided into
16 1/2 bit sequences, main frame sequence are " 1,1,0,0,0,1,1,1,0,0,0,1,0,1,0,1 ", be from frame sequence " 1,0,1,0,
1,0,0,0,1,1,1,0,0,0,1,1 ", compare the MVB bus signal of input one by one, when identical as main frame sequence, output master
Frame useful signal, and from the identical triggering of frame sequence from frame useful signal, when list entries and both of the above are different from, be for
The decoding operate of invalid frame data, suspension resets each logic module, restarts to monitor start bit.
Serial data turns parallel data principle as shown in fig. 7, incoming 8 built by d type flip flop of decoded MVB data
Bit shift register, contraposition are counted, when counting down to 8,8 bit shift register data are output to 8 bit parallel datas and are delayed
It rushes in device；After decoding principal and subordinate's frame is effective, to corresponding frame sequence, count is incremented, and number of frames is indicated with 7 bit binary datas, and
It is output in low 7 in 8 bit parallel data buffers, main frame sequence is by the 8th set, from frame sequence by the 8th reset；
8 bit parallel data of two above is combined into 16 bit parallel datas, often converts 8 Bits Serial data, one is stored in fifo chip
16 bit parallel datas.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, it will be understood by those of ordinary skill in the art that：It still can be to previous embodiment
Recorded technical solution is modified, and either carries out equivalent replacement to which part or all technical features；And these are repaiied
Change or replaces, the range for technical solution of the embodiment of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (2)
1. a kind of decoding of MVB bus data and collection method, structure feature based on CPLD technologies are, including：
Realize that the method for the present invention, logic functional block have using CPLD chips：Digital signal filter module, start bit judge mould
Block, digit are it is judged that module, main frame sequence judgment module, from frame sequence judgment module, serial data turn parallel data module, frame
End of data judgment module, data storage control module, error in data judgment module；
The digital signal filter module samples 1.5 megahertzs of MVB bus signals as defined in TCN standards, signal processing,
Bus signals restore；
The start bit judgment module judges MVB bus communication data start bit according to TCN standards regulation, triggers simultaneously
Decoding operate；
The digit is it is judged that module provides number of bits according to " 0 ", position data " 1 ", position data " NH " and position data according to TCN standards
" NL " decoding judges；
The main frame sequence judgment module provides to start delimiter multilevel iudge, triggering prime frame to prime frame data according to TCN standards
Data decode；
It is described to provide, to the delimiter multilevel iudge since frame data, to trigger from frame according to TCN standards from frame sequence judgment module
Data decode；
The serial data turns parallel data module according to the digit it is judged that module, by every 8 bit-serial bus data conversion
For parallel data；
The frame data terminate judgment module and are provided according to TCN standards, while according to the digit it is judged that module is to frame data
The end of transmission judges, and triggers data transmission monitoring operation next time；
The serial data is turned the parallel data of parallel data module output by the data storage control module, according to advanced elder generation
In the principle storage to fifo chip gone out；
The error in data judgment module is provided according to TCN standards, and according to the digit it is judged that module, the frame data knot
Beam judgment module and MVB bus data transmission fault is judged from the frame response time.
2. structure according to claim 1, method characteristic are, including：
Step 1 carries out reset initialization operation to each logic functional block in CPLD chips；
Step 2, the digital signal filter module are filtered the MVB bus digital signal of input；
Step 3, treated that bus signals monitor in real time to step 2 for the start bit judgment module, meets start bit when having
It is required that signal after, the decoding operate of triggering following；
Step 4, the main frame sequence judgment module and described from frame sequence judgment module, while to total line sequence after start bit
Row carry out principal and subordinate's frame sequence judgement, when sequence meet when prime frame starts delimiter trigger prime frame data decoding, when sequence meet from
Triggering is decoded from frame data when frame starts delimiter.
Step 5, principal and subordinate's frame data decoding, the serial data turn parallel data module by every 8 bit-serial bus data conversion at
Parallel bus data, parallel bus data are 16, wherein：1 to 8th is bus communication data, and the 9 to 15th is frame sequence
Number, the 16th is principal and subordinate's flag of frame.Meanwhile error in data judgment module contraposition error in data is judged, when there is dislocation
When accidentally occurring, terminates this decoding and return to step 1, and provide fault interrupt；
Step 6, every 8 bit-serial bus data turn the once data storage control module operation of parallel bus data-triggered, will
16 bit parallel datas are written in fifo chip；
Step 7 monitors that stopping this frame after frame end mark transmits decoding operate when the frame data terminate judgment module,
Each logic module is reset into init state, starts frame decoding operation next time, restarts from step 1.Meanwhile
The error in data judgment module judges terminating bit-errors, when there is end bit-errors to occur, provides fault interrupt；
Step 8, after prime frame the data transfer ends, the error in data judgment module triggers timer, and to it is next from
The frame response time is judged, is provided from frame response timeout fault interrupt if time-out.
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Cited By (2)
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| CN110351173A (en) * | 2019-06-24 | 2019-10-18 | 上海申珩电子科技有限公司 | Multifunctional train bus detection device and method |
| CN112187572A (en) * | 2020-09-18 | 2021-01-05 | 北京全路通信信号研究设计院集团有限公司 | Method and system for judging MVB working master station equipment |
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