CN109756303B - Simplex asynchronous Manchester code receiving and decoding method - Google Patents
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Abstract
The invention discloses a simplex asynchronous Manchester code receiving and decoding method, relates to the field of communication, and overcomes the defects of the existing simplex asynchronous Manchester code receiving and processing method. The invention expands the hardware platform adapted to the original asynchronous Manchester code, changes the original C language code into the hardware language code, and expands the hardware platform from being suitable for MCU chips to FPGA chips; the invention can receive multi-path asynchronous Manchester code data flow on one FPGA chip and has the characteristics of concurrency, real time, single line and high speed; the invention can achieve better error detection and fault tolerance effects only by small software and hardware scale, achieves better balance of complexity and performance, and is suitable for receiving and decoding asynchronous Manchester codes.
Description
Technical Field
The invention relates to the field of communication, in particular to a simplex asynchronous Manchester code receiving and decoding method.
Background
Asynchronous manchester code is a communication encoding scheme using phase encoding, and determines whether a transmitted symbol is 0 or 1 by the duration of high and low levels within one symbol period and the context. During synchronous transmission, a transmitting end simultaneously transmits a data signal and a code element clock signal, and a receiving end samples received data by using the received clock signal and recovers the code element data. In asynchronous transmission, the sending end only sends code element signals, but not clock signals, generally sends a synchronization head before code element data, the receiving end regenerates a local clock according to the received synchronization head, and the local clock samples the data code elements and recovers the same data as the sending end. Simplex transmission refers to that the data transmission direction is unidirectional transmission, and duplex transmission refers to that the data transmission direction is two directions.
In the acquisition process of the slow-rate change physical quantity, the update rate of the digital quantity output by the acquisition device is far greater than the change rate of the acquired analog quantity. According to nyquist sampling theory, as long as the acquisition digital rate is greater than 2 times of the change rate of the analog signal, the analog signal can be recovered by using the sampled digital signal. For the analog signals with the characteristics, after the acquisition is finished, the data can be transmitted to a post-processing unit in a simplex asynchronous Manchester code mode. Compared with a synchronous duplex transmission mode, the simplex asynchronous mode can transmit data generated by the sensor to the post-processing unit by only one signal wire.
In the asynchronous Manchester code signal, each bit code element is composed of two levels before and after the intermediate jump. The asynchronous Manchester code data frame contains 5 types of code elements, which are respectively: idle bit, start bit, data 0 bit, data 1 bit, and stop bit.
Where the free bits represent no data and consist of consecutive high levels. The start bit represents the start of a data frame, the first half of the start bit is at low level, the second half of the start bit is at high level, and the high and low levels respectively occupy 50% of the duration time. The stop bit represents the end of the data frame, and in contrast to the start bit, the first half is high and the second half is low, the high and low durations each being 50%. Data 1 bit, first 1/4 bit low and last 3/4 bit high. Data bit 0, first 3/4 bits low, and last 1/4 bits high.
A complete Manchester transmission code byte consists of a start bit, 8 data bits, a check bit and a stop bit, and the stop bit can be connected with the start bit of the next byte to continuously and sequentially transmit a plurality of data bytes. A plurality of data bytes form a group of data frames, and one data frame completes the transmission of one measurement data of the sensor. The check bit adopts a parity check mode, only checks the data bit and does not contain a start bit and a stop bit.
The receiving and processing of the prior simplex asynchronous Manchester code data frame are realized by codes finished by C language and run in a CPU (central processing unit) or MCU (microcontroller) processor. The receiving processing realized by the C language code is limited by the working characteristics of the processors, one processor can only receive one path of asynchronous Manchester code stream at the same time, and cannot receive multiple paths of asynchronous Manchester code stream data in parallel.
The existing Manchester code receiving module has no error detection and correction mechanism or has too complicated detection and correction mechanism. The receiving module without the detection mechanism can transfer error data once an error occurs in the transmission process. And the detection mechanism is too complex, and the system complexity exceeds the obtained error detection benefit, so that the implementation cost is not matched with the performance. In the prior art, a plurality of signal lines are used for synchronous multiplexing of Manchester code transmission. To transmit a bidirectional data signal, a clock signal is also transmitted, which requires a clock signal generator at the data transmitting end. But also consumes more line resources and hardware resources.
Disclosure of Invention
The present invention is directed to a simplex asynchronous manchester code receiving and decoding method, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a simplex asynchronous Manchester code receiving and decoding method comprises the following specific steps:
step one, acquiring a receiving code sequence and filtering glitch interference with the duration less than one clock cycle in the receiving code sequence;
identifying the initial bit of the received code sequence and starting a decoding state machine;
step three, the decoding state machine changes in sequence along with the change of the level of the received code sequence according to a preset state flow;
identifying abnormal level change larger than one clock period in the received code sequence, and abandoning the received code sequence with the abnormal level change larger than one clock period;
fifthly, judging the data bits of the data frames according to the Manchester code encoding rule, and discarding the data frames which do not accord with the encoding rule;
step six, combining 8 interpreted data bits into a received data byte, generating a checksum from the 8 data bits, carrying out XOR judgment on the checksum and the received check bit, and discarding the data frame with the check error;
step seven, generating a byte output clock according to the stop bit of the received code sequence;
splicing a plurality of bytes of data before and after the data is spliced to restore a complete data acquisition value;
and step nine, storing a plurality of data acquisition values, calculating an average value, discarding the data acquisition value with larger deviation from the average value, taking out the data acquisition value with smaller deviation from the average value, and averaging again to obtain an optimized sampling value.
As a further scheme of the invention: the step of filtering the glitch interference in the received code sequence in the step one is as follows: the received code sequence passes through the front-end D trigger, the working clock rate of the front-end D trigger is 8 times of the rate of the received code sequence, if glitch interference with the duration length smaller than one clock cycle occurs in the received code sequence, secondary sampling is performed on the received code sequence through the front-end D trigger, most glitches are filtered, and designers find that under the condition of normal communication, the glitches occur as small probability events, the glitch pulse duration is larger than one clock cycle as a minimum probability event.
As a further scheme of the invention: the predetermined state flow of the decoding state machine in the third step is as follows: idle state, start bit state, 0 th bit state, 1 st bit state, 2 nd bit state, 3 rd bit state, 4 th bit state, 5 th bit state, 6 th bit state, 7 th bit state, check bit state, stop bit state. When the level of the received code sequence is detected to jump from high level to low level for the first time, the decoding state machine jumps from an idle state to a starting bit state, and the resetting operation of the data bit condition process is completed in the starting bit state. And then, the level jumps from low level to high level and then from high level to low level, and if the level jump sequence and the level holding time are consistent with preset maintenance, the decoding state machine jumps from the state of the initial bit to the state of the 0 th bit. If the level jump sequence is different from the preset sequence or the level holding time is different from the preset time, the decoding state machine will jump back to the idle state.
Each state of the decoding state machine corresponds to a state condition process, one decoding logic comprises a plurality of state condition processes, after the decoding state machine enters the state, the corresponding state condition process is triggered and started, the key parameters of the state are recorded, after the state is stopped, the state condition processes stop running, the recorded key parameters are not updated, and the key parameters can be called by other state condition processes or modules. And decoding the 0 th bit state to the 7 th bit state of the state machine, wherein the 8 states correspond to 8 state condition processes, and each process records the duration length of the high level and the low level of the corresponding data state bit. If the duration of the low level is greater than the length of the duration of the high level, the corresponding data bit is 0, otherwise it is 1. If the duration lengths of the high level and the low level are the same, the decoding state can think that the level of the received code sequence is wrong, and discard the frame data, the simplex communication is generally applied to an oversampling system, the data updating rate is far greater than the self changing rate of the signal, the sampled data can be screened secondarily, and the accidental discarding of the data frame cannot influence the system.
The received code sequence filtered by the pre-D flip-flop theoretically has the possibility of an error level with a duration longer than one clock cycle, and if no processing is performed, an erroneous decoding result is generated. The error level will destroy the original continuous length of the receiving code sequence, and according to the characteristic that the error level will destroy the coding rule of the receiving code sequence, the decoding state machine continuously monitors the parameters recorded by the current condition process, and once the out-of-range parameters appear, the decoding state machine immediately returns to the idle state to discard the current receiving code sequence. This error detection discard process is appropriate for manchester code data frames that are repeatedly transmitted in a simplex asynchronous communication mode.
As a further scheme of the invention: the state condition process is used to record the state duration, which may be identified by the number of clock cycles.
As a further scheme of the invention: and step six, the checksum is obtained by carrying out exclusive OR on 8 data bits in parallel, the checksum is compared with the received check bit to obtain a check result, the next state of the decoding state machine is determined according to the check result, if the check result is correct, the decoding state machine jumps to a stop bit state, otherwise, the decoding state machine jumps to an idle state, and the data frame of the received data byte is discarded.
As a further scheme of the invention: and step eight, combining a plurality of byte data into one data sampling value by adopting a byte combining module.
Compared with the prior art, the invention has the beneficial effects that: the invention changes the multiplex multi-wire transmission mode into the simplex single-wire transmission mode, thereby simplifying the line resources and the hardware resources.
Compared with the prior art, the invention also has the following advantages: the invention expands the hardware platform adapted to the original asynchronous Manchester code, changes the original C language code into the hardware language code, and expands the hardware platform from being suitable for MCU (microcontroller) chips to FPGA (field programmable logic array) chips.
Compared with the prior art, the invention has the beneficial effects that: the invention solves the problem that an MCU (microcontroller) chip can not receive multiple paths of asynchronous Manchester code streams at the same time, particularly, multiple paths of code streams with different data rates can receive multiple paths of asynchronous Manchester code data streams on an FPGA (field programmable logic array) chip, and compared with the prior realization of receiving the asynchronous Manchester codes based on the MCU, the invention has the characteristics of concurrency, real-time, single-line and high-speed transmission.
Compared with the prior art, the invention has the beneficial effects that: the invention provides an error detection and fault tolerance mechanism with a three-layer structure most suitable for asynchronous Manchester code reception, which sequentially comprises the following steps according to the sequence of signal flow: filtering burrs of a first layer D trigger; the second layer encoding rule checks for deletion; the third layer is a small deviation average process. After the three-level error detection and fault tolerance mechanism is adopted, the occupied software and hardware scale is very small, the better error detection and fault tolerance effect is achieved, the better balance of complexity and performance is achieved, the interference and the burr in the received signal can be filtered, and the decoding accuracy is improved; the method has the capability of cutting, can be suitable for asynchronous Manchester code decoding, and has wide application prospect.
Drawings
FIG. 1 is a schematic diagram of the encoding level rules of a simplex asynchronous Manchester code.
Fig. 2 is a schematic structural diagram of a single-wire simplex temperature acquisition system according to embodiment 1 of a simplex asynchronous manchester code receiving and decoding method.
Fig. 3 is a block diagram showing the principle of the receiving logic of embodiment 1 of the simplex asynchronous manchester code receiving and decoding method.
Fig. 4 is a flow chart of a receiving state of embodiment 1 of a simplex asynchronous manchester code receiving and decoding method.
Detailed Description
The technical solution of the present patent will be described in further detail with reference to the following embodiments.
Example 1
The output of the digital temperature acquisition probe adopts a simplex asynchronous Manchester code form, and the output data adopts a single-wire unidirectional form to transmit the acquired temperature data to the FPGA chip. The invention is used in an FPGA chip for receiving and processing, and the composition of the single-wire simplex temperature acquisition system of the embodiment is shown in figure 2. The temperature acquisition values received and processed by the FPGA chip are sent to the MCU, and the MCU performs small deviation average processing on the plurality of acquisition values.
The model of the digital temperature acquisition probe in this embodiment is TSIC306, the FPGA uses EP4CE10E22I7N chip of INTEL (INTEL) corporation, and the MCU uses STM32F407ZGT6 chip of ST (intentionally made semiconductor) corporation. The digital temperature acquisition output data rate of the embodiment is 8kbps, one temperature acquisition value comprises two bytes, and the front is high and the rear is low. The clock rate of the module processing is 128kHz, and 16 clock cycles are contained in one data cycle.
The module composition of this embodiment includes: a schematic diagram of the components of the state transition process module, the state synchronization process module, the state condition process module, the output logic generation module, the byte clock generation logic and the small deviation average processing module is shown in fig. 3.
The state transition process runs in an asynchronous mode, and the next state is given according to the output of the state condition process and the input Manchester code; the state synchronization process synchronizes the state migration process; the state condition process is used for generating state residence conditions, each state corresponds to one state condition process, after the state machine enters a certain state, the corresponding state condition process is started, the clock beat number of the state residence clock is recorded, and the state transition process determines the next state according to the clock beat number and the input signal. The output logic presents the binary value of each bit according to the state condition recorded by the state condition process. The output logic presents an array of 8-bit parallel bytes.
The receiving process of the asynchronous Manchester code is periodic, after receiving one frame of data, the system returns to an idle state to wait for the arrival of the next frame of data, and the process is repeated. This requires periodic resets of the various state processes and conditional processes within the receiving logic. And the reset management module is responsible for completing reset operation of all state processes. The reset process module performs reset operation on all condition processes, and performs reset operation on the current state process in the previous state of the current state. The reset time is the start of the present conditional process and also the end of the previous conditional process. During a condition state operation, the calculation generates condition results, the time after the condition results are generated and before the next reset pulse arrives is the storage period of the condition process results, the condition results are available, and other processes can use the condition results.
And error detection and fault tolerance processing, namely filtering burrs of the received data signal, wherein the width of a signal code element is 8 times of the width of a working clock, the high and low levels in the start bit and the stop bit respectively occupy 4 clock widths, and under the condition that the logic is 1, the duration time of the low level is 2 clock cycles, and the duration time of the high and low levels is 6 clock cycles. The minimum duration of a single level of a signal is 2 clock cycles, and if the duration of a single level is less than or equal to 1 clock cycle, we can consider that this level change is not a valid signal. According to such a criterion, the level variation having a duration of 1 clock cycle or less is discarded, and the level value before the variation is retained, thereby completing the filtering of the glitch of the data signal.
The time length of the glitch in the received data is less than or equal to one clock cycle, and the glitch is avoided by the clock rising edge of the front D trigger in one case, so that the glitch can be directly ignored. In another case, the leading edge of the pre-D flip-flop just catches the glitch, and then the subsequent logic can discard the level change according to the duration of the level change, thereby achieving the purpose of filtering the received data glitch.
The decoding state machine adopts a fault-tolerant mechanism in the form of error detection, discarding and re-receiving, and can determine that the currently received data frame is an error frame after monitoring the error state, and the decoding state machine skips from the current state to an idle state to wait for the arrival of the next correct data frame.
The receiving flow of this embodiment is as shown in fig. 4, and the decoding state machine is in an idle state without data after reset. After detecting the level change, the decoding state machine starts a starting bit detection process, the duration time of the starting bit detection process is 50% after the high level is met, and the decoding state machine jumps to a data 0 bit state from the starting bit; if the above condition is not met, the decoding state machine jumps back to the idle state. After the decoding state machine jumps to the state of each data bit, the state condition process corresponding to the data bit is started, and after the state condition process jumps to the next state bit, the high-low timing register of the previous state bit stops running, and the level before and after the logical comparison is output bit by bit to form an output logical value. And when the decoding state machine jumps to the check state, outputting a byte clock according to the check value. Output bytes are combined into a double-word data frame, and then small deviation value average processing is performed in the MCU, wherein the total sampling value in the small deviation value average processing of the embodiment is 10, 5 sampling values with larger deviation values are discarded after the first average value is taken, and the rest 5 sampling values with smaller deviation values are averaged to be used as the final optimized sampling value.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A simplex asynchronous Manchester code receiving and decoding method is characterized by comprising the following specific steps:
step one, acquiring a receiving code sequence and filtering glitch interference with the duration less than one clock cycle in the receiving code sequence;
identifying the initial bit of the received code sequence and starting a decoding state machine;
step three, the decoding state machine changes in sequence along with the change of the level of the received code sequence according to a preset state flow;
identifying abnormal level change larger than one clock period in the received code sequence, and abandoning the received code sequence with the abnormal level change larger than one clock period;
fifthly, judging the data bits of the data frames according to the Manchester code encoding rule, and discarding the data frames which do not accord with the encoding rule;
step six, combining 8 interpreted data bits into a received data byte, generating a checksum from the 8 data bits, carrying out XOR judgment on the checksum and the received check bit, and discarding the data frame with the check error;
step seven, generating a byte output clock according to the stop bit of the received code sequence;
splicing a plurality of bytes of data before and after the data is spliced to restore a complete data acquisition value;
and step nine, storing a plurality of data acquisition values, calculating an average value, discarding the data acquisition value with larger deviation from the average value, taking out the data acquisition value with smaller deviation from the average value, and averaging again to obtain an optimized sampling value.
2. The method for receiving and decoding a simplex asynchronous Manchester code according to claim 1, wherein the error detection and fault tolerance mechanism has a three-layer structure adapted to receipt of the simplex asynchronous Manchester code as follows: a first layer of pre-D trigger burr filtering mechanism; the second layer of coding rule checks the deletion mechanism; the third layer is a small deviation average processing scheme.
3. The method for receiving and decoding a simplex asynchronous Manchester code as claimed in claim 1, wherein the decoding state machine in step three is programmed to perform the following predetermined state procedures: an idle state, a start bit state, a 0 th bit state, a 1 st bit state, a 2 nd bit state, a 3 rd bit state, a 4 th bit state, a 5 th bit state, a 6 th bit state, a 7 th bit state, a check bit state and a stop bit state; when detecting that the receiving level jumps from a high level to a low level for the first time, the decoding state machine jumps from an idle state to a start bit state, and the resetting and initialization operations of the data bit condition process are completed in the start bit state; and then, the receiving level jumps from low level to high level and then jumps from high level to low level, if the level jump sequence and the level holding time are consistent with the preset sequence, the decoding state machine jumps from the state of the initial bit to the 0 th bit state, and if the level jump sequence is different from the preset sequence or the level holding time is different from the preset time, the decoding state machine jumps back to the idle state.
4. The method of receiving and decoding a simplex asynchronous Manchester code as claimed in claim 3, wherein said state condition process identifies a duration of the state condition process as a number of clock cycles.
5. The method for receiving and decoding the simplex asynchronous Manchester code according to claim 1, wherein the checksum in the sixth step is obtained by exclusive-or of 8 data bits in parallel, the checksum is compared with the received check bit to obtain a check result, the next state of the decoding state machine is determined according to the check result, if the check result is correct, the decoding state machine jumps to a stop bit state, otherwise, the decoding state machine jumps to an idle state.
6. The method for receiving and decoding the simplex asynchronous Manchester code according to claim 1, wherein the byte clock in the seventh step is an indication of the validity of the 8-bit long byte after serial-to-parallel conversion.
7. The method for receiving and decoding a simplex asynchronous Manchester code according to claim 1 or 6, wherein the byte combining module is adopted in the eighth step to combine a plurality of bytes of data into one data sample value.
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| CN111835494B (en) * | 2020-07-23 | 2021-11-16 | 深圳市龙信信息技术有限公司 | Multi-channel network data transmission system and method |
| CN111934537B (en) * | 2020-08-21 | 2023-07-21 | 湖北师范大学 | Anti-interference method for driving signals of cascade converter |
| CN113609040B (en) * | 2021-09-29 | 2022-01-28 | 深圳市中科先见医疗科技有限公司 | STM 32-based serial data receiving method and system |
| CN115225423B (en) * | 2022-07-22 | 2023-09-26 | 四川灵通电讯有限公司 | Two-wire system device-to-device communication method based on polar Manchester code |
| CN115017095B (en) * | 2022-08-05 | 2022-11-08 | 微传智能科技（常州）有限公司 | Current output type AK protocol wheel speed chip communication system and method |
| CN115664622B (en) * | 2022-10-18 | 2023-07-04 | 安徽共芯光子科技有限公司 | Manchester decoding method |
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