CN110658743A - WTB waveform recorder and recording method - Google Patents
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Abstract
The invention discloses a WTB waveform recorder and a recording method, wherein the WTB waveform recorder comprises a WTB interface circuit which continuously acquires WTB waveform signals on a WTB bus; ADC, which samples the real time digital to obtain WTB waveform digital signal; the FPGA continuously and circularly writes the WTB waveform digital signal into any storage area of the RAM; stopping writing into the current storage area when the WTB communication is abnormal, and switching to another storage area for writing; a processor which records the WTB waveform digital signal in the current storage area when the WTB communication is abnormal to a memory; the FPGA also reads WTB waveform digital signals in the current storage area in real time, decodes the WTB waveform digital signals, and sends an interrupt instruction to inform a processor to read the messages when detecting that a frame of messages is generated; the processor judges whether the WTB communication is abnormal according to the message. The invention can solve the problems of large data volume and high requirement on recording transmission speed in the waveform recording process.
Description
Technical Field
The invention relates to the technical field of TCN network transmission, in particular to a WTB waveform recorder and a recording method.
Background
The WTB is an underlying bus communication protocol specified in the TCN standards body, and includes a corresponding data link layer and a physical layer. The WTB bus is mainly suitable for the situation that the train composition needs to be changed frequently, such as the situation that international trains and multi-manufacturer trains need to be hung and hung mutually frequently and change directions frequently when in operation. The core function of the WTB bus is to automatically calculate and distribute network topology of the regrouped train, and ensure that the connectivity of the overall network can be maintained no matter how the train is marshalled.
When the WTB communication fails in the actual TCN network transmission process, if the problem that the physical layer cannot be eliminated and solved through upper layer software is involved, the problem is often eliminated by hanging devices such as an oscilloscope and a protocol analyzer on the site, which brings great inconvenience to the elimination of the problem.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a WTB waveform recorder, comprising:
the WTB interface circuit is connected with the WTB bus and is used for continuously acquiring WTB waveform signals on the WTB bus;
the ADC chip is connected with the WTB interface circuit and is used for digitally sampling the WTB waveform signal acquired by the WTB interface circuit in real time to obtain a WTB waveform digital signal;
a RAM including two storage areas;
the FPGA chip is respectively connected with the ADC chip and the RAM and is used for continuously writing the WTB waveform digital signals sampled by the ADC chip into any storage area of the RAM in a circulating manner; when the WTB communication is abnormal, stopping writing the WTB waveform digital signal into the current storage area, and switching to another storage area to continue writing the WTB waveform digital signal;
a memory;
the processor is respectively connected with the FPGA chip and the memory and is used for recording the WTB waveform digital signals in the current storage area in case of WTB communication abnormality into the memory through the FPGA chip;
the FPGA chip is also used for reading WTB waveform digital signals in a current storage area in real time, decoding the WTB waveform digital signals to generate an HDLC message, and sending an interrupt instruction to inform the processor to read the HDLC message when detecting that a complete frame of HDLC message is generated; and the processor judges whether the WTB communication is abnormal or not according to the HDLC message.
In one embodiment, the FPGA chip reads the WTB waveform digital signal in the current storage area in real time, judges the WTB waveform digital signal to obtain a 0-1 signal, and decodes the 0-1 signal to obtain a decoding result and an HDLC message.
In one embodiment, a FIFO buffer is arranged in the processor, the FPGA chip sends the decoding result and the HDLC packet to the FIFO buffer, and the processor reads the decoding result and the HDLC packet from the FIFO buffer.
In one embodiment, the FPGA chip transmits the WTB waveform digital signals in the current storage area when the WTB communication is abnormal to the FIFO buffer, and the processor records the WTB waveform digital signals in the FIFO buffer when the WTB communication is abnormal into the memory.
In one embodiment, a DMA circuit is arranged in the FPGA chip, and the FPGA chip writes the WTB waveform digital signal sampled by the ADC chip into the RAM through the DMA circuit.
In one embodiment, the sampling rate of the ADC chip is at least 60 Mps; the RAM is a DDR3 memory chip.
In one embodiment, further comprising: and the upper computer is connected with the processor and used for reading the WTB waveform digital signals recorded in the memory when the WTB communication is abnormal, performing waveform display on the WTB waveform digital signals when the WTB communication is abnormal, analyzing the WTB waveform digital signals when the WTB communication is abnormal and generating WTB waveform abnormal messages.
In one embodiment, the upper computer is further configured to configure the processor to record a WTB waveform digital signal corresponding to a preset HDLC packet in the memory, and perform waveform display on the WTB waveform digital signal.
The invention also provides a WTB waveform recording method, which comprises the following steps:
the WTB interface circuit continuously acquires WTB waveform signals on a WTB bus;
the ADC chip performs digital sampling on the WTB waveform signal acquired by the WTB interface circuit in real time to obtain a WTB waveform digital signal;
the FPGA chip continuously and circularly writes WTB waveform digital signals sampled by the ADC chip into any storage area of the RAM;
the FPGA chip reads the WTB waveform digital signal in the current storage area in real time and decodes the WTB waveform digital signal to generate an HDLC message;
when detecting that a frame of complete HDLC message is generated, sending an interrupt instruction to inform the processor to read the HDLC message;
when the processor judges that the WTB communication is abnormal according to the HDLC message, the processor informs the FPGA chip to stop writing the WTB waveform digital signal into the current storage area and switches to another storage area to continue writing the WTB waveform digital signal;
and the processor records the WTB waveform digital signals in the current storage area when the WTB communication is abnormal into the memory through the FPGA chip.
In one embodiment, the FPGA chip reads the WTB waveform digital signal in the current storage area in real time, judges the WTB waveform digital signal to obtain a 0-1 signal, and decodes the 0-1 signal to obtain a decoding result and an HDLC message.
One or more embodiments of the present invention may have the following advantages over the prior art:
the invention completes the diagnosis of WTB communication through decoding and message identification, then saves the physical layer waveform segment when the WTB communication is wrong through the FPGA chip, discards useless waveform data through the WTB communication diagnosis, and only saves the physical layer waveform segment when the WTB communication is abnormal, thereby improving the efficiency of the waveform recorder, reducing the cost of waveform recording, lowering the requirement on the storage speed of a memory, avoiding the need of using a CPU and the FPGA for high-speed communication, and reducing the design difficulty and the realization difficulty.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a WTB waveform recorder according to a first embodiment of the present invention;
fig. 2 is a flowchart illustrating a WTB waveform recording method according to a second embodiment of the invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
Example one
Fig. 1 is a schematic structural diagram of a WTB waveform recorder according to a first embodiment of the present invention. As shown in fig. 1, includes a WTB interface circuit 10, an ADC chip 20, a RAM30, an FPGA chip 40, a memory 50, and a processor 60.
The following is a detailed description of the various components and their operation in the WTB waveform recorder.
The WTB interface circuit 10 is connected to a WTB bus (not shown in fig. 1) and is configured to continuously obtain a WTB waveform signal on the WTB bus.
And the ADC chip 20 is connected to the WTB interface circuit 10, and is configured to perform digital sampling on the WTB waveform signal acquired by the WTB interface circuit 10 in real time to obtain a WTB waveform digital signal.
In order to meet the requirement of analyzing the WTB waveform signal of the physical layer, the sampling rate of the WTB waveform signal at least needs 60Mps, and the sampling precision adopts 14 bits. Thus, the sampling rate of the ADC chip 20 is at least 60 Mps. Optionally, the ADC chip 20 is a high-speed ADC chip with a sampling rate of 60 Mps. In order to save cost, the ADC chip 20 may be two medium-speed ADC chips with a sampling rate of 30Mps, but is not limited to two medium-speed ADC chips with a sampling rate of 30Mps, and may also be more than two low-speed ADC chips, as long as it meets the requirement that the total sampling rate is at least 60 Mps.
RAM30 is divided into multiple chip memory partitions, each of which is 1 mbyte in size. The RAM30 includes at least two storage areas. Specifically, the FPGA chip 40 writes the WTB waveform digital signal sampled by the ADC chip 20 into the current partition, and then starts writing from the head, and continuously updates the WTB waveform digital signal in the current partition, so that the WTB waveform digital signal with the latest 1 mbyte is always maintained.
Preferably, the RAM30 is a DDR3 memory chip, and the memory of the DDR3 memory chip requires more than 2M bytes, because it is cheaper and 128M byte DDR3 memory chip can be used. The DDR3 memory chip can only operate 1M byte address at a time, and when the 1M byte is fully written, writing is started from the head, so that the DDR3 memory chip always keeps 1M byte latest waveform data. Suppose the current memory block number is i, the memory base address is 1M × i, the relative offset range of the memory address is 0x00000-0xfffff, and the actual current access address is the memory base address plus the offset address, wherein the offset address circulates in the relative offset range of the memory address.
The FPGA chip 40 is respectively connected with the ADC chip 20 and the RAM30 and is used for continuously writing the WTB waveform digital signals sampled by the ADC chip 20 into any storage area of the RAM30 in a circulating manner; when the WTB communication is abnormal, the writing of the WTB waveform digital signal into the current storage area is stopped, and the WTB waveform digital signal is switched to another storage area to be continuously written. A DMA circuit is arranged in the FPGA chip 40, and the FPGA chip 40 writes the WTB waveform digital signal sampled by the ADC chip 20 into the RAM30 through the DMA circuit.
For example, the FPGA chip 40 continuously and cyclically writes the WTB waveform digital signal sampled by the ADC chip 20 into the first memory block of the DDR3 memory chip, when the WTB communication is abnormal, stops writing the WTB waveform digital signal into the first memory block, and switches to the next memory block (i.e., the second memory block) to continuously and cyclically write the new WTB waveform digital signal into the second memory block. And when the WTB communication is abnormal next time, stopping writing the WTB waveform digital signal into the second memory block, and switching to the first memory block to continuously and circularly write the new WTB waveform digital signal into the first memory block. The first memory block and the second memory block are used alternately.
And the processor 60 is respectively connected with the FPGA chip 40 and the memory 50 and is used for recording the WTB waveform digital signals in the current storage area when the WTB communication is abnormal into the memory 50 through the FPGA chip 40. Specifically, the processor 60 transmits the WTB waveform digital signal in the current storage area when the WTB communication is abnormal to the FIFO buffer through the FPGA chip 40, and then records the WTB waveform digital signal in the FIFO buffer when the WTB communication is abnormal in the memory 50. The size of the data to be transmitted at a time is determined according to the size of the FIFO buffer.
It should be noted that after the storage area starts to write the WTB waveform digital signal, the FPGA chip 40 reads the WTB waveform digital signal in the current storage area in real time, and performs decoding processing on the WTB waveform digital signal to generate the HDLC packet, when it is detected that a complete frame of HDLC packet is generated, an interrupt instruction is sent to notify the processor 60 to read the HDLC packet, and the processor 60 determines whether the WTB communication is abnormal according to the HDLC packet. A FIFO buffer is arranged in the processor 60, the FPGA chip 40 sends an interrupt instruction to the processor 60, and sends the decoding result and the HDLC packet to the FIFO buffer, and the processor 60 reads the decoding result and the HDLC packet from the FIFO buffer.
Preferably, after the FPGA chip 40 reads the WTB waveform digital signal in the current storage area in real time, it determines it to obtain a 0-1 signal, and decodes the 0-1 signal to obtain a decoding result and an HDLC message. That is, the WTB waveform digital signal of the physical layer is converted into the HDLC packet of the data link layer, so that the processor 60 can analyze and process the WTB communication fault problem.
The WTB waveform recorder provided in the first embodiment of the present invention may further include an upper computer 70. The upper computer 70 is connected with the processor 60 of the waveform recorder through a network port. The upper computer 70 reads the WTB waveform digital signal recorded in the memory 50 when the WTB communication is abnormal through the processor 60, performs waveform display on the WTB waveform digital signal when the WTB communication is abnormal, and analyzes the WTB waveform digital signal when the WTB communication is abnormal to generate a WTB waveform abnormal message.
Specifically, after the train stops, the upper computer 70 downloads, through the processor 60, all WTB waveform digital signals recorded in the memory 50 when the WTB communication is abnormal, then performs waveform display and waveform analysis on the WTB waveform digital signals, and generates message data for convenient analysis.
Preferably, the upper computer 70 may configure the recording triggering logic of the processor 60, not only limited to the WTB communication abnormal time, but also perform different types of waveform recording triggering through the HDLC message data. For example, capturing a real-time waveform of a frame during special message transmission. Specifically, the upper computer 70 configures the processor 60 to record the WTB waveform digital signal corresponding to the preset HDLC packet into the memory 50, and perform waveform display on the WTB waveform digital signal.
Although the WTB waveform recorder provided in the first embodiment has high sampling real-time performance, the WTB communication diagnosis and the strategy of only retaining the latest 1 mbyte WTB waveform digital signal solve the problems of large data volume and high requirement on recording transmission speed in the waveform recording process. Due to the adoption of the cheap ADC chip and the DDR3 memory chip, the waveform recording of the WTB communication is realized at lower cost and cost, and the requirements of vehicle-mounted embedded equipment can be met. Moreover, the WTB waveform recorder of the present embodiment is more professional and less costly, since it is directed to WTB physical layer waveform recording.
Furthermore, the upper computer is used for carrying out waveform display and waveform analysis on the WTB waveform digital signal when the WTB communication is abnormal, and generating message data for convenient analysis, so that the WTB communication fault in the train running process can be visually analyzed.
Example two
Fig. 2 is a flowchart illustrating a WTB waveform recording method according to a second embodiment of the invention. The operation of the WTB waveform recorder shown in fig. 1 will be described in detail with reference to fig. 2. As shown in fig. 2, the following steps S210-S270 may be included.
In step S210, the WTB interface circuit 10 continuously acquires the WTB waveform signal on the WTB bus. The WTB waveform signal on the WTB bus acquired there represents the WTB waveform signal of the physical layer.
In step S220, the ADC chip 20 digitally samples the WTB waveform signal acquired by the WTB interface circuit 10 in real time to obtain a WTB waveform digital signal.
In order to meet the requirement of analyzing the WTB waveform signal of the physical layer, the sampling rate of the WTB waveform signal at least needs 60Mps, and the sampling precision adopts 14 bits. Thus, the sampling rate of the ADC chip 20 is at least 60 Mps. Optionally, the ADC chip 20 is a high-speed ADC chip with a sampling rate of 60 Mps. In order to save cost, the ADC chip 20 may be two medium-speed ADC chips with a sampling rate of 30Mps, but is not limited to two medium-speed ADC chips with a sampling rate of 30Mps, and may also be more than two low-speed ADC chips, as long as it meets the requirement that the total sampling rate is at least 60 Mps.
In step S230, the FPGA chip 40 continuously and cyclically writes the WTB waveform digital signal sampled by the ADC chip 20 into any one of the storage areas of the RAM 30. A DMA circuit is arranged in the FPGA chip 40, and the FPGA chip 40 writes the WTB waveform digital signal sampled by the ADC chip 20 into the RAM30 through the DMA circuit.
RAM30 is divided into multiple chip memory partitions, each of which is 1 mbyte in size. The RAM30 includes at least two storage areas. Specifically, the FPGA chip 40 writes the WTB waveform digital signal sampled by the ADC chip 20 into the current partition, and then starts writing from the head, and continuously updates the WTB waveform digital signal in the current partition, so that the WTB waveform digital signal with the latest 1 mbyte is always maintained.
Preferably, the RAM30 is a DDR3 memory chip, and the memory of the DDR3 memory chip requires more than 2M bytes, because it is cheaper and 128M byte DDR3 memory chip can be used. The DDR3 memory chip can only operate 1M byte address at a time, and when the 1M byte is fully written, writing is started from the head, so that the DDR3 memory chip always keeps 1M byte latest waveform data. Suppose the current memory block number is i, the memory base address is 1M × i, the relative offset range of the memory address is 0x00000-0xfffff, and the actual current access address is the memory base address plus the offset address, wherein the offset address circulates in the relative offset range of the memory address.
In step S240, the FPGA chip 40 reads the WTB waveform digital signal in the current storage area in real time and performs decoding processing on the WTB waveform digital signal to generate an HDLC packet. Preferably, the FPGA chip 40 reads the WTB waveform digital signal in the current storage area in real time, determines the WTB waveform digital signal to obtain a 0-1 signal, and decodes the 0-1 signal to obtain a decoding result and an HDLC message. That is, the WTB waveform digital signal of the physical layer is converted into the HDLC packet of the data link layer, so that the processor 60 can analyze and process the WTB communication fault problem.
In step S250, when it is detected that a complete frame of HDLC packet is generated, an interrupt command is issued to notify the processor 60 to read the HDLC packet. A FIFO buffer is provided in the processor 60, and the FPGA chip 40 issues an interrupt instruction to the processor 60 and sends the decoding result and the HDLC packet to the FIFO buffer.
In step S260, the processor 60 reads the HDLC packet and determines whether the WTB communication is abnormal according to the HDLC packet, if so, step S270 is performed, and if not, step S230 is performed. The processor 60 reads the decoding result and the HDLC packet from the FIFO buffer.
In step S270, the FPGA chip 40 is notified to stop writing the WTB waveform digital signal into the current storage area, and is switched to another storage area to continue writing the WTB waveform digital signal.
The above steps S230 to S270 are performed in a loop. For example, the FPGA chip 40 continuously and cyclically writes the WTB waveform digital signal sampled by the ADC chip 20 into the first memory block of the DDR3 memory chip, when the WTB communication is abnormal, stops writing the WTB waveform digital signal into the first memory block, and switches to the next memory block (i.e., the second memory block) to continuously and cyclically write the new WTB waveform digital signal into the second memory block. And when the WTB communication is abnormal next time, stopping writing the WTB waveform digital signal into the second memory block, and switching to the first memory block to continuously and circularly write the new WTB waveform digital signal into the first memory block. The first memory block and the second memory block are used alternately.
In step S280, the processor 60 records the WTB waveform digital signal in the current storage area at the time of the WTB communication abnormality into the memory 50 through the FPGA chip 40. Specifically, the processor 60 transmits the WTB waveform digital signal in the current storage area when the WTB communication is abnormal to the FIFO buffer through the FPGA chip 40. The processor 60 records the WTB waveform digital signal in the FIFO buffer when the WTB communication is abnormal in the memory 50.
The embodiment further comprises the following steps: the upper computer 70 reads the WTB waveform digital signal recorded in the memory 50 when the WTB communication is abnormal through the processor 60, performs waveform display on the WTB waveform digital signal when the WTB communication is abnormal, and analyzes the WTB waveform digital signal when the WTB communication is abnormal to generate a WTB waveform abnormal message.
Specifically, after the train stops, the upper computer 70 downloads, through the processor 60, all WTB waveform digital signals recorded in the memory 50 when the WTB communication is abnormal, then performs waveform display and waveform analysis on the WTB waveform digital signals, and generates message data for convenient analysis.
Preferably, the upper computer 70 may configure the recording triggering logic of the processor 60, not only limited to the WTB communication abnormal time, but also perform different types of waveform recording triggering through the HDLC message data. For example, capturing a real-time waveform of a frame during special message transmission. Specifically, the upper computer 70 configures the processor 60 to record the WTB waveform digital signal corresponding to the preset HDLC packet into the memory 50, and perform waveform display on the WTB waveform digital signal.
Although the WTB waveform recording method provided in the second embodiment has high sampling real-time performance, the WTB communication diagnosis and the strategy of only retaining the latest 1 mbyte WTB waveform digital signal solve the problems of large data volume and high requirement for recording transmission speed in the waveform recording process. Due to the adoption of the cheap ADC chip and the DDR3 memory chip, the waveform recording of the WTB communication is realized at lower cost and cost, and the requirements of vehicle-mounted embedded equipment can be met. Moreover, the WTB waveform recorder of the present embodiment is more professional and less costly, since it is directed to WTB physical layer waveform recording.
Furthermore, the upper computer is used for carrying out waveform display and waveform analysis on the WTB waveform digital signal when the WTB communication is abnormal, and generating message data for convenient analysis, so that the WTB communication fault in the train running process can be visually analyzed.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A WTB waveform recorder, comprising:
the WTB interface circuit is connected with the WTB bus and is used for continuously acquiring WTB waveform signals on the WTB bus;
the ADC chip is connected with the WTB interface circuit and is used for digitally sampling the WTB waveform signal acquired by the WTB interface circuit in real time to obtain a WTB waveform digital signal;
a RAM including two storage areas;
the FPGA chip is respectively connected with the ADC chip and the RAM and is used for continuously writing the WTB waveform digital signals sampled by the ADC chip into any storage area of the RAM in a circulating manner; when the WTB communication is abnormal, stopping writing the WTB waveform digital signal into the current storage area, and switching to another storage area to continue writing the WTB waveform digital signal;
a memory;
the processor is respectively connected with the FPGA chip and the memory and is used for recording the WTB waveform digital signals in the current storage area in case of WTB communication abnormality into the memory through the FPGA chip;
the FPGA chip is also used for reading WTB waveform digital signals in a current storage area in real time, decoding the WTB waveform digital signals to generate an HDLC message, and sending an interrupt instruction to inform the processor to read the HDLC message when detecting that a complete frame of HDLC message is generated; and the processor judges whether the WTB communication is abnormal or not according to the HDLC message.
2. The WTB waveform recorder according to claim 1, wherein the FPGA chip reads the WTB waveform digital signal in the current storage area in real time, determines the WTB waveform digital signal to obtain a 0-1 signal, and decodes the 0-1 signal to obtain a decoding result and an HDLC message.
3. The WTB waveform recorder according to claim 2, wherein a FIFO buffer is provided in the processor, the FPGA chip sends the decoding result and HDLC packets to the FIFO buffer, and the processor reads the decoding result and HDLC packets from the FIFO buffer.
4. The WTB waveform recorder according to claim 3, wherein the FPGA chip transmits WTB waveform digital signals in a current storage area when WTB communication is abnormal to the FIFO buffer, and the processor records the WTB waveform digital signals in the FIFO buffer when WTB communication is abnormal to the memory.
5. The WTB waveform recorder according to claim 1, wherein a DMA circuit is provided in the FPGA chip, and the FPGA chip writes the WTB waveform digital signals sampled by the ADC chip into the RAM through the DMA circuit.
6. The WTB waveform recorder according to claim 1, wherein the ADC chip has a sampling rate of at least 60 Mps; the RAM is a DDR3 memory chip.
7. The WTB waveform recorder according to claim 1, further comprising:
and the upper computer is connected with the processor and used for reading the WTB waveform digital signals recorded in the memory when the WTB communication is abnormal, performing waveform display on the WTB waveform digital signals when the WTB communication is abnormal, analyzing the WTB waveform digital signals when the WTB communication is abnormal and generating WTB waveform abnormal messages.
8. The WTB waveform recorder according to claim 1, wherein the host computer is further configured to configure the processor to record WTB waveform digital signals corresponding to preset HDLC messages into the memory and perform waveform display on the WTB waveform digital signals.
9. A WTB waveform recording method, comprising the steps of:
the WTB interface circuit continuously acquires WTB waveform signals on a WTB bus;
the ADC chip performs digital sampling on the WTB waveform signal acquired by the WTB interface circuit in real time to obtain a WTB waveform digital signal;
the FPGA chip continuously and circularly writes WTB waveform digital signals sampled by the ADC chip into any storage area of the RAM;
the FPGA chip reads the WTB waveform digital signal in the current storage area in real time and decodes the WTB waveform digital signal to generate an HDLC message;
when detecting that a frame of complete HDLC message is generated, sending an interrupt instruction to inform the processor to read the HDLC message;
when the processor judges that the WTB communication is abnormal according to the HDLC message, the processor informs the FPGA chip to stop writing the WTB waveform digital signal into the current storage area and switches to another storage area to continue writing the WTB waveform digital signal;
and the processor records the WTB waveform digital signals in the current storage area when the WTB communication is abnormal into the memory through the FPGA chip.
10. The WTB waveform recording method according to claim 9, wherein the FPGA chip reads the WTB waveform digital signal in the current storage area in real time, determines the WTB waveform digital signal to obtain a 0-1 signal, and decodes the 0-1 signal to obtain a decoding result and an HDLC packet.
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| CN112631987A (en) * | 2020-12-24 | 2021-04-09 | 合肥埃科光电科技有限公司 | FPGA target waveform grabbing method and device |
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