CN112118144B

CN112118144B - Ethernet data frame output method and system

Info

Publication number: CN112118144B
Application number: CN201910531833.3A
Authority: CN
Inventors: 贺昀彦; 陈飞月
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd
Priority date: 2019-06-19
Filing date: 2019-06-19
Publication date: 2022-04-29
Anticipated expiration: 2039-06-19
Also published as: CN112118144A

Abstract

The invention discloses an Ethernet data frame output method and system, and relates to the technical field of communication. The Ethernet data frame output method comprises the following steps: the processor receives an output instruction issued by the debugging host and forwards the output instruction to the FPGA; or the processor and the FPGA respectively store preset instructions; the FPGA responds to the output instruction or the preset instruction, and at least one Ethernet data frame processed by the FPGA is captured and cached from the frame header; the processor sends a report signal; the FPGA responds to the report signal, reports the cache data in the storage area in which each Ethernet data frame is stored to the CPU bus, and then stores the cache data in the next captured Ethernet data frame; and the processor sends the reported cache data to the debugging host. The invention ensures to obtain accurate Ethernet data frames.

Description

Ethernet data frame output method and system

Technical Field

The invention relates to the technical field of communication, in particular to an Ethernet data frame output method and system.

Background

In network devices, due to the flexibility and high performance of Field Programmable Gate Arrays (FPGAs), more and more processing of ethernet data frames is put into the FPGAs to be implemented. When the processing function of the ethernet data frame of the FPGA is verified or fault location is performed, the ethernet data frame received and processed by the FPGA needs to be captured and reported to a debugging host for monitoring by developers.

The Central Processing Unit (CPU) in the network device can control the FPGA to capture the ethernet data frame and store the ethernet data frame in the buffer, and then read the captured ethernet data frame from the buffer and report the captured ethernet data frame. However, the capturing and reporting time of the ethernet data frame is not synchronous, and the rate may also be different, and it may happen that the capturing starts to be reported when half of the capturing is performed, so that the first half of all the reported data is the new data currently captured and buffered, and the second half of all the reported data is the old data previously captured and buffered. It may also happen that the acquisition is restarted when the reporting has progressed to half, resulting in the first half of the report being old data and the second half being new data. Therefore, it is difficult to obtain an accurate monitoring result.

If the time for capturing and reporting each ethernet data frame is controlled by using the CPU, the capturing and reporting time is difficult to master under the condition that the update of the ethernet data frame is slow or unknown, and under the condition that there are many ethernet data frames, more control commands are required for capturing and reporting each time, so that the operation is complicated.

Disclosure of Invention

In view of the defects in the prior art, an object of the present invention is to provide a method and a system for outputting ethernet data frames, which ensure to obtain accurate ethernet data frames.

The invention provides an Ethernet data frame output method, which comprises the following steps:

the processor receives an output instruction issued by the debugging host and forwards the output instruction to the FPGA; or the processor and the FPGA respectively store preset instructions;

the FPGA responds to the output instruction or the preset instruction, and at least one Ethernet data frame processed by the FPGA is captured and cached from the frame header;

the processor sends a report signal;

the FPGA responds to the report signal, reports the cache data in the storage area where each Ethernet data frame is stored to a CPU bus, and then stores the cache data in the next captured Ethernet data frame;

and the processor sends the reported cache data to the debugging host.

On the basis of the above technical solution, the capturing and buffering at least one ethernet data frame processed by the FPGA from the frame header includes:

according to the reset control signal, the report signal, the frame interface signal of the frame data interface and the current read or write address in the storage area, establishing a state machine and generating a read or write control effective signal, wherein the state machine comprises a reset state and a capture report state;

when the write control effective signal is generated in the capture reporting state, capturing and caching the Ethernet data frame; and when the read control effective signal is generated, reporting the cache data.

On the basis of the technical scheme, the capture reporting state comprises states to be captured, to be reported and reported which are converted in sequence, wherein the write control effective signal is generated in the capture state; and generating the effective reading control signal in the states of waiting to be reported and reporting.

On the basis of the technical scheme, the method further comprises the following steps:

in the reset state, responding to the report signal, and generating and reporting a reset code pattern;

and when the effective reading control signal is not generated, generating and reporting incomplete reading, no sampling to a frame, no sampling to a full frame or no sampling to a full frame code pattern in response to the report signal.

On the basis of the above technical solution, the starting to capture and buffer the ethernet data frame includes:

and generating frame data invalid, frame tail dislocation or an invalid frame tail code pattern according to the frame interface signal, and storing the frame data invalid, the frame tail dislocation or the invalid frame tail code pattern in the storage area.

when the data bit width of the frame data interface is smaller than the data bit width of the CPU bus, performing serial-parallel conversion on the data output by the frame data interface and writing the data into the storage area;

the beginning to report the cached data includes:

and when the data bit width of the frame data interface is greater than the data bit width of the CPU bus, reading the cache data from the storage area, and reporting the cache data after parallel-serial conversion.

converting the data of the small end sequence output by the frame data interface into the data of the large end sequence according to bytes and caching the data;

the beginning to report the cached data further includes:

and when the data bit width of the frame data interface is greater than the data bit width of the CPU bus, reading the cache data from the storage area, and reporting the cache data after reverse order conversion.

The invention also provides an Ethernet data frame output system which is arranged in network equipment, wherein the network equipment comprises a processor and an FPGA (field programmable gate array), and the system comprises a processing module arranged in the processor and an acquisition module arranged in the FPGA;

the processing module is used for receiving an output instruction issued by the debugging host or storing a preset instruction; issuing the output instruction and a report signal to the acquisition module; the debugging host is also used for sending the cache data reported by the acquisition module to the debugging host;

the acquisition module is used for responding to the output instruction or storing the preset instruction, and capturing and caching at least one Ethernet data frame processed by the FPGA from a frame header; and the CPU is also used for reporting the cache data in the storage area where each Ethernet data frame is stored to the CPU bus in response to the report signal and then storing the next captured Ethernet data frame.

On the basis of the technical scheme, the acquisition module comprises a control unit, a storage unit and at least one execution unit, wherein each execution unit comprises a capturing and reporting unit;

the control unit is used for receiving the output instruction or storing the preset instruction and distributing a storage area in the storage unit for each execution unit; the execution unit is also used for informing the execution unit to respond to the output instruction and the report signal or execute the preset instruction;

the execution unit is used for establishing a state machine and generating a read-write control effective signal according to the reset control signal, the report signal, a frame interface signal of a frame data interface and a current read-write address in the storage area, wherein the state machine comprises a reset state and a capture report state;

the capturing and reporting unit is used for capturing and caching the Ethernet data frame when the writing control effective signal is generated in the capturing and reporting state; and when the read control effective signal is generated, reporting the cache data.

On the basis of the technical scheme, when the acquisition module comprises one execution unit, the control unit is also used for generating a current read or write address in the storage area and sending the current read or write address to the state machine;

when the acquisition module comprises more than two execution units, each execution unit also comprises an address mapping unit; the control unit is also used for informing the address mapping unit of the storage area; the address mapping unit is used for generating a current read or write address in the storage area and sending the current read or write address to the control unit and the state machine.

On the basis of the above technical solution, the capture reporting unit is further configured to generate a frame data invalid, frame tail misplaced or invalid frame tail pattern according to the frame interface signal and store the frame data invalid, frame tail misplaced or invalid frame tail pattern in the storage area when the write control signal is valid.

On the basis of the above technical solution, the capture reporting unit is further configured to respond to the reporting signal in the reset state, and generate and report a reset pattern; and when the effective reading control signal is not generated, generating and reporting incomplete reading, no sampling to a frame, no sampling to a full frame or no sampling to a full frame code pattern in response to the report signal.

On the basis of the technical scheme, each execution unit further comprises a conversion unit;

the conversion unit is used for performing serial-parallel conversion on the data output by the frame data interface and then transmitting the data to the capturing and reporting unit when the data bit width of the frame data interface is smaller than the data bit width of the CPU bus; the data processing device is also used for converting the data of the small end sequence output by the frame data interface into the data of the large end sequence according to bytes;

and the acquisition module is also used for reading the cache data from the storage area and reporting the cache data after parallel-serial conversion and reverse order conversion when the data bit width of the frame data interface is greater than the data bit width of the CPU bus.

Compared with the prior art, the embodiment of the invention receives the output instruction issued by the debugging host through the processor and forwards the output instruction to the FPGA; or the processor and the FPGA respectively store preset instructions; the FPGA responds to the output instruction or the preset instruction, and at least one Ethernet data frame processed by the FPGA is captured and cached from the frame header; the processor sends a report signal; the FPGA responds to the report signal, reports the cache data in the storage area in which each Ethernet data frame is stored to the CPU bus, and then stores the cache data in the next captured Ethernet data frame; and the processor sends the reported cache data to the debugging host to ensure that an accurate Ethernet data frame is obtained.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of an ethernet data frame output method according to an embodiment of the present invention;

fig. 2 is a flowchart of an ethernet frame output method according to another embodiment of the present invention;

fig. 3 is a flowchart of an ethernet frame output method according to yet another embodiment of the present invention;

FIG. 4A is a diagram illustrating a state transition of a state machine according to an embodiment of the present invention;

FIG. 4B is a state transition diagram of another state machine according to an embodiment of the present invention;

fig. 5 is an application diagram of a reporting system of an ethernet data frame according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a system for reporting an ethernet data frame according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a system for reporting ethernet frames according to another embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and the embodiments.

The embodiment of the invention provides an Ethernet data frame output method, which is used for reporting at least one Ethernet data frame processed by an FPGA in network equipment to a debugging host, wherein the network equipment further comprises a processor, the processor comprises a CPU, and the Ethernet data frame processed by the FPGA can be a test frame or an Ethernet data frame of actual transmission service of the network equipment.

Referring to fig. 1, the ethernet data frame output method includes:

the S1 processor receives an output instruction issued by the debugging host and forwards the output instruction to the FPGA; or the processor and the FPGA respectively store preset instructions.

And S2, responding to the output instruction or the preset instruction by the FPGA, and capturing and caching at least one Ethernet data frame processed by the FPGA from the frame header.

The S3 processor issues a report signal.

And S4, responding to the report signal by the FPGA, reporting the cache data in the storage area in which each Ethernet data frame is stored to the CPU bus, and then storing the cache data in the next captured Ethernet data frame.

And the S5 processor sends the reported cache data to the debugging host.

The processor of the network device performs steps S1, S3, and S5.

In step S1, the output command may include information of the ethernet frames that need to be reported, for example, the total number of ethernet frames to be reported may be 1 or more ethernet frames.

The output instruction may also simply notify the processor and the FPGA to report a predetermined number of ethernet data frames, where the predetermined number may be included in a preset instruction pre-stored in the FPGA, and the preset instruction please refer to the description of the other embodiments. The FPGA prestores the preset number of the Ethernet data frames without debugging a host and issuing the preset number by a processor, thereby simplifying commands.

In step S1, the processor issues an output instruction to the FPGA only once to instruct the FPGA to report the specified number of ethernet data frames, and does not need to issue an output instruction to each ethernet data frame to control the capturing time, thereby reducing the number of commands issued by the processor, simplifying the command processing in the reporting process, and facilitating the improvement of the reporting efficiency.

In step S3, the processor issues a report signal to the FPGA to notify the FPGA to report the buffered data to the CPU bus.

Specifically, the processor may determine the number of times of sending the report signal according to the total number of the ethernet data frames to be reported and the number of the ethernet data frames already reported by the FPGA. The reporting signal is sent after the output command, and a predetermined time interval may exist between the output command and the reporting signal and between two adjacent reporting signals.

In step S5, the processor may send the cached data to the debugging host through a Secure Shell (SSH) protocol, a Telnet (Telnet) protocol, an ethernet interface, or a serial port, without limitation.

The execution of steps S3 to S5 may be implemented in one of the following manners, or otherwise, without limitation:

and executing the steps S3 to S4 once, and if the FPGA reports that the specified number of ethernet data frames is completed, the processor executes the step S5, and then the process is ended.

And (4) performing the steps S3 to S4 for two times or more, reporting the specified number of Ethernet data frames by the FPGA, and performing the step S5 by the processor to end.

The steps S3 to S5 are performed twice or more, and are finished when the processor finishes outputting the specified number of ethernet data frames.

The embodiment of the invention receives an output instruction issued by a debugging host through a processor and forwards the output instruction to the FPGA; or the processor and the FPGA respectively store preset instructions; the FPGA responds to the output instruction or the preset instruction, and at least one Ethernet data frame processed by the FPGA is captured and cached from the frame header; the processor sends a report signal; the FPGA responds to the report signal, reports the cache data in the storage area in which each Ethernet data frame is stored to the CPU bus, and then stores the cache data in the next captured Ethernet data frame; and the processor sends the reported cache data to the debugging host to ensure that an accurate Ethernet data frame is obtained.

Referring to fig. 2, in one embodiment, an ethernet data frame output method includes:

s100, the processor receives an output instruction issued by the debugging host.

And S110, the processor forwards the output instruction issued by the debugging host to the FPGA.

And S120, receiving an output instruction by the FPGA.

S130, the Ethernet data frames processed by the FPGA are processed in batch or in parallel.

Each batch process captures and buffers at least one ethernet data frame starting from the frame header. Parallel processing captures and buffers each ethernet data frame starting from the frame header.

And S140, the processor issues a report signal to the FPGA.

S150, the FPGA responds to the report signal and reports the cache data to the CPU bus.

And S160, the processor sends the reported cache data to the debugging host.

The processor performs steps S100, S110, S140, and S160.

The FPGA executes the steps S120, S130 and S150, wherein each batch of processing captures and caches at least one Ethernet data frame from the frame head, and then responds to a reporting signal sent by the processor, reports the cached data to the CPU bus, and then executes the next batch of processing.

Specifically, the number of ethernet data frames processed in each batch may be 1, 2, or more than 2. When the number of ethernet data frames processed in each batch is 2 or more than 2, all ethernet data frames may be captured and buffered simultaneously in a parallel manner in each batch, or each ethernet data frame may be captured and buffered one by one, without limitation.

In some specific scenes, a plurality of ethernet data frames which are continuous according to the time sequence need to be reported, and because the time rates of the capture and the report of the FPGA are asynchronous, the complete report from the first frame to the last frame is allowed only after all the frames are captured and cached through batch processing, that is, the first frame is not allowed to be reported before the capture of the last frame is completed, so that the continuity of all the reported ethernet data frames according to the time sequence is ensured.

And for each Ethernet data frame processed in parallel, capturing and buffering the Ethernet data frame from the frame head, responding to a reporting signal, reporting the buffered data to a CPU bus, and processing the next Ethernet data frame.

Specifically, when the total number of ethernet data frames to be reported is 2 or more than 2, multiple ethernet data frames may be captured and buffered simultaneously in a parallel manner, which is different from the batch processing: after the first frame is captured, the reporting of the first frame is allowed, that is, the reporting of the first frame can be performed simultaneously with the capturing of the second frame and independently performed, and this way cannot guarantee that all frames are continuous according to the time sequence, but does not need to wait for enough frames, so that the reporting is more common.

In step S150, after the reporting is completed, the FPGA may also clear the reported ethernet data frame to store the ethernet data frame captured later.

Specifically, after steps S130 to S150 are all executed, the processor finally executes step S160. Alternatively, steps S130 to S150 are performed in synchronization with step S160, but not limited thereto.

Specifically, the CPU bus typically includes control signal lines for clock, chip select, address, write data, read data, and read/write enable. Each read and write command typically lasts for several beats. A CPU in the processor drives control signal lines to write commands to the FPGA or read data from the FPGA. The CPU writes an output instruction into the FPGA by driving a clock, chip selection, an address, write data and write enable; the CPU drives the clock, chip select, address and read enable to send a report signal, and the FPGA controls the read data to read the cache data and report the cache data to the CPU bus.

The processor and the FPGA receive and respond to an output instruction issued by a debugging host, and carry out batch processing or parallel processing on Ethernet data frames; in each batch of processing, the FPGA captures and caches at least one Ethernet data frame from a frame header, then responds to a reporting signal sent by a processor, reports the cached data to a CPU bus, and then executes the next batch of processing; for each Ethernet data frame processed in parallel, the FPGA starts to capture and buffer from the frame head, then responds to a reporting signal, reports the buffer data to a CPU bus, and processes the next Ethernet data frame; the processor sends the reported cache data to the debugging host, thereby avoiding the problem that the capturing and reporting time of the Ethernet data frame are not synchronous, simplifying the command processing in the reporting process, being beneficial to improving the reporting efficiency and ensuring that the accurate Ethernet data frame is obtained.

In other embodiments, the output instruction in step S110 may also include cycle output information and a total number of ethernet frames to be output in each cycle, where the cycle output information includes a cycle number or a cycle end condition. After performing step S160, the ethernet data frame output method further includes:

s170, judging whether the circulation times are finished or a circulation finishing condition is reached, if so, finishing; if not, the process returns to step S130.

The embodiment of the invention can test and verify the Ethernet data frame processing function of the FPGA at the design debugging stage, can also be built in the formal version of the FPGA, can be debugged on line without power off, can not destroy the field measurement of the frame interface signal in the FPGA on the engineering, and can be used for positioning the fault on the engineering.

In another embodiment of the present invention, referring to fig. 3, an ethernet data frame output method includes:

s200 the processor saves a first preset instruction.

And S210, the FPGA stores a second preset instruction.

Specifically, the first preset instruction and the second preset instruction both include a predetermined number of ethernet data frames output at a time, and the first preset instruction and the second preset instruction may be the same or different.

Specifically, the first preset instruction and the second preset instruction are both predefined in the code and then burned into the hardware.

The processor sends a report signal to the FPGA after delaying for a period of time after the FPGA is started or reset according to the first preset instruction, and informs the FPGA to report a preset number of Ethernet data frames. And the FPGA directly reports the Ethernet data frames of the preset number after the FPGA is started or reset without issuing an output instruction by the processor according to the second preset instruction.

And S220, the FPGA receives a starting signal or a reset recovery signal.

After the FPGA is started or reset, a start signal or a reset recovery signal is received, where the reset recovery signal may be issued by the CPU or triggered by hardware on the network device.

And S230, the FPGA carries out batch processing or parallel processing on the Ethernet data frames.

And S240, the processor issues a report signal to the FPGA.

And S250, responding to the report signal by the FPGA, and reporting the cache data to the CPU bus.

And S260, the processor sends the reported cache data to the debugging host.

Steps S230 to S260 are substantially the same as steps S130 to S160, and are not described herein again. The detailed description of steps S130 to S160 hereinafter also applies to steps S230 to S260.

In other embodiments, the first preset instruction and the second preset instruction in steps S200 and S210 may further include cycle output information and a total number of ethernet data frames to be output in each cycle, where the cycle output information includes a cycle number or a cycle end condition. After performing step S260, the ethernet data frame output method further includes:

s270, judging whether the circulation times are finished or a circulation finishing condition is reached, if so, finishing; if not, the process returns to step S230.

In other embodiments, step S220 may not be performed.

The embodiment of the invention can verify the Ethernet data frame processing function of the FPGA at the design debugging stage, can be built in the formal version of the FPGA, can debug on line without power off, can not destroy the field measurement of the frame interface signals in the FPGA on the engineering, and can be used for positioning the faults on the engineering.

In an optional implementation manner, the step S130 may further include:

s131 allocates a storage area for each ethernet frame.

Specifically, under the condition that batch processing or parallel processing requires capturing of a plurality of frames, the storage areas may be allocated according to the time sequence of frame interface output frames.

And marking the frames output by the frame interface, wherein the first frame to the frame interface is marked as 1, the second frame to the frame interface is marked as 2, the Nth frame is marked as N, the (N + 1) th frame is marked as 1, and the (N + 2) th frame is marked as 2, and repeating the steps.

And equally dividing all address spaces into N storage areas, distributing the 1 st storage area for the frame marked as 1, and distributing the Nth storage area for the frame marked as N.

Thus the frame marked 1 is the first in N frame periods and the allocated address space is the first 1 st. The frame marked N is the most backward in N frame periods, and the allocated address space is the most backward nth.

The method comprises the steps of capturing an Ethernet data frame with a specific length by allocating a storage area, and completing if the length of the captured Ethernet data frame is less than the length, and exceeding truncation.

S132, according to the reset control signal, the frame interface signal of the frame data interface and the address of the currently read or written storage area, a state machine is established and a read or write control effective signal is generated, wherein the state machine comprises a reset state and a capture reporting state.

Specifically, the frame data interface is used for outputting an ethernet data frame processed by the FPGA, that is, an interface of the ethernet data frame in the FPGA. The frame interface signal generally includes: the frame data interface comprises a frame header signal, a frame tail signal, a frame data effective signal, a frame data signal and a frame tail byte mask signal, wherein when the rate of the frame data interface is upgraded, the data bit width is generally increased, and the clock frequency of the frame data interface is increased.

Referring to fig. 4A, the state machine includes a reset state and a capture report state. When the FPGA is reset, the reset control signal is effective. The reset control signal has the highest priority, and enters a reset state as long as the reset control signal is effective; when the reset recovery signal is received, the reset control signal is invalid, and the acquisition reporting state can be entered.

Specifically, a corresponding state machine may be established for each ethernet data frame.

S133 starts capturing and buffering the ethernet data frame when the write control valid signal is generated in the capture report state.

Further, the step S150 may further include:

s151 starts to report the buffered data when the read control valid signal is generated in the capture report state.

Specifically, in the capture reporting state, a write control valid signal is generated first, a capture frame header signal is valid, an ethernet data frame is captured and cached, and writing is performed sequentially from a head address of the storage area until a current write address of the storage area reaches a tail address of the storage area. And then generating a reading control effective signal according to the received report signal, and sequentially reading the cache data from the head address of the storage area until the current reading address reaches the tail address of the storage area.

The embodiment of the invention realizes the foolproof design through the state machine and the effective reading or writing control signal, namely, when the effective reading control signal is generated, reporting is carried out, the fact that complete and consistent Ethernet data frames are read is guaranteed, and invalid reading operation and data updating are automatically shielded.

Further, the capturing and reporting states include 4 states that are sequentially converted: starting from the state to be captured, entering the state to be captured again after the state to be captured, the state to be reported and the state to be reported are finished, and continuously circulating. Generating a write control valid signal in the capture-in-progress state; and generating a read control effective signal in the states to be reported and in the process of reporting.

Referring to fig. 4B, the state machine includes a reset state and states to be captured, to be reported, and to be reported, which are sequentially converted.

A. As long as the reset control signal rst is active, rst is equal to 1' b1, and a reset state is entered. If the state transition (state _ trs) occurs: rst is cancelled, and rst is valid as 1' b0 and is converted into a state to be captured (state).

B. In a state to be captured (state), if a state transition (state _ trs) condition occurs: the capture frame header signal (| fs _ i [ div _ par-1:0]) is valid and is converted into a capture-in-progress state.

C. In the capture state (state), if a state transition condition occurs (state _ trs), the address (adr _ w) of the currently written storage area is filled to the end address (ending _ adr) of the storage area to be validated, that is, the address (adr _ w) becomes the ending _ adr, and the state is changed to the state to be reported (state _ prerd).

D. In the state to be reported (state ═ prerd), the condition of state transition (state _ trs) occurs: the read operation of the head address (sop _ adr) of the memory area is:

(re _ bmu & (adr _ bmu single _ adrwidth-1:0 ═ sop _ adr)) takes effect and the state transitions to reporting (state ═ rding).

E. In reporting a state (state) and a condition that a state transition (state _ trs) occurs: the read operation of the last address of the memory area, namely:

(re _ bmu & (adr _ bmu single _ adrwidth-1:0 ═ ending _ adr)) takes effect and the state is changed to be captured (state ═ precap).

Wherein re _ bmu is effective for reporting and reading, adr _ bmu is a reported and read address, and single _ adrwidth is an occupied address bit width reported by each ethernet data frame.

In an alternative embodiment, the step S133 may include:

s1331, when the data bit width of the frame data interface is less than that of the CPU bus, writing the output data of the frame data interface into the storage area after serial-parallel conversion.

The step S151 may further include:

s1511, when the data bit width of the frame data interface is larger than that of the CPU bus, the buffer data is read from the storage area and reported after parallel-serial conversion.

When the data bit width of the frame interface is less than the data bit width of the CPU bus, serial-parallel conversion can be performed during storage. And splicing the frame data of several continuous beats into data with a data bit width of a CPU bus. Therefore, when the data is reported through the CPU bus, invalid data cannot exist in the data reported by each address, and each byte of the reported data corresponds to each byte of the frame data.

When the data bit width of the frame interface is larger than the data bit width of the CPU bus, parallel-serial conversion can be carried out during reporting. And reporting the frame data of each address in the storage area to a CPU bus in a grading way, and ensuring that each byte of the frame data is reported.

In the embodiment of the invention, under the condition that the data bit width of the CPU bus is not equal to the data bit width of the frame interface, the data output by the frame data interface is subjected to serial-parallel conversion or parallel-serial conversion during reporting, so that visual reading is realized and accurate data is obtained.

In an optional implementation manner, the step S133 may further include:

s1332 converts the data in the small endian output from the frame data interface into data in the large endian by byte, and writes the data in the storage area.

The step S151 may further include:

s1512, when the data bit width of the frame data interface is greater than the data bit width of the CPU bus, reading the cache data from the storage area, and reporting after reverse order conversion.

In the implementation manner of S1332, a preset byte order (byte order) parameter value may be provided, which represents a big endian and a small endian when the parameter value is 1 and 0, respectively, and if the input ethernet data frame is a small endian, the ethernet data frame is converted into the big endian, otherwise, the conversion is not required, and the frame data is presented according to the natural reading order.

When the FPGA reports through the CPU bus, under the condition that the data bit width of the CPU bus is not equal to that of the frame interface, if the frame content is stored and reported as it is, reading is not intuitive or the obtained data is not accurate.

In the embodiment of the invention, under the condition that the frame data interface outputs the data of the small end sequence, the data is converted into the data of the large end sequence according to the bytes and is written into the storage area, and when the data bit width of the frame data interface is larger than the data bit width of the CPU bus, the cache data is read from the storage area and is reported after reverse conversion, so that the data which is read intuitively and accurately is obtained.

In an optional implementation manner, the step S133 may further include:

and S1333, generating frame data invalid, frame tail dislocation or invalid frame tail code patterns according to the frame interface signals, and storing the frame data invalid, frame tail dislocation or invalid frame tail code patterns in a storage area.

The frame interface signal generally includes: a frame header signal, a frame trailer signal, a frame data valid signal, a frame data signal, and a frame trailer byte mask signal. The frame data valid signal identifies the beginning to the end of a frame.

In the capture state (state), the capture starts from the effective start of the frame header signal, the frame header is stored in the head address of the storage area, the cache data is sequentially stored in the storage area until the allocated storage area is filled, and the capture is finished.

In the capture state, if the frame data valid signal becomes invalid, generating a frame data invalid code pattern, and writing the frame data invalid code pattern into the current write address of the storage area; if the frame tail signal is valid and the frame data valid signal is invalid, generating an invalid frame tail code pattern, and writing the invalid frame tail code pattern into the current write address of the storage area; and if the frame tail signal is one beat later than the effective signal of the frame data, generating a frame tail dislocation code pattern and writing the frame tail dislocation code pattern into the current writing address of the storage area.

And if the frame is captured completely and the current writing address does not reach the last address of the storage area, continuing to write the frame data invalid pattern until the last address of the storage area.

The step S151 may further include:

s1513 in the reset state, responding to the report signal, generating and reporting a reset code pattern; and when the reading control effective signal is not generated, generating and reporting incomplete reading, no sampling to a frame, no sampling to a full frame or no sampling to a full frame code pattern in response to the reporting signal.

Specifically, in a reset state, if a report signal is received, the FPGA determines whether the report signal starts to be read from an address where a frame header in the storage area is located, and if so, outputs a reset pattern; otherwise, judging that the reported cache data has errors, and outputting an incomplete code reading pattern.

In a state to be captured (state) and a state in capturing (state), if a reporting signal is received, the FPGA judges whether the reporting signal starts to read from an address where a frame header is located in a storage area, if so, the FPGA respectively outputs a non-sampled frame and a non-sampled full-frame code pattern; otherwise, judging that the reported cache data has errors, and outputting an incomplete code reading pattern.

In a state to be reported (state), if a reporting signal is received, the FPGA judges whether the reporting signal starts to be read from an address where a frame header is located in a storage area and starts to be read from an address where the frame header is located of a first execution unit in a batch mode, if not, the FPGA judges that the reported cache data has errors, and outputs an incomplete code reading type; if so, whether capturing is finished in the parallel mode or the batch mode and all execution units are judged, if so, the sampled frame data is output, and if not, all frame code patterns are output without sampling.

In the reporting state (state) if a reporting signal is received, the FPGA judges whether the FPGA is in the parallel mode or the batch mode and starts reading from the frame header address of the first execution unit, if not, the FPGA outputs an incomplete read code pattern, if yes, the FPGA checks whether the FPGA is in the parallel mode or the batch mode and finishes capturing frames of all execution units, if not, the FPGA outputs all the incomplete read code patterns, and if yes, the FPGA outputs read data of the memory.

During batch processing, it is only required to wait for capturing and buffering all frames of the batch, and complete reporting from the first frame to the last frame is allowed, and for the captured and buffered ethernet data frames, the state machines of the ethernet data frames are in a reporting state, and then all frame patterns which are not sampled are generated. For the Ethernet data frame of the batch in the capture state, thenGeneratingThe full frame pattern is not sampled. And generating an un-sampled frame code pattern for the Ethernet data frame in the state to be captured.

During parallel processing, for the captured and cached Ethernet data frames, if the state machines of the Ethernet data frames are in a reporting state, reporting the cached data; and for the Ethernet data frames which are not captured and cached completely, if the state machines of the Ethernet data frames are not in the reporting state, outputting the corresponding code patterns according to the description.

The value of each pattern is not limited, and possible implementations include:

1) and (4) reading the same fixed value by using the parameter preset value for each reported address. For example, in the case of a 32-bit reporting bus, prered ═ 32 'h edded, taping ═ 32' h cacaca, or prered ═ prer (ASCII code, each occupies 1 byte), taping ═ ning.

2) Preset values are used, but each reported address reads a different value. Can be used to express long sentences using ASCII patterns. For example, in the reset state, the reset code pattern repeats "system is resetting." (20 ASCII codes occupy 5 addresses if 32 bits are reported to the bus) according to the read address.

3) Using the configuration port, the value of each code pattern can be changed and defined by the configuration command of the debugging host. The method comprises the two conditions that each reporting address reads the same value and reads different values.

The values of all patterns do not necessarily have to be implemented identically, for example, a frame data null pattern would typically be the first type because a frame end null byte mask in bytes would be expressed.

In the prior art, when data of an ethernet data frame is not output, sometimes the FPGA is in a reset state, sometimes a new ethernet data frame is not received all the time, sometimes action conflicts between a reporting operation and a capturing operation result, sometimes an erroneous reading operation, such as reading from the middle of a frame, etc. If the different exceptions and states are not distinguished, all 0 (initial value of a memory and no processing is needed) is used as a read value, so that the technical personnel cannot distinguish, and the frame processing of the FPGA is difficult to accurately diagnose. If the information is provided through various abnormal states and abnormal counts, more addresses are read, and a diagnosis tool is diagnosed, so that the usability is greatly reduced, and the application range is limited.

The embodiment of the invention indicates the reset state, the non-sampling to frame state, the non-sampling to full frame state and the error reading operation state by outputting the code pattern, and indicates the time sequence relation among the frame start, the data validity and the frame end signal. The frame content, the frame interface time sequence, the captured and reported running state and the abnormal state of the frame interface can be obtained by reading the same section of address only through one-time operation, the reported information is richer, and the accuracy and the reliability of diagnosis are further improved.

The embodiment of the present invention further provides a reporting system for ethernet data frames, which is used to implement the method for outputting ethernet data frames in the above embodiment, and report at least one ethernet data frame processed by an FPGA in a network device to a debugging host, where the reporting system for ethernet data frames includes a processing module disposed in a processor and an acquisition module disposed in the FPGA.

Specifically, the processor includes a CPU, and the processing module may be provided in the CPU, or the processor includes a CPU and a processing module.

Fig. 5 is an application schematic diagram of a reporting system of an ethernet data frame according to an embodiment of the present invention, where at least one frame processing unit is disposed in an FPGA, the frame processing unit may output a processed ethernet data frame through a multi-selector, and the multi-selector is connected to an acquisition module through a frame data interface, or the multi-selector may be selectively connected to a frame filter, and the frame filter is used to filter the ethernet data frame.

The processing module is used for receiving an output instruction issued by the debugging host or storing a preset instruction; issuing an output instruction and a reporting signal to an acquisition module; and the data processing module is also used for sending the cache data reported by the acquisition module to the debugging host.

The acquisition module is used for responding to the output instruction or storing a preset instruction, and capturing and caching at least one Ethernet data frame processed by the FPGA from the frame header; and the CPU is also used for responding to the report signal, reporting the cache data in the storage area storing each Ethernet data frame to the CPU bus, and then storing the next captured Ethernet data frame.

Specifically, the acquisition module is configured to perform batch processing or parallel processing on ethernet data frames processed by the FPGA, wherein in each batch processing, the acquisition module captures and caches at least one ethernet data frame from a frame header, and then responds to a report signal to report the cached data to the CPU bus and then executes the next batch processing; for each Ethernet data frame processed in parallel, the acquisition module starts to capture and buffer from the frame head, and then processes the next Ethernet data frame after reporting the buffer data to the CPU bus in response to the report signal.

Referring to fig. 6, in an alternative embodiment, the acquisition module includes a control unit, a storage unit, and an execution unit, and each execution unit includes a capture reporting unit.

The control unit is used for receiving the output instruction or saving the preset instruction, allocating a storage area in the storage unit for each execution unit, generating a current read or write address in the storage area and sending the current read or write address to the state machine; and the execution unit is also used for informing the execution unit to respond to the output instruction and report a signal or execute a preset instruction.

The execution unit is used for establishing a state machine and generating a read-write control effective signal according to the reset control signal, the report signal, the frame interface signal of the frame data interface and the current read-write address in the storage area, wherein the state machine comprises a reset state and a capture report state.

The capturing and reporting unit is used for capturing and caching the Ethernet data frame when generating a write control effective signal in a capturing and reporting state; and when the read control effective signal is generated, reporting the cache data.

Further, the capturing and reporting state comprises states to be captured, to be reported and reported which are converted in sequence, wherein a write control effective signal is generated in the capturing state; and generating a read control effective signal in the states to be reported and in the process of reporting.

Furthermore, the capturing and reporting unit is further configured to generate a frame data invalid, frame tail misplaced or invalid frame tail code pattern according to the frame interface signal and store the frame data invalid, frame tail misplaced or invalid frame tail code pattern in the storage area when the write control signal is valid.

Furthermore, the capturing and reporting unit is also used for responding to a reporting signal in a reset state and generating and reporting a reset code pattern; and when the reading control effective signal is not generated, generating and reporting incomplete reading, no sampling to a frame, no sampling to a full frame or no sampling to a full frame code pattern in response to the reporting signal.

Further, each execution unit further comprises a conversion unit.

The conversion unit is used for performing serial-parallel conversion on the output data of the frame data interface and transmitting the converted output data to the capturing and reporting unit when the data bit width of the frame data interface is smaller than the data bit width of the CPU bus; and the data processing device is also used for converting the data of the small endian output by the frame data interface into the data of the large endian according to the bytes.

Referring to fig. 7, in an alternative embodiment, the acquisition module includes a control unit, a storage unit and N execution units, where N is a positive integer, and N ≧ 2. Each execution unit comprises a capturing and reporting unit and an address mapping unit.

The control unit is used for receiving the output instruction or storing a preset instruction and distributing a storage area in the storage unit for each execution unit; and the execution unit is also used for informing the execution unit to respond to the output instruction and report a signal or execute a preset instruction.

And marking the frames output by the frame interface, wherein the first frame to the frame interface is marked as 1, the second frame to the frame interface is marked as 2, the Nth frame is marked as N, the (N + 1) th frame is marked as 1, and the (N + 2) th frame is marked as 2, and repeating the steps. The frame labeled 1 allocates the 1 st execution unit and the frame labeled N allocates the nth execution unit.

And dividing all address spaces into N storage areas equally, distributing the 1 st storage area for the 1 st execution unit, and distributing the Nth storage area for the Nth execution unit.

The control unit is also used for informing the address mapping unit of the storage area; the address mapping unit is used for generating the current read or write address in the storage area and sending the current read or write address to the control unit and the state machine.

Further, each execution unit further comprises a conversion unit.

The following description will be given by taking fig. 7 as an example.

A conversion unit: and the data processing device is used for converting the data byte order of the frame data according to the parameters of the data byte order type of the frame data, the data bit width of the frame data interface, the FPGA reported data bit width and the like, and storing the data after serial-parallel change if the data bit width of the frame data interface is less than the FPGA reported data bit width. And reporting the data bit width as the data bit width of the CPU bus by the FPGA.

A capturing and reporting unit: the device is used for generating corresponding code patterns according to different states output by the state machine, the reset initial state of the FPGA and frame interface signals of the captured reporting state and the frame data interface, outputting the frame data to the storage unit and reporting the code patterns and/or the cache data to the CPU bus.

An address mapping unit: the method is used for allocating the address of each frame head, the address range of each frame, the total address range, the maximum capture length of each frame and the capture frame number according to the data bit width of the frame data interface, the FPGA reported data bit width, the capture frame length bit width and the capture total address bit width parameters. Distributing the frame corresponding to each capturing and reporting unit, generating the current writing address of the captured data, and distributing the capturing and reporting unit corresponding to the current reporting address and the corresponding capturing and reporting unit reporting address.

A state machine: the device is used for generating reset, to-be-captured, capturing, to-be-reported and to-be-reported states according to a frame head and a frame tail input by a frame data interface, comparing the current capture length and the maximum capture length of each frame, comparing a read address and the address of the current frame head, comparing the address range of the current frame and the current state, and generating effective write and read control signals.

A storage unit: when generating a write control effective signal, receiving buffer data comprising rearranged frame data and code patterns according to a frame header signal and a frame tail signal, and sequentially writing the buffer data into a current write address output by an address mapping unit; otherwise, the frame interface signal is ignored. When generating the effective reading control signal, the control unit receives the current reading address output by the address mapping unit, reads the cache data in the corresponding address of the storage unit and sends the cache data to the capturing and reporting unit, otherwise, the capturing and reporting unit outputs the code pattern.

A control unit: the device comprises a storage unit, a control unit and a control unit, wherein the storage unit is used for receiving an output instruction or storing a preset instruction, performing parameter calculation and allocating a storage area in the storage unit for each execution unit; and the execution unit is also used for informing the execution unit to respond to the output instruction and report a signal or execute a preset instruction.

The control unit distributes the address of each frame header, the address range of each frame, the total address range and the maximum capture length of each frame according to the data bit width of the frame data interface, the FPGA reported data bit width, the capture frame length bit width, the capture total address bit width and other parameters.

The embodiment of the invention does not need to be connected with high-speed interfaces, instruments or other special tools and extra hardware pins, such as Gigabit Media Independent Interface (GMII), Serial Gigabit Media Independent Interface (SGMII) and small Pluggable optical transceiver Module (XFP) of the FPGA, and can be used only by basic and simple and reliable CPU access. Because the debugging of the complex interface and the flow channel is not dependent, expensive and scarce instruments are not needed, and a complex test environment is not needed to be set up, the requirements on the structural design and the thermal design of equipment are reduced, and the usability of diagnosis are greatly improved; all modules can be developed in parallel to promote development progress; and the flow processing function of other chips is isolated, so that the problem positioning is facilitated.

The embodiment of the invention can be built in an FPGA formal version, can be debugged on line, does not need to be powered off, can not damage a field measurement FPGA inner frame interface signal in engineering, and can be used for fault positioning in engineering.

The embodiment of the invention uses the natural reading sequence to present data, the frame head position is determined, and the result is visual. The method does not need a software debugging environment to specially write an adaptive drive for the function, reduces the application threshold and has high adaptability. The frame content, the frame interface time sequence, the capturing and reporting running state and the abnormal state of the frame interface can be obtained by reading the same address only once, the automatic reading is realized, the information is rich, and the operation is simple. The method and the device automatically adapt to bit widths of various frame interfaces and read-write interfaces, and the design of calling the module is very convenient.

The embodiment of the invention has simple application and use, easy operation, intuitive result and no technical experience, and can be widely used in the design and actual engineering of network equipment.

The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.

Claims

1. An ethernet frame output method, comprising:

the processor sends a report signal;

the processor sends the reported cache data to the debugging host;

the capturing and buffering of the at least one ethernet data frame processed by the FPGA from the frame header comprises:

2. The ethernet data frame output method of claim 1, wherein:

the capture reporting state comprises states to be captured, to be reported and reported which are converted in sequence, wherein the write control effective signal is generated in the capture state; and generating the effective reading control signal in the states of waiting to be reported and reporting.

3. The ethernet data frame output method of claim 1, wherein the method further comprises:

4. The ethernet data frame output method of claim 1, wherein said starting capturing and buffering the ethernet data frame comprises:

5. The ethernet data frame output method of claim 1, wherein:

the starting to capture and buffer the ethernet data frame comprises:

the beginning to report the cached data includes:

6. The ethernet data frame output method of claim 1, wherein:

the starting to capture and buffer the ethernet data frame comprises:

the beginning to report the cached data further includes:

7. The utility model provides an ethernet data frame output system, locates in network equipment, and network equipment includes treater and FPGA, its characterized in that: the system comprises a processing module arranged in the processor and an acquisition module arranged in the FPGA;

the acquisition module is used for responding to the output instruction or storing the preset instruction, and capturing and caching at least one Ethernet data frame processed by the FPGA from a frame header; the Ethernet data frame acquisition module is also used for responding to the report signal, reporting the cache data in the storage area where each Ethernet data frame is stored to a CPU bus, and then storing the cache data in the next captured Ethernet data frame;

the acquisition module comprises a control unit, a storage unit and at least one execution unit, wherein each execution unit comprises a capturing and reporting unit;

the execution unit is used for establishing a state machine and generating a read-write control effective signal according to the reset control signal, the report signal, a frame interface signal of the frame data interface and the current read-write address in the storage area, wherein the state machine comprises a reset state and a capture report state;

8. The ethernet frame output system of claim 7, wherein:

9. The ethernet frame output system of claim 7, wherein:

when the acquisition module comprises one execution unit, the control unit is also used for generating a current read or write address in the storage area and sending the current read or write address to the state machine;

10. The ethernet frame output system of claim 7, wherein:

the capturing and reporting unit is further configured to generate a frame data invalid, a frame tail misplaced or invalid frame tail code pattern according to the frame interface signal when the capturing and caching of the ethernet data frame is started, and store the frame data invalid, the frame tail misplaced or the invalid frame tail code pattern in the storage area.

11. The ethernet frame output system of claim 7, wherein:

the capturing and reporting unit is further configured to respond to the reporting signal in the reset state and generate and report a reset code pattern; and when the effective reading control signal is not generated, generating and reporting incomplete reading, no sampling to a frame, no sampling to a full frame or no sampling to a full frame code pattern in response to the report signal.

12. The ethernet frame output system of claim 7, wherein:

each execution unit further comprises a conversion unit;