CN114509966A - Asynchronous high-speed serial port real-time continuous data acquisition system - Google Patents
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Abstract
The invention discloses a real-time continuous data acquisition system of an asynchronous high-speed serial port, which comprises: the hardware acquisition module is used for converting the acquired analog signals into digital signals; the software control module is used for filtering the digital signal, accumulating the digital signal through a pulse counter, and sending the filtered digital signal to a serial port buffer area of a receiver to form a real-time continuous data stream; and the real-time data splicing module is used for analyzing the serial port data through the acquisition thread and judging the integrity and continuity of the serial port data so as to realize splicing processing of the real-time continuous data stream under the condition of no synchronous signal. By adopting a multi-serial-port card and a pulse sampling controller module and designing a serial-port high-speed transceiving and data packet splicing module, the condition that no packet is lost or wrong data is ensured in the test process is ensured; multistage hardware filtering and software filtering are adopted in the acquisition system, so that complete data reception and extremely low error rate can be guaranteed under the condition of high-speed serial port real-time data acquisition.
Description
Technical Field
The present invention relates to the field of communications. And more particularly to a real-time continuous data acquisition system for asynchronous high-speed serial ports.
Background
In the data acquisition and communication application scenario, a serial communication interface is often adopted to replace other large communication interfaces as an interface for data transceiving and interactive communication. In the data transmission process, synchronization signals are generally adopted to synchronize the real-time performance of a receiving end and a sending end, but when a clock source is not used as the synchronization signal, when the serial port packet data is larger, the whole packet data task cannot be completed in multiple timed receiving, so that packet loss or error codes are caused, and particularly, when the serial port is transmitted at a high speed, for example, the serial port receiving and sending period below 10ms or the baud rate is greater than the transmission rate of 460800, the problem is more obvious.
The Chinese patent application No. 201910683867.4 entitled "method, system and device for acquiring and analyzing serial protocol data" discloses a method, system and device for acquiring and analyzing serial protocol data, which performs frame check and frame analysis according to the contents of high and low bits of serial data, difference and mean value, and is mainly a general data analysis method applied to serial protocol change. The method only appoints and analyzes the integrity of a certain frame of serial port data, but matches the receiving and transmitting device in real time, does not take further consideration on the continuity of the multi-frame serial port data, and can cause the problems of data loss and disorder after error codes occur.
The invention discloses a multi-serial port communication control method, a device and an upper computer in the name of Chinese patent application No. CN202010667832.4, and mainly aims at monitoring a plurality of serial port control areas of a human-computer interaction interface of the upper computer, so that an operator can conveniently operate the on-off of a plurality of serial ports and receive and send data. The method is mainly used for completing related parameters and function setting of the multi-serial port based on a human-computer interaction interface, and independent operability polar data interaction integrity of the multi-serial port is not discussed.
Therefore, how to ensure complete data reception and extremely low bit error rate under the condition of high-speed serial port real-time data acquisition is a technical problem to be urgently solved by technical personnel in the field.
Disclosure of Invention
In order to solve at least one of the above problems, the present application proposes a high-speed serial communication real-time data acquisition system, which includes:
the hardware acquisition module is used for converting the acquired analog signals into digital signals;
the software control module is used for filtering the digital signal, accumulating the digital signal through a pulse counter, and sending the filtered digital signal to a serial port buffer area of a receiver to form a real-time continuous data stream;
and the real-time data splicing module is used for analyzing the serial port data through the acquisition thread and judging the integrity and continuity of the serial port data so as to realize splicing processing of the real-time continuous data stream under the condition of no synchronous signal.
In a specific embodiment, the hardware acquisition module includes:
a sampling controller, an industrial personal computer, an RS-422 transceiver, an RS-422 multi-serial port card and a data transmission cable, wherein,
the sampling controller is used for converting the input analog signals into digital signals and sending the digital signals to the RS-422 multi-serial-port card through the RS-422 transceiver, specifically, the sampling controller is used for completing the real-time acquisition system of accelerometer and gyroscope pulse analog signals and the real-time sending of serial port data, the industrial personal computer carries a non-real-time operating system for receiving, wherein the sending period is TwThe timing receiving period is TRNon real-time drift of Δ TRAnd satisfy Tw＜TR±ΔTR＜10TwClock transceiving conditions;
the RS-422 multi-serial port card is used for sending the digital signal to a computer.
In one embodiment, the sampling controller is based on an FPGA chip with RS-422 device architecture.
In one embodiment, the RS-422 multi-serial port card is disposed on the motherboard of the computer in the form of a bus slot.
In one embodiment, the software control module comprises: the system comprises an embedded FPGA software module and an upper computer data receiving software module.
In a specific embodiment, the software control module is used for realizing the functions of analog signal acquisition, conditioning and filtering, analog-to-digital logic conversion, serial port initialization operation, high-speed data acquisition, multi-serial port and multi-thread work and real-time data display and storage.
In a specific embodiment, the real-time data splicing module comprises:
s1, serial port equipment and data initialization, which are used for starting a data acquisition thread, configuring serial port parameters including baud rate, data sending form and data acquisition interval time, emptying a serial port buffer area, splicing a data reserved storage area and a complete frame data storage area, setting a data splicing flag bit to be 0, and setting an upper computer data receiving stop flag bit to be 0;
s2, the initial packet header judging unit reads the serial port buffer area, judges whether the first byte of the current serial port data is a preset packet header byte, if yes, the data enters a complete checking unit S3, and if not, the data enters a data packet post-splicing unit S5;
s3, a complete checking unit, which reads data from the first packet header in sequence according to the preset serial port byte length N, checks the preset continuous channel code, check bit and packet tail, if the check fails, reports a data receiving and sending error warning, discards the frame data, and returns to S1; if the check is passed, the data stream with the byte length of N is stored in a complete frame data storage area according to a frame of complete data, and then the complete check unit S3 is carried out again from the next packet head until the data in the buffer area is not enough with the byte length of N, and then the data stream is transferred to a data packet pre-reservation unit S4;
s4, reserving a data packet ahead unit, reserving residual data to a splicing data reserved storage area from the next byte at the last packet tail in the buffer area, recording the length of the byte as 1, setting the splicing flag bit of the data packet as 1, and entering an initial packet header judging unit S2;
s5, a data packet post-splicing unit, for performing the packet splicing processing of the latter half of the incomplete data packet in the previous packet, judging whether the first byte of the data in the current buffer is the packet header, if not, reading the bytes backwards in sequence, when the read byte is equal to the first packet header, reserving all the data in the buffer before the byte, and setting the byte length as N, if N is satisfied, the length of the byte isback+NpreN, and the check passes, and the check is spliced with the completion of the previous packet and storedSetting the data splicing flag bit to be 0 in the complete frame data storage area, clearing the spliced data reserved storage area, reporting a data transceiving error warning if the data splicing flag bit is not met, and returning to S1;
and S6, a data receiving stopping unit for receiving the upper computer data receiving stopping mark in a timing mode in the running process of S2-S5, if the upper computer data receiving stopping mark is 0, continuing the original step, and if the upper computer data receiving stopping mark is 1, closing the serial port data acquisition thread.
The invention has the following beneficial effects:
aiming at the existing problems, the application establishes an asynchronous high-speed serial port real-time continuous data acquisition system, and ensures that no packet loss and no wrong data are generated in the test process by adopting a multi-serial port card and a pulse sampling controller module and designing a serial port high-speed transceiving and data splicing module; furthermore, multistage hardware filtering and software filtering are adopted in the acquisition system, a counter and a latch are combined in a sampling controller to design aiming at high-speed serial port data acquisition, complete data receiving can be guaranteed under the high-speed serial port real-time data acquisition, and an extremely low error rate is guaranteed.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a schematic structural diagram of an asynchronous high-speed serial port real-time continuous data acquisition system according to an embodiment of the present application.
Fig. 2 shows a schematic structural diagram of a hardware acquisition module according to an embodiment of the present application.
FIG. 3 shows a schematic diagram of an FPGA chip according to an embodiment of the present application.
Fig. 4 shows a schematic diagram of an RS-422 transceiver according to an embodiment of the present application.
FIG. 5 shows a schematic diagram of a flow chart of FPGA embedded software according to an embodiment of the present application.
Fig. 6 is a schematic diagram illustrating a flowchart of the upper computer control software according to an embodiment of the present application.
Fig. 7 shows a schematic diagram of a splicing flow of a real-time data splicing module according to an embodiment of the application.
Detailed Description
In order to make the technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the present application provides a high-speed serial communication real-time data acquisition system, which includes:
the hardware acquisition module 10 is used for converting the acquired analog signals into digital signals;
the software control module 20 is used for filtering the digital signals, accumulating the digital signals through a pulse counter, and sending the filtered digital signals to a serial port buffer area of a receiver to form a real-time continuous data stream;
and the real-time data splicing module 30 is used for analyzing the serial port data through the acquisition thread and judging the integrity and continuity of the serial port data so as to realize splicing processing of the real-time continuous data stream under the condition of no synchronous signal.
In a specific embodiment, the hardware acquisition module includes: a sampling controller, an industrial personal computer, an RS-422 transceiver, an RS-422 multi-serial port card and a data transmission cable, wherein,
the sampling controller is used for converting the input analog signals into digital signals and sending the digital signals to the RS-422 multi-serial-port card through the RS-422 transceiver, specifically, the sampling controller is used for completing the real-time acquisition system of accelerometer and gyroscope pulse analog signals and the real-time sending of serial-port data, and the industrial personal computer carries a non-real-time operating system for receiving the signals, wherein the requirements of receiving the signals and sending the signals to the RS-422 multi-serial-port card are metTransmission period of TwThe timing receiving period is TRNon real-time drift of Δ TRAnd satisfy Tw＜TR±ΔTR＜10TwClock transceiving conditions;
the RS-422 multi-serial port card is used for sending the digital signal to a computer.
In a specific example, as shown in fig. 2, the hardware acquisition module of the whole system includes a sampling controller, an industrial personal computer, an RS-422 multi-serial-port card, a transmission cable, and the like, when a test starts, a plurality of analog signals enter the sampling controller, and then are converted into digital signals, and a data stream is sent to a computer through an RS-422 serial port, where the RS-422 serial-port card is generally installed on a computer motherboard in a bus slot form, such as PCI, PCIe, and the serial-port data enters the computer for subsequent data processing.
In one embodiment, the sampling controller is based on an FPGA chip with RS-422 device architecture.
For example, as shown in fig. 3, an EP3C 25Q-series FPGA chip is selected for use in the sampling controller, wherein an SCI interface is selected to configure corresponding SCIRX and SCITX pins, and the SCIRX and SCITX pins correspond to read/write channels of serial signals. After an external analog signal enters a sampling controller, different filter circuits such as RC (resistor-capacitor) filter low-pass circuits are designed according to signals of different frequency bands and different interference forms, analog-digital signal conversion is completed in an FPGA (field programmable gate array) after filtering, and specifically, a logic device records and converts the analog signal into a count value at a certain time interval to obtain a numerical value and transmits the numerical value to an RS-422 transceiver.
It should be noted that, as shown in fig. 4, the RS-422 transceiver in this embodiment selects a MAX3491ESD chip, and outputs serial read/write signal pairs RX and TX as differential signals. Specifically, the upper computer software firstly sends an initialization command to the sampling controller through the RS422 high-speed serial port, and when the test is started, the data stream is sent to the computer multi-serial-port card for receiving through the digital signal of the FPGA and then through the RS-422 transceiver on the sampling controller.
In this example, the hardware acquisition module mainly realizes that the conversion of the digital signal is completed by the multi-channel analog signal through the filter circuit, the processing of the FPGA chip and the RS-422 transceiver.
In a specific embodiment, the software control module mainly realizes functions of serial port initialization operation, timing data receiving and sending and the like, and calls a plurality of serial ports to work in a thread synchronization mode in a multithreading mode. Wherein the software control module comprises: an embedded FPGA software module as shown in fig. 5 and an upper computer data receiving software module as shown in fig. 6. Wherein the content of the first and second substances,
the development environment of the FPGA embedded software module is Quartus II 8.1, and the programming language is Verilog. An operating system for upper computer software development selects Win 764 bit, a corresponding installation package is Qt-windows-x86-5.2.exe, a Qt creator 4.6.3 is selected as an integrated development environment, a MinGw carried by Qt creator is selected as a C + + compiler, a programming language is C + +, and a software driving mode is that a multi-serial port card drives Moxa PComm 2K.
In this example, the software control module is used to implement functions of analog signal acquisition, conditioning and filtering, analog-to-digital logic conversion, serial port initialization operation, high-speed data acquisition, multi-serial port and multi-thread work, and real-time data display and storage.
In addition, the software control module in this embodiment performs design of a primary thread and a secondary thread and an equivalent mode thread on the application program, and creates an equivalent secondary thread ComThread in the main test thread MainWindow according to the number of open serial ports. The time sequence planning and the thread synchronization in the testing process are carried out among the multiple sub-threads through the thread synchronization class QNutex and the thread waiting class QWhitCondition, so that the application program is easier to expand and maintain.
In a specific embodiment, the real-time data splicing module mainly completes the splicing function of upper and lower two packets of data under the condition that the data packets are cut off in the high-speed transceiving process of a plurality of serial ports. As shown in fig. 7, the real-time data splicing process includes:
s1, serial port equipment and data initialization, which are used for starting a data acquisition thread, configuring serial port parameters including baud rate, data sending form and data acquisition interval time, emptying a serial port buffer area, splicing a data reserved storage area and a complete frame data storage area, setting a data splicing flag bit to be 0, and setting an upper computer data receiving stop flag bit to be 0;
s2, the initial packet header judging unit reads the serial port buffer area, judges whether the first byte of the current serial port data is a preset packet header byte, if yes, the data enters a complete checking unit S3, and if not, the data enters a data packet post-splicing unit S5;
s3, a complete checking unit, which reads data from the first packet header in sequence according to the preset serial port byte length N, checks the preset continuous channel code, check bit and packet tail, if the check fails, reports a data receiving and sending error warning, discards the frame data, and returns to S1; if the check is passed, the data stream with the byte length of N is stored in a complete frame data storage area according to a frame of complete data, and then the complete check unit S3 is carried out again from the next packet head until the data in the buffer area is not enough with the byte length of N, and then the data stream is transferred to a data packet pre-reservation unit S4;
s4, reserving a data packet ahead unit, reserving residual data to a splicing data reserved storage area from the next byte at the last packet tail in the buffer area, recording the length of the byte as 1, setting the splicing flag bit of the data packet as 1, and entering an initial packet header judging unit S2;
s5, a data packet post-splicing unit, for performing the packet splicing processing of the latter half of the incomplete data packet in the previous packet, judging whether the first byte of the data in the current buffer is the packet header, if not, reading the bytes backwards in sequence, when the read byte is equal to the first packet header, reserving all the data in the buffer before the byte, and setting the byte length as N, if N is satisfied, the length of the byte isback+NpreIf the verification is passed, the data is spliced with the last packet and stored in a complete frame data storage area, the data splicing flag bit is set to be 0, meanwhile, the spliced data reserved storage area is cleared, if the verification is not met, a data transceiving error warning is reported, and the step returns to S1;
and S6, a data receiving stopping unit for receiving the upper computer data receiving stopping mark in a timing mode in the running process of S2-S5, if the upper computer data receiving stopping mark is 0, continuing the original step, and if the upper computer data receiving stopping mark is 1, closing the serial port data acquisition thread.
The technical scheme is suitable for a scene of high-speed serial port real-time data acquisition, for the data acquisition system when causing the error code because of single frame data is cut off to high-speed serial port transmission, utilize mutually supporting between hardware acquisition module, software control module and the real-time data concatenation module, guarantee the complete receipt of data and guarantee extremely low error rate under the high-speed serial port real-time data acquisition finally, the method has the characteristics of strong commonality, simple structure, the method is suitable for high-speed serial communication interface real-time data acquisition, very big reduction development time, and the development cost is reduced.
In the embodiment, a design mode of a multi-serial-port card designed by hardware is adopted, so that the multi-path serial ports can be tested and collected simultaneously on the basis of a hardware principle; by adopting a multithreading program scheduling and designing mode, the system ensures that the multi-path serial ports can simultaneously carry out test acquisition on software, so that the high-speed serial communication interface real-time data acquisition system has the characteristic of strong universality.
In addition, in the embodiment, a multi-serial-port card and a pulse sampling controller module are adopted, and a serial-port high-speed transceiving and data packet splicing module is designed, so that no packet loss and no wrong number are ensured in the test process; the acquisition system adopts multi-level hardware filtering and software filtering, and a counter and a latch are combined in a sampling controller to design the high-speed serial port data acquisition, so that the high-speed serial communication interface real-time data acquisition system of the embodiment can improve the accuracy of pulse acquisition.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (7)
1. The utility model provides a continuous real-time data acquisition system of high-speed serial ports of non-synchronization which characterized in that includes:
the hardware acquisition module is used for converting the acquired analog signals into digital signals;
the software control module is used for filtering the digital signals, accumulating the digital signals through the pulse counter, and sending the filtered digital signals to a serial port buffer area of a receiver to form a real-time continuous data stream;
and the real-time data splicing module is used for analyzing the serial port data through the acquisition thread and judging the integrity and continuity of the serial port data so as to realize splicing processing of the real-time continuous data stream under the condition of no synchronous signal.
2. The system of claim 1, wherein the hardware acquisition module comprises: a sampling controller, an industrial personal computer, an RS-422 transceiver, an RS-422 multi-serial port card and a data transmission cable, wherein,
the sampling controller is used for converting the input analog signals into digital signals and sending the digital signals to the RS-422 multi-serial-port card through the RS-422 transceiver, specifically, the sampling controller is used for completing the real-time acquisition system of accelerometer and gyroscope pulse analog signals and the real-time sending of serial port data, the industrial personal computer carries a non-real-time operating system for receiving, wherein the sending period is TwThe timing receiving period is TRNon real-time drift of Δ TRAnd satisfy Tw<TR±ΔTR<10TwClock transceiving conditions;
the RS-422 multi-serial port card is used for sending the digital signal to a computer.
3. The system of claim 2, wherein the sampling controller is based on an FPGA chip collocated RS-422 architecture.
4. The system of claim 2, wherein the RS-422 multi-serial port card is disposed on a motherboard of the computer in a form of a bus slot.
5. The system of claim 1, wherein the software control module comprises: the system comprises an embedded FPGA software module and an upper computer data receiving software module.
6. The system of claim 1, wherein the software control module is configured to perform functions of analog signal acquisition, conditioning and filtering, analog-to-digital logic conversion, serial port initialization operation, high-speed data acquisition, multi-serial port and multi-thread operation, and real-time data display and storage.
7. The system of claim 1, wherein the real-time data splicing module splicing process comprises:
s1, serial port equipment and data initialization, which are used for starting a data acquisition thread, configuring serial port parameters including baud rate, data sending form and data acquisition interval time, emptying a serial port buffer area, splicing a data reserved storage area and a complete frame data storage area, setting a data splicing flag bit to be 0, and setting an upper computer data receiving stop flag bit to be 0;
s2, the initial packet header judging unit reads the serial port buffer area, judges whether the first byte of the current serial port data is a preset packet header byte, if yes, the data enters a complete checking unit S3, and if not, the data enters a data packet post-splicing unit S5;
s3, a complete checking unit, which reads data from the first packet header in sequence according to the preset serial port byte length N, checks the preset continuous channel code, check bit and packet tail, if the check fails, reports a data receiving and sending error warning, discards the frame data, and returns to S1; if the check is passed, the data stream with the byte length of N is stored in a complete frame data storage area according to a frame of complete data, and then the complete check unit S3 is carried out again from the next packet head until the data in the buffer area is not enough with the byte length of N, and then the data stream is transferred to a data packet pre-reservation unit S4;
s4, reserving a data packet ahead unit, reserving residual data to a splicing data reserved storage area from the next byte at the last packet tail in the buffer area, recording the length of the byte as 1, setting the splicing flag bit of the data packet as 1, and entering an initial packet header judging unit S2;
s5, a data packet post-splicing unit, for performing the packet splicing processing of the latter half of the incomplete data packet in the previous packet, judging whether the first byte of the data in the current buffer is the packet header, if not, reading the bytes backwards in sequence, when the read byte is equal to the first packet header, reserving all the data in the buffer before the byte, and setting the byte length as N, if N is satisfied, the length of the byte isback+NpreIf the verification is passed, the data is spliced with the last packet and stored in a complete frame data storage area, the data splicing flag bit is set to be 0, meanwhile, the spliced data reserved storage area is cleared, if the verification is not met, a data transceiving error warning is reported, and the step returns to S1;
and S6, a data receiving stopping unit for receiving the upper computer data receiving stopping mark in a timing mode in the running process of S2-S5, if the upper computer data receiving stopping mark is 0, continuing the original step, and if the upper computer data receiving stopping mark is 1, closing the serial port data acquisition thread.
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