CN116450563A - Message receiving device and processor communication system - Google Patents

Message receiving device and processor communication system Download PDF

Info

Publication number
CN116450563A
CN116450563A CN202310508037.4A CN202310508037A CN116450563A CN 116450563 A CN116450563 A CN 116450563A CN 202310508037 A CN202310508037 A CN 202310508037A CN 116450563 A CN116450563 A CN 116450563A
Authority
CN
China
Prior art keywords
message
standard format
preset
interrupt
receiving device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310508037.4A
Other languages
Chinese (zh)
Inventor
韩崇飞
吴飞
李倍
杨壮
马千祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Enflame Technology Co ltd
Original Assignee
Shanghai Enflame Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Enflame Technology Co ltd filed Critical Shanghai Enflame Technology Co ltd
Priority to CN202310508037.4A priority Critical patent/CN116450563A/en
Publication of CN116450563A publication Critical patent/CN116450563A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/546Message passing systems or structures, e.g. queues
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/54Indexing scheme relating to G06F9/54
    • G06F2209/548Queue
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer And Data Communications (AREA)

Abstract

The invention discloses a message receiving device and a processor communication system. The device comprises: the linked list storage module is used for storing the standard format message sent by the message sending device into a preset linked list and sending the standard format message in the preset linked list to the bus sender based on a preset message output rule; the bus transmitter is used for forwarding the standard format message sent by the linked list storage module to a preset storage body; and the interrupt transmitter is used for generating an interrupt notification and transmitting the interrupt notification to the message receiving device so that the message receiving device can read the standard format message corresponding to the interrupt notification from the preset storage body. According to the technical scheme, the message receiving device is connected with the message receiving equipment through the newly added message receiving device so as to realize message receiving and temporary storage, so that the service messages of different types, formats and sources can be efficiently received, the flexibility and expandability of message receiving of the processor can be improved, and the message acquisition delay can be reduced.

Description

Message receiving device and processor communication system
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a message receiving device and a processor communication system.
Background
At present, a large-scale chip represented by an artificial intelligent chip needs multiple processors to coordinate with functional modules, and in the running process of the chip, a great amount of service information is transferred between the processors and the functional modules, and the processors need to be capable of timely receiving and processing information from other processors or the functional modules.
In a large-scale chip, the number of processors is as high as several tens, and the types are diverse (for example, may include a scheduling processor, a user host processor, an application processor, etc.), and these heterogeneous processors have a need for information reception. Second, the types of messages that different processors need to receive are diverse and there is a priority score. In addition, the source device that sends the message is multiple, and includes virtual devices in addition to physical devices, and the processor needs to be able to accurately identify the message sending device when receiving and processing the message. Moreover, large-scale chips have multi-Die scenarios, and the processor needs to be able to identify from which Die the message specifically came. Aiming at the complex requirement, the existing information receiving mode is difficult to meet.
Disclosure of Invention
The invention provides a message receiving device and a processor communication system, which can realize the efficient receiving of service messages of different types, formats and sources, can improve the flexibility and the expandability of the message receiving of a processor and can reduce the message acquisition delay.
According to one aspect of the invention, a message receiving device is provided, which comprises a linked list storage module, a bus transmitter and an interrupt transmitter, wherein the message receiving device corresponds to a message receiving device one by one;
the linked list storage module is connected with the bus transmitter and is used for storing the standard format message sent by the message sending device into a preset linked list and sending the standard format message in the preset linked list to the bus transmitter based on a preset message output rule;
the bus transmitter is used for forwarding the standard format message sent by the linked list storage module to a preset storage body;
the interrupt transmitter is used for generating an interrupt notification and transmitting the interrupt notification to the message receiving device so that the message receiving device can read the standard format message corresponding to the interrupt notification from the preset storage body.
Optionally, the linked list storage module includes a message distributor and a plurality of message registers;
the message distributor is connected with each message register and is used for analyzing the standard format message to acquire a target address and a context identification mark, acquiring a target message register corresponding to the standard format message according to the target address and the context identification mark, and sending the standard format message to the target message register;
the target message register is used for temporarily storing the standard format message.
Optionally, the linked list storage module further includes a data encapsulation manager, and the preset linked list includes a plurality of message queues;
the data encapsulation manager is connected with each message register, and is used for reading standard format messages from each message register, encapsulating the read standard format messages to obtain encapsulation messages, obtaining target message queues of a preset linked list matched with the encapsulation messages according to equipment identification identifiers in the read standard format messages, and storing the encapsulation messages to the target message queues;
the message register is further configured to send a standard format message corresponding to the message read request to the data encapsulation manager when the message read request of the data encapsulation manager is received;
the bus transmitter is further configured to read the encapsulated message from the target message queue and send the encapsulated message to the preset memory bank.
Optionally, the linked list storage module further includes a plurality of configuration registers;
the configuration register is used for configuring the maximum number of message queues in the preset linked list, and setting attribute information and storage body information corresponding to each message queue according to information configuration operation of a user on each message queue;
wherein the attribute information includes a queue length, and the memory bank information includes a memory bank initial address, a memory bank size, a read-write pointer, and/or an interrupt threshold.
Optionally, the interrupt transmitter is specifically configured to:
and if the number of messages corresponding to the current message queue sent by the bus sender to the preset storage body is detected to be greater than zero at each preset period, generating a first interrupt notification corresponding to the current message queue, and sending the first interrupt notification to the message receiving equipment so that the message receiving equipment reads standard format messages corresponding to the first interrupt notification from the preset storage body.
Optionally, the interrupt transmitter is further configured to:
if the number of the messages corresponding to the current message queue sent to the preset storage body by the bus sender is detected to be larger than or equal to a preset number threshold, generating a second interrupt notification corresponding to the current message queue, and sending the second interrupt notification to the message receiving device, so that the message receiving device reads standard format messages corresponding to the second interrupt notification from the preset storage body.
Optionally, the interrupt sender sends the interrupt notification in a manner including connection interrupt and message signal interrupt.
Optionally, the standard format message includes at least one of a business message, an interrupt message, a remote procedure call message, and a virtual serial port communication message.
According to another aspect of the present invention, there is provided a processor communication system including a plurality of message receiving apparatuses and message transmitting apparatuses according to any one of the embodiments of the present invention, each of the message transmitting apparatuses being connected to each of the message receiving apparatuses through a bus network;
the message sending device is used for carrying out standardized processing on the message to be sent of the message sending equipment so as to obtain a standard format message, and sending the standard format message to the corresponding message receiving device through the bus network.
Optionally, the message sending device is specifically configured to:
and acquiring a device identification identifier and a context identification identifier corresponding to the message sending device, and generating a standard format message according to the device identification identifier, the context identification identifier and the message to be sent.
According to the technical scheme, the standard format message sent by the message sending device is stored in the preset linked list through the linked list storage module, and the standard format message in the preset linked list is sent to the bus sender based on the preset message output rule; then, the standard format message sent by the linked list storage module is forwarded to a preset storage body through a bus sender; and finally, generating an interrupt notification by the interrupt transmitter and transmitting the interrupt notification to the message receiving device so that the message receiving device reads the standard format message corresponding to the interrupt notification from the preset storage body, and connecting the message receiving device by the newly added message receiving device to realize message receiving and temporary storage, thereby realizing the efficient receiving of service messages of different types, formats and sources, improving the flexibility and expandability of message receiving of a processor and reducing the message acquisition delay.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1A is a schematic structural diagram of a message receiving device according to a first embodiment of the present invention;
FIG. 1B is a schematic diagram of a linked list storage module according to a first embodiment of the present invention;
FIG. 1C is a schematic diagram of another linked list storage module according to an embodiment of the present invention;
FIG. 1D is a schematic diagram of another linked list storage module according to an embodiment of the present invention;
fig. 1E is a schematic diagram of an application of a message receiving apparatus provided in a large-scale chip according to a first embodiment of the present invention;
fig. 1F is a schematic diagram of an internal design of a message receiving device according to a first embodiment of the present invention;
fig. 2A is a schematic structural diagram of a processor communication system according to a second embodiment of the present invention;
fig. 2B is a schematic structural diagram of another processor communication system according to a second embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," "target," and the like in the description and claims of the present invention and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1A is a schematic structural diagram of a message receiving apparatus according to a first embodiment of the present invention, where a message receiving apparatus 10 may include a linked list storage module 11, a bus transmitter 12, and an interrupt transmitter 13, where the message receiving apparatus 10 corresponds to a message receiving device one by one;
the message receiving device may be a device with a message receiving requirement on a chip, for example, may be a scheduling processor, a user host processor, an application processor, a system manager, a video processor, or an intelligent operation processor, etc., and the processor may correspond to different architecture types, for example, may be an ARM single core processor, an ARM multiple core processor, a risc_v architecture (five) processor, an x86 architecture processor on a host device, etc.
In this embodiment, for each message receiving device, a unique corresponding message receiving apparatus 10 may be deployed in advance, for receiving and storing a plurality of entities or virtual devices, different types of messages sent to the corresponding message receiving device, and the corresponding message receiving devices may be notified with different priorities. It will be appreciated that the message receiving apparatus 10 is connected to a corresponding message receiving device, and that all messages sent to the message receiving device are sent to the message receiving apparatus 10 first.
The linked list storage module 11 is connected to the bus transmitter 12, and is configured to store the standard format message sent by the message sending device into a preset linked list, and send the standard format message in the preset linked list to the bus transmitter 12 based on a preset message output rule.
In this embodiment, for each message sending apparatus, a unique corresponding message sending device may be deployed in advance. When the message sending device needs to send the service message, the service message needs to be sent to the corresponding message sending device, the message sending device firstly performs standardization processing on the service message to be sent so as to obtain the standard format message, and then sends the standard format message to the message receiving device 10 corresponding to the destination message receiving device. The standard format message may be a processor message corresponding to a unified data format.
The linked list storage module 11 is configured to temporarily store and forward a received standard format message. It should be noted that, the linked list storage module 11 adopts a linked list storage design, and compared with the multiple first-in first-out (First Input First Output, FIFO) storage design adopted in the prior art, multiple types of messages can be stored in the same storage structure in a mixed manner, so as to realize multiple caches of one linked list, and the reserved storage space of each type of message is not needed to be estimated in advance, so that the linked list storage module has advantages when processing multiple types of messages in unbalanced manner, and can avoid the waste of actual physical storage under any message combination.
In this embodiment, the linked list storage module 11 may be preset with a linked list, and is configured to store received messages in different standard formats, and may output the stored messages in standard formats to the bus sender 12 according to a preset message output rule, for example, performing message output every certain time, performing message output when the number of detected messages reaches a set number threshold, performing message output at a uniform rate, or the like.
Optionally, before storing the standard format message in the preset linked list, the standard format message may be encapsulated, and then the encapsulated standard format message is stored in the preset linked list. The preset linked list may include a plurality of message queues, and each message queue may correspond to a message type or a message source. When the messages are stored in the preset linked list, the message types can be stored in sequence according to the receiving sequence without considering, and the connection relation can be established through pointers for the stored messages corresponding to the same message queue.
The standard format message may include at least one of a service message, an interrupt message, a remote procedure call message, and a virtual serial port communication message, among others. The type of message that needs to be received may be one or a combination of any number of these, and the message type may be continuously extended for a single processor. In addition, there is a priority within or between different types of messages, and the processor needs to process the messages according to the priority.
The bus transmitter 12 is configured to forward the standard format message sent by the linked list storage module 11 to a preset storage; specifically, the bus transmitter 12 may transmit the standard format message or the encapsulation message in the preset linked list in the linked list storage module 11 to the preset memory bank at intervals of a certain time or in real time.
The preset memory bank may be a pre-designated memory, and may be communicatively connected to the message receiving device 10 through a bus network. Typically, the preset memory bank may include a plurality of message queues for storing different types of standard format messages.
The interrupt transmitter 13 is configured to generate an interrupt notification and send the interrupt notification to a message receiving device, so that the message receiving device reads a standard format message corresponding to the interrupt notification from the preset storage body. The interrupt notification may be instruction information for notifying the message receiving device to read the message, and may include information such as a memory bank address, a queue identifier, a queue pointer, and the like. After receiving the interrupt notification, the message receiving device can read the standard format message corresponding to the interrupt notification from the preset storage body, and then process the message.
According to the technical scheme, the standard format message sent by the message sending device is stored in the preset linked list through the linked list storage module, and the standard format message in the preset linked list is sent to the bus sender based on the preset message output rule; then, the standard format message sent by the linked list storage module is forwarded to a preset storage body through a bus sender; and finally, generating an interrupt notification by the interrupt transmitter and transmitting the interrupt notification to the message receiving device so that the message receiving device reads the standard format message corresponding to the interrupt notification from the preset storage body, and connecting the message receiving device by the newly added message receiving device to realize message receiving and temporary storage, thereby realizing the efficient receiving of service messages of different types, formats and sources, improving the flexibility and expandability of message receiving of a processor and reducing the message acquisition delay.
Alternatively, as shown in FIG. 1B, the linked list storage module 11 may include a message distributor 111 and a plurality of message registers 112; one message register 112 may correspond to one or more message queues.
The message distributor 111 is connected to each message register 112, and is configured to parse the standard format message to obtain a target address and a context identification identifier, obtain a target message register 112 corresponding to the standard format message according to the target address and the context identification identifier, and send the standard format message to the target message register 112. When the message sending device performs standardized processing on the message to be sent, it needs to add the device identification identifier uniquely corresponding to the message sending device, the context identification identifier uniquely corresponding to each virtual machine on the message sending device, and the writing address of the message to the sideband signal of the message to be sent, so as to identify the source of the message. Thus, the message distributor 111 may obtain the destination address and the context identification from the sideband signal by performing content parsing on the standard format message.
The target address may be a writing address of the message; the context identification identifier may be a string for identifying the identity of the virtual machine. In this embodiment, the correspondence between the access address, the context identification identifier and the message register 112 may be pre-established, so that the target message register 112 may be found according to the current target address, the context identification identifier, and the pre-established correspondence. The message distributor 111 may then send the current standard format message to the destination message register 112.
In this embodiment, even if the destination addresses of the messages are the same, the message distributor 11 can store the standard format messages in different message queues, that is, different message registers 112, according to the context identification identifier and the device identification identifier. Wherein, different message queues can be attributed to different virtual functions, thereby facilitating the mutual isolation of virtual function processing.
The destination message register 112 is configured to temporarily store the standard format message.
Optionally, as shown in fig. 1C, the linked list storage module 11 may further include a data encapsulation manager 113, where the preset linked list includes a plurality of message queues;
the data encapsulation manager 113 is connected to each message register 112, and is configured to read a standard format message from each message register 112, encapsulate the read standard format message to obtain an encapsulated message, obtain a target message queue of a preset linked list matched with the encapsulated message according to a device identification identifier in the read standard format message, and store the encapsulated message in the target message queue.
In a specific example, the data encapsulation manager 113 may encapsulate the standard format message in each message register 112 according to the data format corresponding to the preset linked list, and sequentially store the encapsulated message in the corresponding message queue in the preset linked list. Specifically, content analysis can be performed on the standard format message to obtain a device identification identifier and a context identification identifier of the message sending device; then, the current target message queue can be determined according to the current equipment identification identifier, the context identification identifier, and the preset mapping relationship among the equipment identification identifier, the context identification identifier and the message queue. Finally, the encapsulated message may be sent to a target message queue of a preset linked list for storage.
The message register 112 is further configured to, when receiving a message read request from the data encapsulation manager 113, send a standard format message corresponding to the message read request to the data encapsulation manager 113; alternatively, the message register 112 may automatically send stored standard format messages to the data encapsulation manager 113 at regular time or based on a fixed rate.
The bus transmitter 12 is further configured to read the encapsulated message from the target message queue and transmit the encapsulated message to the preset memory bank.
Optionally, as shown in fig. 1D, the linked list storage module 11 may further include a plurality of configuration registers 114; configuration registers 114 may be coupled to message distributor 111, message register 112, and a preset linked list, respectively.
The configuration register 114 is configured to configure a maximum number of message queues in the preset linked list, and set attribute information and storage information corresponding to each message queue according to information configuration operation of a user on each message queue;
wherein the attribute information includes a queue length, and the memory bank information includes a memory bank initial address, a memory bank size, a read-write pointer, and/or an interrupt threshold.
In this embodiment, the preset linked list may support, through register configuration, a service scenario serving a single message type, multiple message types, multiple virtual caches, and multiple priorities, and finally, multiple queues capable of being dynamically enabled, operated, and removed are presented to the client, so that the client may operate conveniently.
In this embodiment, the configuration registers 114 may be divided into multiple groups, and may be accessed by different virtual machines in a manner of mapping physical addresses by virtual addresses, where the multiple virtual machines may operate the message receiving apparatus 10 at the same time and do not affect each other. The configuration registers 114 are grouped as follows: (1) A physical function (Physical Function, PF) general configuration register, which may be generally configured by the hypervisor software, for normalizing the general functions of the message receiving device 10; (2) A physical function packet configuration register, which may be configured by the hypervisor software, for specifying the behavior of each message queue, e.g., RAS interrupt setup, etc.; (3) A Virtual Function (VF) packet configuration register, which may be set by the guard software, is used to set the output Virtual address, queue length, read-write pointer, etc. of each message queue.
The interrupt transmitter 13 may be specifically configured to: and if detecting that the number of messages corresponding to the current message queue sent by the bus sender 12 to the preset storage body is greater than zero, generating a first interrupt notification corresponding to the current message queue and sending the first interrupt notification to the message receiving device at intervals of preset period, so that the message receiving device reads a standard format message corresponding to the first interrupt notification from the preset storage body.
In a specific example, the interrupt transmitter 13 may transmit the interrupt notification in a periodic transmission manner; specifically, if it is detected that the number of messages corresponding to a certain message queue sent by the bus sender 12 is not zero, an interrupt notification corresponding to the message queue may be generated and sent to the message receiving device, so that the message receiving device reads a message from a preset memory bank based on the interrupt notification. Optionally, when the standard format message is encapsulated, the message receiving device may also read the encapsulated message corresponding to the interrupt notification from the preset storage. The preset period may be a preset time length, and may be adaptively set according to actual requirements.
In addition, the interrupt sender 13 may be further specifically configured to generate a second interrupt notification corresponding to the current message queue and send the second interrupt notification to the message receiving device if it is detected that the number of messages corresponding to the current message queue sent by the bus sender 12 to the preset memory bank is greater than or equal to a preset number threshold, so that the message receiving device reads a standard format message corresponding to the second interrupt notification from the preset memory bank.
In another specific example, the interrupt transmitter 13 may also transmit an interrupt notification in real time; specifically, once the interrupt transmitter 13 detects that the number of messages corresponding to a certain message queue sent by the bus transmitter 12 is greater than or equal to the preset number threshold, an interrupt notification corresponding to the message queue may be generated immediately and sent to the message receiving device, so that the message receiving device reads a message from the preset storage body.
The preset number threshold may be a preset number value, for example, 1, 10, etc. Typically, when the preset number threshold is 1, as soon as the bus transmitter 12 transmits an encapsulated message corresponding to a certain message queue, the interrupt transmitter 13 generates an interrupt notification corresponding to the message queue and transmits the interrupt notification to the message receiving apparatus.
Among them, the manner in which the interrupt transmitter 13 transmits the interrupt notification may include connection interrupt and message signal interrupt. Wherein, the connection interruption can be that a special connecting wire is adopted to send an interruption notification; message signaled interrupt (message signal interrupt, MSI), may be by sending a specific message to effect a processor interrupt.
Optionally, after receiving the interrupt notification, the message receiving device may select, according to a preset arbitration policy and a cache line of the message queue, the encapsulated messages cached in different message queues for reading and processing.
In a specific implementation of this embodiment, the application of the message receiving device 10 in a large-scale chip may be as shown in fig. 1E. Each message receiving device, e.g., SP processor, host processor, AP processor, SSM processor, etc., may deploy one message receiving apparatus 10 and multiple virtual machines on the processor. Each message receiving apparatus 10 is connected to the message transmitting apparatus via a bus network, and messages of different types transmitted to the message receiving device are received by the message receiving apparatus 10 first.
It will be appreciated that the message receiving device may also be provided with a message sending function, and may send different types of messages to the message receiving means 10 of other message receiving devices via the bus network. Thus, one processor can configure the message receiving device 10 and the message transmitting device at the same time. The messages may include interrupt messages, remote procedure call messages, serial communication messages, and the like.
In another specific implementation of this embodiment, the internal design of the message receiving device 10 may be as shown in fig. 1F. The received service message is firstly distributed to a matched message register 112 for temporary storage by an address mapping manager according to a target address, a device identification identifier and a context identification identifier in the service message; then, the data encapsulation manager 113 reads the standard format message from each message register 112, encapsulates it to obtain an encapsulated message, and stores the encapsulated message in a message queue matched in a preset linked list.
Further, the bus transmitter 12 may send the encapsulated messages corresponding to the message queues in the preset linked list to the corresponding message queues in the memory bank for storing. Meanwhile, the interrupt transmitter 13 may generate an interrupt notification corresponding to the message queue to transmit to the message receiving device (processor) so that the processor performs message reading and processing from the memory bank.
Next, the overall function of the message receiving apparatus 10, as well as attribute information and bank information of each message queue, may be configured by each of the configuration registers 114, for example, PF overall configuration registers (e.g., general configuration registers, MSI configuration registers, mask registers, address mapping registers, etc.), PF packet configuration registers (e.g., PF configuration registers, RAS registers, etc.), and VF allocation configuration registers (e.g., queue configuration registers, queue read pointer registers, queue write pointer registers, and queue interrupt registers). The PF overall configuration register and the PF grouping configuration register can be configured based on the hypervisor software, and the VF grouping configuration register can be configured based on the guest software.
Example two
Fig. 2A is a schematic structural diagram of a processor communication system according to a second embodiment of the present invention, where the processor communication system 20 may include a plurality of message receiving apparatuses 10 and message sending apparatuses 21 according to the first embodiment, and each of the message sending apparatuses 21 is connected to each of the message receiving apparatuses 10 through a bus network;
the message sending device 21 is configured to perform standardization processing on a message to be sent of the message sending device, so as to obtain a standard format message, and send the standard format message to the corresponding message receiving device 10 through the bus network. Specifically, the message sending device 21 may be configured to receive a message sending pulse from a message sending device such as a processor or a functional module, and convert the message sending pulse into data on one or more buses according to a message type for transmission.
In this embodiment, for each message sending device, for example, a processor, a functional module, etc., a corresponding message sending device 21 may be configured, and all messages to be sent by the message sending device need to be sent to the corresponding message sending device 21 first. The message sending device 21 may be a general component, that is, all the message sending devices 21 have identical structural components.
The message to be sent may be a service message with different types and different formats, and may include contents such as a target address, a source address, and the like.
In a specific example, the message sending device 21 may perform data format conversion on the messages to be sent in different data formats, so as to obtain standard format messages corresponding to the unified data format. Meanwhile, the message receiving device can be determined by performing content analysis on the message to be sent to acquire the target address. The standard format message may then be transmitted over the bus network to the message receiving means 10 corresponding to the message receiving device. The unified data format may be preset, for example, may be a bus data format.
Optionally, the message sending device 21 may be specifically configured to: and acquiring a device identification identifier and a context identification identifier corresponding to the message sending device, and generating a standard format message according to the device identification identifier, the context identification identifier and the message to be sent.
It should be noted that each message sending device has a unique device identification identifier, and each virtual machine on the device corresponds to a unique context identification identifier. In this embodiment, in order to identify the source of the message, when the message sending apparatus 21 performs standardized processing on the message to be sent, the device identification identifier and the context identification identifier corresponding to the current message sending device may be obtained, and the device identification identifier and the context identification identifier may be embedded into the sideband signal of the message to be sent after the data format conversion, so as to generate the message in the standard format.
According to the technical scheme, the message sending device and the message receiving device are respectively deployed, so that efficient communication among different processors can be realized, high design complexity of a transmission mode caused by non-uniform message formats can be reduced, efficient transmission and processing of multi-type service messages can be realized, consistent design can be realized, design efficiency can be improved, and overall development and maintenance cost can be reduced.
In one specific implementation of this embodiment, the processor communication system 20 may be configured as shown in fig. 2B. Wherein, each message sending device is provided with a corresponding message sending device A, and each message receiving device (processor) is provided with a corresponding message receiving device B, and the message sending device 21 and the message receiving device 10 are connected through a bus network. The message transmitting apparatus 21 attaches a device identification number and a context identification number corresponding to the message transmitting device when transmitting the message. The bus network passes the message sent by the message sending device 21 to different processors according to the bus write address to achieve message transmission.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. The message receiving device is characterized by comprising a linked list storage module, a bus transmitter and an interrupt transmitter, wherein the message receiving device corresponds to the message receiving equipment one by one;
the linked list storage module is connected with the bus transmitter and is used for storing the standard format message sent by the message sending device into a preset linked list and sending the standard format message in the preset linked list to the bus transmitter based on a preset message output rule;
the bus transmitter is used for forwarding the standard format message sent by the linked list storage module to a preset storage body;
the interrupt transmitter is used for generating an interrupt notification and transmitting the interrupt notification to the message receiving device so that the message receiving device can read the standard format message corresponding to the interrupt notification from the preset storage body.
2. The message receiving device of claim 1, wherein the linked list storage module comprises a message distributor and a plurality of message registers;
the message distributor is connected with each message register and is used for analyzing the standard format message to acquire a target address and a context identification mark, acquiring a target message register corresponding to the standard format message according to the target address and the context identification mark, and sending the standard format message to the target message register;
the target message register is used for temporarily storing the standard format message.
3. The message receiving device of claim 2, wherein the linked list storage module further comprises a data encapsulation manager, the preset linked list comprising a plurality of message queues;
the data encapsulation manager is connected with each message register, and is used for reading standard format messages from each message register, encapsulating the read standard format messages to obtain encapsulation messages, obtaining target message queues of a preset linked list matched with the encapsulation messages according to equipment identification identifiers in the read standard format messages, and storing the encapsulation messages to the target message queues;
the message register is further configured to send a standard format message corresponding to the message read request to the data encapsulation manager when the message read request of the data encapsulation manager is received;
the bus transmitter is further configured to read the encapsulated message from the target message queue and send the encapsulated message to the preset memory bank.
4. The message receiving device of claim 3, wherein the linked list storage module further comprises a plurality of configuration registers;
the configuration register is used for configuring the maximum number of message queues in the preset linked list, and setting attribute information and storage body information corresponding to each message queue according to information configuration operation of a user on each message queue;
wherein the attribute information includes a queue length, and the memory bank information includes a memory bank initial address, a memory bank size, a read-write pointer, and/or an interrupt threshold.
5. Message receiving device according to claim 1, characterized in that the interrupt sender is specifically configured to:
and if the number of messages corresponding to the current message queue sent by the bus sender to the preset storage body is detected to be greater than zero at each preset period, generating a first interrupt notification corresponding to the current message queue, and sending the first interrupt notification to the message receiving equipment so that the message receiving equipment reads standard format messages corresponding to the first interrupt notification from the preset storage body.
6. The message receiving apparatus of claim 1, wherein the interrupt transmitter is further configured to:
if the number of the messages corresponding to the current message queue sent to the preset storage body by the bus sender is detected to be larger than or equal to a preset number threshold, generating a second interrupt notification corresponding to the current message queue, and sending the second interrupt notification to the message receiving device, so that the message receiving device reads standard format messages corresponding to the second interrupt notification from the preset storage body.
7. A message receiving device according to claim 5 or 6, characterized in that the way in which the interrupt sender sends interrupt notifications comprises a connection interrupt and a message signal interrupt.
8. The message receiving apparatus according to any one of claims 1 to 7, wherein the standard format message includes at least one of a service message, an interrupt message, a remote procedure call message, and a virtual serial port communication message.
9. A processor communication system comprising a plurality of message receiving means as claimed in any one of claims 1 to 8 and message transmitting means, each of said message transmitting means being connected to each of said message receiving means by a bus network;
the message sending device is used for carrying out standardized processing on the message to be sent of the message sending equipment so as to obtain a standard format message, and sending the standard format message to the corresponding message receiving device through the bus network.
10. The processor communication system according to claim 9, wherein the message sending means is specifically configured to:
and acquiring a device identification identifier and a context identification identifier corresponding to the message sending device, and generating a standard format message according to the device identification identifier, the context identification identifier and the message to be sent.
CN202310508037.4A 2023-05-06 2023-05-06 Message receiving device and processor communication system Pending CN116450563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310508037.4A CN116450563A (en) 2023-05-06 2023-05-06 Message receiving device and processor communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310508037.4A CN116450563A (en) 2023-05-06 2023-05-06 Message receiving device and processor communication system

Publications (1)

Publication Number Publication Date
CN116450563A true CN116450563A (en) 2023-07-18

Family

ID=87128650

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310508037.4A Pending CN116450563A (en) 2023-05-06 2023-05-06 Message receiving device and processor communication system

Country Status (1)

Country Link
CN (1) CN116450563A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117149837A (en) * 2023-10-27 2023-12-01 建信金融科技有限责任公司 Message sending method, device, electronic equipment and computer readable medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117149837A (en) * 2023-10-27 2023-12-01 建信金融科技有限责任公司 Message sending method, device, electronic equipment and computer readable medium

Similar Documents

Publication Publication Date Title
CN105511954A (en) Method and device for message processing
CN103141058A (en) Network interface controller for virtual and distributed services
CN111294235B (en) Data processing method, device, gateway and readable storage medium
CN111163018B (en) Network equipment and method for reducing transmission delay thereof
CN110532208B (en) Data processing method, interface conversion structure and data processing equipment
US11095626B2 (en) Secure in-line received network packet processing
CN116450563A (en) Message receiving device and processor communication system
US11010165B2 (en) Buffer allocation with memory-based configuration
CN106487549A (en) With the method communicated nothing central processing unit veneer and communication apparatus
CN104378161A (en) FCoE protocol acceleration engine IP core based on AXI4 bus formwork
CN106713183B (en) Interface board of network equipment, network equipment and message forwarding method
CN105610730A (en) Method and system for message interaction between CPU and network equipment
CN114338801B (en) Lightweight publishing and subscribing method and system suitable for intelligent measuring equipment, equipment and storage medium
CN109286564B (en) Message forwarding method and device
CN116185499B (en) Register data transmission method, register cache module, intelligent device and medium
CN115617733B (en) RapidIO network message conversion method, system and equipment
CN115344522B (en) Message conversion channel, message conversion device, electronic equipment and exchange equipment
CN108521416B (en) ECN integrated circuit board
US11038856B2 (en) Secure in-line network packet transmittal
CN101404656A (en) Software interface design method for communicating with third party intelligent equipment protocol
CN108984324A (en) FPGA hardware level of abstraction
CN101938453A (en) Device and method for realizing data transmission between central processing unit and Ethernet
CN115883675A (en) Extensible SPI bus and CAN bus data conversion method
CN113055493B (en) Data packet processing method, device, system, scheduling device and storage medium
CN114897532A (en) Operation log processing method, system, device, equipment and storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Country or region after: China

Address after: Room a-522, 188 Yesheng Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306

Applicant after: Shanghai Suiyuan Technology Co.,Ltd.

Address before: Room a-522, 188 Yesheng Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306

Applicant before: SHANGHAI ENFLAME TECHNOLOGY Co.,Ltd.

Country or region before: China

CB02 Change of applicant information