CN114384354A - Hardware-implemented serial communication high-dynamic-range baud rate identification method and circuit - Google Patents
Hardware-implemented serial communication high-dynamic-range baud rate identification method and circuit Download PDFInfo
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Abstract
The invention provides a hardware-implemented serial communication high dynamic range baud rate identification method and a circuit, wherein the method comprises the following steps: collecting the baud rate of the packet head through a baud rate collecting circuit; accurately identifying data of each bit of the packet head through a bit data acquisition circuit according to the acquired baud rate; and timing judgment is carried out on the width between the adjacent edges in the packet head through a single-bit duration detection circuit. The invention has the beneficial effects that: (1) the recognition range of the baud rate can be greatly improved through a midpoint sampling mechanism, and the correctness of the acquired data is effectively ensured; (2) the whole identification circuit is reset immediately once the baud rate error is detected, so that the initial state can be quickly recovered after the erroneous baud rate is detected, so that the next correct bit rate packet header can be detected in time, and the robustness of the whole baud rate identification circuit is improved; (3) because software execution is not needed, the bandwidth of the CPU can be released to other peripheral devices for use.
Description
Technical Field
The invention relates to the technical field of quick charging of mobile terminal equipment, in particular to a hardware-implemented serial communication high dynamic range baud rate identification method and circuit.
Background
In order to achieve a fast charging of mobile terminal devices, many fast charging protocols have emerged. The fast charging protocol is usually a serial bus, and uses UART as a basic frame structure. The sending end selects a baud rate to send data, starts with a preset character, and the receiving end needs to identify the accurate baud rate according to the preset character of the sent data and further analyzes correct data.
In the existing baud rate identification method, the baud rate identification method is usually realized based on software acquisition, which can greatly occupy the bandwidth and time of a CPU, and in addition, the time of software execution can cause low identification precision and large error.
Disclosure of Invention
The invention aims to provide a hardware-implemented serial communication high-dynamic-range baud rate identification method and a hardware-implemented serial communication high-dynamic-range baud rate identification circuit, and aims to solve the problems that a large amount of bandwidth and time of a CPU (central processing unit) can be occupied in the software-implemented baud rate identification method, and the time of software execution can cause low identification precision and large errors.
The invention provides a hardware-implemented serial communication high dynamic range baud rate identification method, which comprises the following steps:
collecting the baud rate of the packet head through a baud rate collecting circuit;
accurately identifying data of each bit of the packet head through a bit data acquisition circuit according to the acquired baud rate;
and timing judgment is carried out on the width between the adjacent edges in the packet head through a single-bit duration detection circuit.
Further, the method for acquiring the baud rate by the baud rate acquisition circuit includes:
(1) the start bit and the B0 bit are between the first falling edge and the first rising edge; acquiring the time from a first falling edge to a first rising edge through a high-frequency clock signal to obtain a Baud rate BR0 of the currently received byte;
(2) sampling subsequent B1-B6 bits according to the Baud rate BR0 of the currently accepted byte, and putting the sampled samples into a data shift register;
(3) between the first falling edge and the rising edge of the B7 bit, 8 bits including the start bit and B0-B6; acquiring the time from the first falling edge to the rising edge of the B7 bit to obtain the average baud rate BR6 of the B6 bit;
(4) sampling subsequent B7 bits and end bits according to the average baud rate BR6, and putting the samples into a data shift register;
(5) when the end bit is ended, on one hand, judging that the data in the data shift register is a preset fixed value, and on the other hand, judging whether the average baud rate BR6 is in a preset baud rate range; if both conditions are satisfied, the average baud rate BR6 is output as the final acquired baud rate.
Further, the method for accurately identifying the data of each bit of the packet header through the bit data acquisition circuit according to the acquired baud rate comprises the following steps:
(1) calculating the midpoint time of the baud rate according to the collected baud rate;
(2) sampling is carried out on the midpoint of each bit of the packet head according to the midpoint time of the baud rate, so that the data of each bit of the packet head is accurately identified.
Further, the method for determining the timing of the width between adjacent edges in the packet header by the single-bit duration detection circuit includes:
(1) starting baud rate identification from the first falling edge, starting a hardware timer at the same time, and acquiring a timer value T0 when the next edge is reached; restarting the timer at the same time, stopping the timer at the next edge, and repeating the steps until the time is T1, and so on to obtain 7 results of the timer, namely T0, T1, … … and T6; judging whether the timer is in a set baud rate range or not when the timer stops, and if the timer exceeds the set baud rate range, determining that the baud rate is wrong and resetting the whole identification circuit, namely resetting a baud rate acquisition circuit and a bit data acquisition circuit single-bit duration detection circuit;
(2) when the timer is started, whether the timer is in a set baud rate range is judged, if the timer exceeds the set baud rate range, the baud rate is considered to be wrong, and the whole identification circuit is reset, namely the baud rate acquisition circuit and the bit data acquisition circuit are reset, and the single-bit duration detection circuit is also reset;
(3) the 7 results of each timer T0, T1, … …, T6 and 7 results are compared with each other and need to be in the same baud rate range, if the baud rate range is exceeded, the baud rate is considered to be wrong, and the whole identification circuit is reset, namely the baud rate acquisition circuit and the bit data acquisition circuit single-bit duration detection circuit are reset.
The invention provides a hardware-implemented serial communication high dynamic range baud rate identification circuit, which comprises a baud rate acquisition circuit, a bit data acquisition circuit and a single-bit duration detection circuit; the baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are connected with each other;
the baud rate acquisition circuit is used for acquiring the baud rate of the packet header;
the bit data acquisition circuit is used for accurately identifying data of each bit of the packet head according to the acquired baud rate;
and the single-bit duration detection circuit is used for timing and judging the width between adjacent edges in the packet header.
In some embodiments, the baud rate acquisition circuit, the bit data acquisition circuit and the single bit duration detection circuit are implemented by using a counter, a latch and a logic circuit.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
in the serial communication high dynamic range baud rate identification method and circuit realized by hardware, the identification range of the baud rate can be greatly improved by a midpoint sampling mechanism, and the correctness of the acquired data is effectively ensured; (2) the whole identification circuit is reset immediately once the baud rate error is detected, so that the initial state can be quickly recovered after the erroneous baud rate is detected, so that the next correct bit rate packet header can be detected in time, and the robustness of the whole baud rate identification circuit is improved; (3) because software execution is not needed, the bandwidth of the CPU can be released to other peripheral devices for use.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a hardware-implemented serial communication high dynamic range baud rate identification circuit according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a baud rate acquisition circuit according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a bit data acquisition circuit according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a single-bit duration detection circuit according to an embodiment of the present invention.
Fig. 5 is an explanatory diagram of the operation timing of the baud rate acquisition circuit according to the embodiment of the present invention.
Fig. 6 is an explanatory diagram of an operation timing of the bit data acquisition circuit according to the embodiment of the present invention.
Fig. 7 is an explanatory diagram of the operation timing of the single-bit duration detection circuit according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
As shown in fig. 1, the embodiment provides a hardware-implemented serial communication high dynamic range baud rate identification circuit, which includes a baud rate acquisition circuit, a bit data acquisition circuit, and a single-bit duration detection circuit; the baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are connected with each other;
in this embodiment, the baud rate acquisition circuit, the bit data acquisition circuit, and the single-bit duration detection circuit are implemented by using a counter, a latch, and a logic circuit. The method comprises the following specific steps:
the baud rate acquisition circuit is used for acquiring the baud rate of the packet header; the structure of the baud rate acquisition circuit in this embodiment is as shown in fig. 2, and first, rising edge and falling edge detection of a received signal is realized through a trigger D1 and two and gates; counting the number of detected edges (rising edges and falling edges) by a counter C1; when the number of edges is 0, the data reception is started, and at this time, a counter C2 and a counter C3 are started; when the number of the edges is 1, the start bit and the B0 bit are received, the count value of the counter C2 is latched through a latch L1, and the lowest bit (namely, the lowest bit is divided by 2) of the data is removed to obtain a baud rate BR 0; when the number of the edges is 8, the edge indicates that B6 bits are received, the count value of the counter C3 is latched through a latch L2, and the average baud rate BR6 is obtained by removing the lower three bits of data (namely dividing by 8); outputting the acquired baud rate data to an in-place acquisition circuit to provide a data acquisition reference;
the bit data acquisition circuit is used for accurately identifying data of each bit of the packet head according to the acquired baud rate; the structure of the bit data acquisition circuit in this embodiment is shown in fig. 3, where C4 is a counter for acquiring the number of data bits, and when the count value of the counter C4 is less than 6, the baud rate selects BR 0; when the count of the counter C4 is more than 6, selecting BR6 as the baud rate; c3 is a baud rate counter, which starts at the falling edge of uart _ rx, when the count value of the counter C3 reaches half of the selected baud rate, the currently received value is latched by the latch L3, the midpoint sampling of each bit is realized, and the midpoint time of each bit is obtained; when the count value of the counter C3 reaches the value of the selected baud rate, the counter C4 adds a value which indicates that 1 bit of data is acquired, and meanwhile, the counter C3 is cleared and starts counting again; when 8-bit values are collected, namely the counter C4 is added to 8, the value of the register group D2 is latched, and the value is the value of each collected bit; comparing and judging the value with a preset correct value to obtain a signal indicating whether the packet header data is correct or not; outputting the signal result to a baud rate acquisition circuit, and if the acquired data result is wrong, resetting the whole system;
the single-bit duration detection circuit is used for timing and judging the width between adjacent edges in the packet head; the structure of the single-bit duration detection circuit in this embodiment is shown in fig. 4, and timing between adjacent edges is realized; the input signals are the rising edge and the falling edge of the received signals realized in the baud rate acquisition module, when each edge comes, the counter C5 is cleared and starts to count, and meanwhile, the count value of the counter is latched; comparing the latched count value with a preset correct range, and if the comparison result shows that the count value exceeds the preset range, outputting a reset signal to reset the whole system;
the serial communication high dynamic range baud rate identification circuit based on the hardware can realize a hardware-realized serial communication high dynamic range baud rate identification method, can improve the baud rate identification precision through high-frequency clock sampling in the hardware, can identify the dynamic range as 20 percent, reduce the system communication error rate, and simultaneously can release the bandwidth of a CPU (Central processing Unit) for other peripherals to use. The method comprises the following steps:
s1, acquiring the baud rate of the packet header through a baud rate acquisition circuit;
as shown in fig. 5, a packet header with a character of 0xAA is preset, and the method for acquiring the baud rate by the baud rate acquisition circuit includes:
(1) the start bit and the B0 bit are between the first falling edge and the first rising edge; acquiring the time from a first falling edge to a first rising edge by a high-frequency (generally at least 10 times of the baud rate to be acquired, and the higher the frequency, the smaller the error of the baud rate result) clock signal to obtain the baud rate BR0 of the currently accepted bytes;
(2) sampling subsequent B1-B6 bits according to the Baud rate BR0 of the currently accepted byte, and putting the sampled samples into a data shift register;
(3) between the first falling edge and the rising edge of the B7 bit, 8 bits including the start bit and B0-B6; acquiring the time from the first falling edge to the rising edge of the B7 bit to obtain the average baud rate BR6 of the B6 bit; at the moment, the difference between BR0 and BR6 is compared, if the difference exceeds 10%, the baud rate identification is judged to be wrong, and the circuit returns to the initial state;
(4) sampling subsequent B7 bits and end bits according to the average baud rate BR6, and putting the samples into a data shift register;
(5) when the end bit is ended, on one hand, judging that the data in the data shift register is a preset fixed value, and on the other hand, judging whether the average baud rate BR6 is in a preset baud rate range; if both conditions are satisfied, the average baud rate BR6 is output as the final acquired baud rate.
S2, accurately identifying the data of each bit of the packet header through a bit data acquisition circuit according to the acquired baud rate;
as shown in fig. 6, a packet header with a preset character of 0xAA, based on the baud rate acquisition circuit, the B0-B7 bits and the end bit all obtain the baud rate through step S1, and acquire the data of the current bit; the method for accurately identifying the data of each bit of the packet header through the bit data acquisition circuit according to the acquired baud rate comprises the following steps:
(1) based on the baud rate obtained in the step, the midpoint time of the baud rate of each bit is obtained through a hardware counter;
(2) sampling is performed at each bit midpoint of the packet header according to the baud rate midpoint time, such as D0-D7 in fig. 6, so as to accurately identify the data of each bit of the packet header.
Compared with sampling at other positions, the midpoint sampling mechanism in the bit data acquisition circuit can greatly improve the baud rate identification range and effectively ensure the correctness of the acquired data.
S3, timing and judging the width between the adjacent edges in the packet head through the single-bit duration detection circuit;
as shown in fig. 7, the header with the default character of 0xAA has a fixed range of adjacent edge width for data with a fixed baud rate. Therefore, the method for judging the timing of the width between the adjacent edges in the packet header by the single-bit duration detection circuit comprises the following steps:
(1) starting baud rate identification from the first falling edge, starting a hardware timer at the same time, and acquiring a timer value T0 when the next edge is reached; restarting the timer at the same time, stopping the timer at the next edge, and repeating the steps until the time is T1, and so on to obtain 7 results of the timer, namely T0, T1, … … and T6; judging whether the timer is in a set baud rate range or not when the timer stops, and if the timer exceeds the set baud rate range, determining that the baud rate is wrong and resetting the whole identification circuit, namely resetting a baud rate acquisition circuit and a bit data acquisition circuit single-bit duration detection circuit;
(2) when the timer is started, whether the timer is in a set baud rate range is judged, if the timer exceeds the set baud rate range, the baud rate is considered to be wrong, and the whole identification circuit is reset, namely the baud rate acquisition circuit and the bit data acquisition circuit are reset, and the single-bit duration detection circuit is also reset;
(3) the 7 results of each timer T0, T1, … …, T6 and 7 results are compared with each other and need to be in the same baud rate range, if the baud rate range is exceeded, the baud rate is considered to be wrong, and the whole identification circuit is reset, namely the baud rate acquisition circuit and the bit data acquisition circuit single-bit duration detection circuit are reset.
The single-bit duration detection circuit of the invention immediately resets the whole identification circuit once detecting the baud rate error, so that the initial state can be quickly recovered after detecting the error baud rate so as to detect the next correct bit rate packet header in time, thereby improving the robustness of the whole baud rate identification circuit.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A hardware-implemented serial communication high dynamic range baud rate identification method is characterized by comprising the following steps:
collecting the baud rate of the packet head through a baud rate collecting circuit;
accurately identifying data of each bit of the packet head through a bit data acquisition circuit according to the acquired baud rate;
and timing judgment is carried out on the width between the adjacent edges in the packet head through a single-bit duration detection circuit.
2. The hardware-implemented serial communication high-dynamic-range baud rate identification method of claim 1, wherein the method for acquiring the baud rate by the baud rate acquisition circuit comprises:
(1) the start bit and the B0 bit are between the first falling edge and the first rising edge; acquiring the time from a first falling edge to a first rising edge through a high-frequency clock signal to obtain a Baud rate BR0 of the currently received byte;
(2) sampling subsequent B1-B6 bits according to the Baud rate BR0 of the currently accepted byte, and putting the sampled samples into a data shift register;
(3) between the first falling edge and the rising edge of the B7 bit, 8 bits including the start bit and B0-B6; acquiring the time from the first falling edge to the rising edge of the B7 bit to obtain the average baud rate BR6 of the B6 bit;
(4) sampling subsequent B7 bits and end bits according to the average baud rate BR6, and putting the samples into a data shift register;
(5) when the end bit is ended, on one hand, judging that the data in the data shift register is a preset fixed value, and on the other hand, judging whether the average baud rate BR6 is in a preset baud rate range; if both conditions are satisfied, the average baud rate BR6 is output as the final acquired baud rate.
3. The hardware-implemented serial communication high dynamic range baud rate identification method of claim 2, wherein the method for accurately identifying each bit of data in the packet header according to the acquired baud rate by the bit data acquisition circuit comprises:
(1) calculating the midpoint time of the baud rate according to the collected baud rate;
(2) sampling is carried out on the midpoint of each bit of the packet head according to the midpoint time of the baud rate, so that the data of each bit of the packet head is accurately identified.
4. The hardware-implemented serial communication high dynamic range baud rate identification method of claim 3, wherein the method for timing and determining the width between adjacent edges in the packet header by the single-bit duration detection circuit comprises:
(1) starting baud rate identification from the first falling edge, starting a hardware timer at the same time, and acquiring a timer value T0 when the next edge is reached; restarting the timer at the same time, stopping the timer at the next edge, and repeating the steps until the time is T1, and so on to obtain 7 results of the timer, namely T0, T1, … … and T6; judging whether the timer is in a set baud rate range or not when the timer stops, and if the timer exceeds the set baud rate range, determining that the baud rate is wrong and resetting the whole identification circuit, namely resetting a baud rate acquisition circuit and a bit data acquisition circuit single-bit duration detection circuit;
(2) when the timer is started, whether the timer is in a set baud rate range is judged, if the timer exceeds the set baud rate range, the baud rate is considered to be wrong, and the whole identification circuit is reset, namely the baud rate acquisition circuit and the bit data acquisition circuit are reset, and the single-bit duration detection circuit is also reset;
(3) the 7 results of each timer T0, T1, … …, T6 and 7 results are compared with each other and need to be in the same baud rate range, if the baud rate range is exceeded, the baud rate is considered to be wrong, and the whole identification circuit is reset, namely the baud rate acquisition circuit and the bit data acquisition circuit single-bit duration detection circuit are reset.
5. A hardware-implemented serial communication high dynamic range baud rate identification circuit is characterized by comprising a baud rate acquisition circuit, a bit data acquisition circuit and a single-bit duration detection circuit; the baud rate acquisition circuit, the bit data acquisition circuit and the single-bit duration detection circuit are connected with each other;
the baud rate acquisition circuit is used for acquiring the baud rate of the packet header;
the bit data acquisition circuit is used for accurately identifying data of each bit of the packet head according to the acquired baud rate;
and the single-bit duration detection circuit is used for timing and judging the width between adjacent edges in the packet header.
6. The hardware-implemented serial communication high dynamic range baud rate identification circuit of claim 5, wherein the baud rate acquisition circuit, the bit data acquisition circuit and the single bit duration detection circuit are implemented using counters, latches and logic circuits.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114710161A (en) * | 2022-06-06 | 2022-07-05 | 成都市易冲半导体有限公司 | Area optimization method and circuit for ADC channel result calculation |
| CN115202425A (en) * | 2022-09-15 | 2022-10-18 | 成都市易冲半导体有限公司 | IO (input/output) design circuit and method for detecting ultra-low power supply voltage of serial communication bus |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114710161A (en) * | 2022-06-06 | 2022-07-05 | 成都市易冲半导体有限公司 | Area optimization method and circuit for ADC channel result calculation |
| CN114710161B (en) * | 2022-06-06 | 2022-08-16 | 成都市易冲半导体有限公司 | Area optimization method and circuit for ADC channel result calculation |
| CN115202425A (en) * | 2022-09-15 | 2022-10-18 | 成都市易冲半导体有限公司 | IO (input/output) design circuit and method for detecting ultra-low power supply voltage of serial communication bus |
| CN115202425B (en) * | 2022-09-15 | 2022-11-22 | 成都市易冲半导体有限公司 | IO (input/output) design circuit and method for detecting ultra-low power supply voltage of serial communication bus |
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