CN105807679B - Data sampling circuit module, data sampling method and memory storage apparatus - Google Patents
Data sampling circuit module, data sampling method and memory storage apparatus Download PDFInfo
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- CN105807679B CN105807679B CN201410851264.8A CN201410851264A CN105807679B CN 105807679 B CN105807679 B CN 105807679B CN 201410851264 A CN201410851264 A CN 201410851264A CN 105807679 B CN105807679 B CN 105807679B
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Abstract
A kind of data sampling circuit module of present invention offer, data sampling method and memory storage apparatus.The method includes：It receives differential signal and input data crossfire is generated according to the differential signal；Come sampling clock signal and sampled signal is exported according to multiple continuous state switching points of the input data crossfire；And the bit data crossfire corresponding to the input data crossfire is exported according to the sampled signal.
Description
Technical field
The invention relates to a kind of data sampling circuit modules, and in particular to a kind of data sampling circuit mould
Block, data sampling method and memory storage apparatus.
Background technology
In general, in order to save the power consumption of signal transmission, certain signals can be come in a manner of differential signal into
Row transmission.After receiving end device receives one group of differential signal, this differential signal can be restored to a data stream.This
Data stream is made of a series of pulse, and the waveform of these pulses can be related with the bit data to be transmitted.For example,
A certain waveform is to indicate transmitted bit data " 1 ", and another waveform is to indicate transmitted bit data " 0 ".
Traditionally, in order to identify the waveform of each pulse in above-mentioned data stream, when receiving end device can be by one
The very high clock signal of arteries and veins frequency is come the signal that is sampled to this data stream, and obtained by analytical sampling in large quantities
It is the logically high or logic low fallen in data stream, to reconstruct the impulse waveform in data stream.However, this sampling side
Formula needs the very high clock signal of frequency of use, larger for the power consumption of system, and also bad using upper efficiency.
Invention content
A kind of data sampling circuit module of present invention offer, data sampling method and memory storage apparatus, can effectively carry
Rise the efficiency handled the differential signal received.
One example of the present invention embodiment provides a kind of data sampling circuit module comprising differential signal conversion circuit,
Sample circuit and bit data output circuit.The differential signal conversion circuit is receiving differential signal and according to the difference
Sub-signal generates input data crossfire.The sample circuit is electrically connected the differential signal conversion circuit, wherein the sampling
Circuit according to multiple continuous state switching points of the input data crossfire come sampling clock signal and exporting sampled signal.Institute
It states bit data output circuit and is electrically connected the sample circuit and to be exported corresponding to institute according to the sampled signal
State the bit data crossfire of input data crossfire.
In one example of the present invention embodiment, the continuous state switching points belong to the same clock cycle, described continuously to turn
State point includes the first state switching points, the second state switching points and third state switching points, and first state switching points are to belong to the third state switching points
In one of rising edge and failing edge, and second state switching points are its for belonging to the rising edge and the failing edge
In it is another.
In one example of the present invention embodiment, the bit data output circuit includes an at least counting circuit compared with
Circuit.The counting circuit is obtaining the relativeness between the continuous state switching points according to the sampled signal.The ratio
It is electrically connected to the counting circuit compared with circuit and to determine bit according to the relativeness between the continuous state switching points
Data.
In one example of the present invention embodiment, the bit data output circuit further includes output circuit.The output
Circuit is electrically connected to the differential signal conversion circuit with the comparison circuit and to according to the input data crossfire
The bit data crossfire is exported with the bit data.
In one example of the present invention embodiment, the counting circuit includes the first counting circuit, and described first calculates electricity
Road is poor to the first time for calculating first state switching points and second state switching points according to the sampled signal, wherein institute
It states comparison circuit and poor determines the bit data with threshold value and according to comparison result to the first time.
In one example of the present invention embodiment, the counting circuit further includes the second counting circuit, and described second calculates
Circuit is calculating the second time difference of first state switching points and the third state switching points according to the sampled signal.
In one example of the present invention embodiment, the comparison circuit first time it is poor with the threshold value simultaneously
And determine that the operation of the bit data includes according to the comparison result：Judge that the first time is poor whether more than described
The half of second time difference；If the first time poor half more than second time difference, the first bit data is exported；With
And if the first time poor half no more than second time difference, export the second bit data.
In one example of the present invention embodiment, the counting circuit further includes third counting circuit, and the third calculates
Circuit is calculating the third time difference of second state switching points and the third state switching points according to the sampled signal.
In one example of the present invention embodiment, the comparison circuit first time it is poor with the threshold value simultaneously
And determine that the operation of the bit data includes according to the comparison result：Judge that the first time is poor whether more than described
The third time difference；If the first time is poor more than the third time difference, the first bit data is exported；And if described first
Time difference is not more than the third time difference, exports the second bit data.
In one example of the present invention embodiment, the sample circuit include the first sample circuit, the second sample circuit and
Third sample circuit.First sample circuit is sampling the clock signal according to first state switching points and export
First sampled data.Second sample circuit is sampling the clock signal according to second state switching points and export
Second sampled data.The third sample circuit is sampling the clock signal according to the third state switching points and export
Third sampled data.
In one example of the present invention embodiment, first sample circuit, second sample circuit and the third
Sample circuit includes respectively D flip-flop.
Another example of the present invention embodiment provides a kind of data sampling method comprising：Receive differential signal and root
Input data crossfire is generated according to the differential signal；According to multiple continuous state switching points of the input data crossfire come sampling clock
Signal and export sampled signal；And the bit number corresponding to the input data crossfire is exported according to the sampled signal
According to crossfire.
In one example of the present invention embodiment, exported corresponding to the input data crossfire according to the sampled signal
The bit data crossfire the step of include：The opposite pass between the continuous state switching points is obtained according to the sampled signal
System；And bit data is determined according to the relativeness between the continuous state switching points.
In one example of the present invention embodiment, exported corresponding to the input data crossfire according to the sampled signal
The bit data crossfire the step of further include：The ratio is exported according to the input data crossfire and the bit data
Special data stream.
In one example of the present invention embodiment, obtained according to the sampled signal opposite between the continuous state switching points
The step of relationship includes：The first time of first state switching points and second state switching points is calculated according to the sampled signal
Difference, and include the step of determining the bit data according to the relativeness between the continuous state switching points：Compare described first
Time difference and threshold value and bit data is determined according to comparison result.
In one example of the present invention embodiment, obtained according to the sampled signal opposite between the continuous state switching points
The step of relationship further includes：When calculating the second of first state switching points and the third state switching points according to the sampled signal
Between it is poor.
In one example of the present invention embodiment, the first time is poor with the threshold value and according to the ratio
Relatively result includes the step of determining the bit data：Judge that the first time is poor whether more than second time difference
Half；If the first time poor half more than second time difference, the first bit data is exported；And if described first
Time difference is not more than the half of second time difference, exports the second bit data.
In one example of the present invention embodiment, obtained according to the sampled signal opposite between the continuous state switching points
The step of relationship further includes：When calculating third of second state switching points with the third state switching points according to the sampled signal
Between it is poor.
In one example of the present invention embodiment, the first time is poor with the threshold value and according to the ratio
Relatively result includes the step of determining the bit data：Judge that the first time is poor whether more than the third time difference；
If the first time is poor more than the third time difference, the first bit data is exported；And if the first time is poor less
In the third time difference, the second bit data is exported.
In one example of the present invention embodiment, according to the continuous state switching points of the input data crossfire to sample
It states clock signal and includes the step of exporting the sampled signal：The clock signal is sampled according to first state switching points
And export the first sampled data；The clock signal is sampled according to second state switching points and exports the second hits
According to；And it samples the clock signal according to the third state switching points and exports third sampled data.
Another example of the present invention embodiment provides a kind of memory storage apparatus comprising connecting interface unit can answer
Write formula non-volatile memory module and memorizer control circuit unit.The connecting interface unit is electrically connected to host
System.The reproducible nonvolatile memorizer module includes multiple entity erased cells.The memorizer control circuit list
Member is electrically connected to the connecting interface unit and the reproducible nonvolatile memorizer module.The connecting interface unit
Including data sampling circuit module.The data sampling circuit module includes differential signal conversion circuit, sample circuit and bit
Data output circuit.The differential signal conversion circuit inputs to receive differential signal and be generated according to the differential signal
Data stream.The sample circuit is electrically connected the differential signal conversion circuit, wherein the sample circuit is to according to institute
The multiple continuous state switching points for stating input data crossfire carry out sampling clock signal and export sampled signal.The bit data output
Circuit is electrically connected the sample circuit and to be exported corresponding to the input data crossfire according to the sampled signal
Bit data crossfire.
Based on above-mentioned, after the differential signal received is converted to input data crossfire, the present invention can be defeated according to this
The sampled signal for entering multiple continuous state switching points of data stream to be sampled to a clock signal, and being obtained according to sampling
To generate the bit data crossfire corresponding to the input data crossfire.Thereby, the differential signal to receiving can effectively be promoted
The efficiency handled.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make
Carefully it is described as follows.
Description of the drawings
Fig. 1 is the schematic diagram of the data sampling circuit module shown by an exemplary embodiment according to the present invention；
Fig. 2 is the schematic diagram of the generation input data crossfire shown by an exemplary embodiment according to the present invention；
Fig. 3 is the schematic diagram of the input data crossfire shown by an exemplary embodiment according to the present invention；
Fig. 4 is the schematic diagram of the data sampling circuit module shown by an exemplary embodiment according to the present invention；
Fig. 5 is the schematic diagram of the data sampling circuit module shown by another exemplary embodiment according to the present invention；
Fig. 6 is the flow chart of the data sampling method shown by an exemplary embodiment according to the present invention；
Fig. 7 is the signal of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention
Figure；
Fig. 8 is the schematic diagram of the computer system and input/output device shown by an exemplary embodiment according to the present invention；
Fig. 9 is the signal of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention
Figure；
Figure 10 is the schematic block diagram for showing memory storage apparatus shown in Fig. 7；
Figure 11 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Reference sign：
10,40,50：Data sampling circuit module；
11,41：Differential signal conversion circuit；
12,42,421~423：Sample circuit；
13,43：Bit data output circuit；
44：Clock signal generation circuit；
411：Difference amplifier；
4210,4220,4230：D flip-flop；
431,432,532：Counting circuit；
433,533：Comparison circuit；
434：Output circuit；
BD：Bit data；
BDS：Bit data crossfire；
CS：Clock signal；
D1~D4：Section；
IDS：Input data crossfire；
RXDP,RXDN：Differential signal；
SD, SD1~SD3：Sampled signal；
TD1,TD2：Time difference；
TP1~TP11：State switching points；
WV21~WV26, WV31~WV35：Pulse；S601~S603：Step；
100：Memory storage apparatus；
1000：Host system；
1100：Computer；
1102：Microprocessor；
1104：Random access memory；
1106：Input/output device；
1108：System bus；
1110：Data transmission interface；
1202：Mouse；
1204：Keyboard；
1206：Display；
1208：Printer；
1212：USB flash disk；
1214：Storage card；
1216：Solid state disk；
1310：Digital camera；
1312：SD card；
1314：Mmc card；
1316：Memory stick；
1318：CF cards；
1320：Embedded storage device；
1002：Connecting interface unit；
1004：Memorizer control circuit unit；
1006：Reproducible nonvolatile memorizer module；
304 (0)~304 (R)：Entity erased cell；
202：Memory management circuitry；
204：Host interface；
206：Memory interface；
252：Buffer storage；
254：Electric power management circuit；
256：Error checking and correction circuit.
Specific implementation mode
Multiple embodiments set forth below illustrate the present invention, however the present invention be not limited only to shown in multiple embodiments.Again
Combination appropriate is also still allowed between embodiment." electricity used in this case specification full text (including claim)
Property connection " word can refer to any direct or indirect connection means.For example, if it is described herein that first device is electrically connected at
Second device, then should be construed as the first device can be directly connected to the second device or the first device can be with
It is coupled indirectly to the second device by other devices or certain connection means.In addition, " signal " word can refer at least one
Electric current, voltage, charge, temperature, data or any other one or more signal.
Fig. 1 is the schematic diagram of the data sampling circuit module shown by an exemplary embodiment according to the present invention.
Fig. 1 is please referred to, data sampling circuit module 10 includes differential signal conversion circuit 11, sample circuit 12 and bit number
According to output circuit 13.
Differential signal conversion circuit 11 to receive differential signal RXDP and RXDN and according to differential signal RXDP with
RXDN generates input data crossfire IDS.Wherein, differential signal RXDP and RXDN is to modulate (Pulse using pulse width respectively
Width Modulation, abbreviation PWM) pulse width modulating signal caused by technology.Differential signal RXDP's and RXDN shakes
It is identical, and the opposite in phase of differential signal RXDP and RXDN.In this exemplary embodiment, 11 meeting of differential signal conversion circuit
The differential signal RXDP of simulation and RXDN are converted to the input data crossfire IDS of number.
Fig. 2 is the schematic diagram of the generation input data crossfire shown by an exemplary embodiment according to the present invention.
Fig. 2 is please referred to, if receiving one in a pulse WV21 and differential signal RXDN in differential signal RXDP
Pulse WV21 and WV22 can be converted to an arteries and veins in input data crossfire IDS by pulse WV22, differential signal conversion circuit 11
Rush WV23.Wherein, the length of pulse WV21~WV23 all meets a clock cycle, and logic low (logic in pulse WV23
Low section D1) is longer than the section D2 of wherein logically high (logic high).If in addition, receiving in differential signal RXDP
A pulse WV25 in one pulse WV24 and differential signal RXDN, then differential signal conversion circuit 11 can by pulse WV24 with
WV25 is converted to a pulse WV26 in input data crossfire IDS.Wherein, the length of pulse WV24~WV26 also all meets one
A clock cycle, and the section D3 of logic low is shorter than wherein logically high section D4 in pulse WV26.
In this exemplary embodiment, pulse WV23 and WV26 are indicating different types of bit data.For example, pulse
WV23 indicates bit data " 1 ", and pulse WV26 indicates bit data " 0 ".The needs of data sampling circuit module 10 identify
Pulse WV23 and WV26 in input data crossfire IDS, to export corresponding bit data.In another exemplary embodiment,
Pulse WV23 can also indicate bit data " 0 ", and pulse WV26 can also indicate bit data " 1 ".In addition, in another model
Example embodiment in, in input data crossfire IDS the pulse of different wave can also be used to indicate arbitrary two kinds of different types and ratio
The bit data of special not limited to.Data sampling circuit module 10 can export corresponding bit according to input data crossfire IDS
Data.
Sample circuit 12 is electrically connected differential signal conversion circuit 11.Sample circuit 12 is to according to input data crossfire
Multiple continuous state switching points (turn states) in IDS sample a clock signal and export sampled signal SD.Here,
One state switching points refers to pulse to be converted to logic low or is converted to logically high place from logic low from logically high；And clock signal
It is, for example, then an internal clock signal either data sampling circuit module 10 that data sampling circuit module 10 voluntarily generates
The clock signal that the electronic device (for example, memory storage apparatus or memorizer control circuit unit) at place is provided.At this time
The clock frequency of arteries and veins signal can be higher than the clock frequency of input data crossfire IDS.For example, the clock frequency of this clock signal can be with
It is 5~6 times of the clock frequency of input data crossfire IDS.For example, it is assumed that the clock frequency of a pulse shown in Fig. 2 is 72
Megahertz (Mega Hertz, abbreviation MHz), then the clock frequency of this clock signal may, for example, be 360~432 megahertzs.So
And the clock frequency of this clock signal can also be higher or lower, and the clock frequency and input data of this clock signal
Relationship between the clock frequency of crossfire IDS can also be adjusted depending on the demand in practice, and the present invention does not limit.In addition,
Sampled signal SD is indicating the relativeness of the multiple continuous state switching points sampled in time.
Bit data output circuit 13 is electrically connected sample circuit 12.Bit data output circuit 13 is to according to sampling letter
Number SD exports the bit data crossfire BDS corresponding to input data crossfire IDS.For example, bit data output circuit 13 can root
The relativeness of multiple state switching points in input data crossfire IDS in time is obtained according to sampled signal SD, it is opposite according to this
Relationship determines the waveform and the data bit representated by it of each pulse in input data crossfire IDS, and exports according to this
Corresponding data bit crossfire BDS.
Fig. 3 is the schematic diagram of the input data crossfire shown by an exemplary embodiment according to the present invention.
Please refer to Fig. 3, it is assumed that arteries and veins of the input data crossfire IDS including representing bit data " 1 ", " 0 ", " 0 ", " 1 " and " 1 "
Rush WV31~WV35 (pulse is divided with a clock cycle), sample circuit 12 can according to state switching points TP1~TP11 come
One clock signal of sampling simultaneously exports corresponding output sampled signal SD.Bit data output circuit 13 can be according to this sampled signal
SD identifies that the waveform of each pulse WV31~WV35 is to belong in Fig. 2 the waveform of pulse WV23 or WV26 and defeated according to this
Go out corresponding data bit crossfire BDS.
By taking pulse WV31 as an example, sample circuit 12 can be according to state switching points TP1, TP2 and TP3 for belonging to the same clock cycle
Carry out sampling clock signal.Wherein, state switching points TP1 and TP3 refer respectively to pulse WV31 from it is logically high be converted to logic low in place of, and
And state switching points TP2 refers to then that pulse WV7 is converted to logically high place from logic low.In other words, state switching points TP1 and TP3 is to belong to
The failing edge (falling edges) of pulse WV31, and state switching points TP2 is the rising edge (raising for belonging to pulse WV31
edge).According to the clock signal sampled, sample circuit 12 can export corresponding sampled signal SD.Here, sampled signal SD can
To indicate the relativeness of state switching points TP1, TP2 and TP3 in time.For example, sampled signal SD may indicate that state switching points TP1 with
The time difference of the time difference of TP2, the time difference of state switching points TP1 and TP3 and/or state switching points TP2 and TP3.According to sampled signal SD,
Bit data output circuit 13 can learn time difference of state switching points TP1 and TP2 less than state switching points TP2 and TP3 time difference (that is,
The waveform of pulse WV31 is the waveform for belonging to pulse WV23 in Fig. 2), to determine that pulse WV31 is to indicate bit data " 1 ".
With pulse WV32 for another example, sample circuit 12 can be according to state switching points TP3, TP4 for belonging to the same clock cycle
And TP5 carrys out sampling clock signal.Wherein, state switching points TP3 and TP5 refer respectively to pulse WV32 from it is logically high be converted to logic low it
Place, and state switching points TP4 refers to then that pulse WV32 is converted to logically high place from logic low.In other words, state switching points TP3 and TP5
It is to belong to the failing edge of pulse WV32, and state switching points TP2 is the rising edge for belonging to pulse WV32.According to the clock pulse letter sampled
Number, sample circuit 12 can export corresponding sampled signal SD.Here, sampled signal SD can be used to indicate state switching points TP3, TP4 and
The relativeness of TP5 in time.For example, sampled signal SD may indicate that the time difference of state switching points TP3 and TP4, state switching points TP3 with
The time difference of TP5 and/or the time difference of state switching points TP4 and TP5.According to sampled signal SD, bit data output circuit 13 can obtain
Know time difference of the time difference more than state switching points TP4 and TP5 of state switching points TP3 and TP4 (that is, the waveform of pulse WV32 is to belong to Fig. 2
The waveform of middle pulse WV26), to determine that pulse WV32 is to indicate bit data " 0 ".Above-mentioned identification pulse WV31's and WV32
The operation of waveform can be applied to identification pulse WV33~WV35, just not repeat to repeat herein.
It is noted that above-mentioned exemplary embodiment is to indicate the phase of state switching points in time with the time difference of state switching points
To relationship, however, in another exemplary embodiment, the relativeness of state switching points in time can also be between state switching points
The conversion frequency of high and low logic or the modes such as metering number indicate in distance or signal, and the present invention does not limit.In addition,
In another exemplary embodiment, if by the phasing back of input data crossfire IDS, state switching points TP1 and TP3, which can be changed into, to be belonged to
The rising edge of pulse WV31, and state switching points TP2 can change into the failing edge for belonging to pulse WV31, remaining state switching points TP4~
TP11 and so on.
Fig. 4 is the schematic diagram of the data sampling circuit module shown by an exemplary embodiment according to the present invention.
Fig. 4 is please referred to, data sampling circuit module 40 includes differential signal conversion circuit 41, sample circuit 42, bit number
According to output circuit 43 and clock pulse signal generating circuit 44.Clock signal generation circuit 44 is providing clock signal CS.For example, when
Arteries and veins signal generating circuit 44 includes an oscillator (oscillator).
Differential signal conversion circuit 41 includes difference amplifier 411.Difference amplifier 411 is receiving differential signal RXDP
Differential amplification is executed to generate input data crossfire IDS with RXDN and according to differential signal RXDP and RXDN.
Sample circuit 42 includes sample circuit 421~423.Sample circuit 421~423 is receiving input data crossfire
IDS.Sample circuit 421~423 can carry out clock signal CS according to continuous multiple state switching points in input data crossfire IDS
It samples and exports sampled signal SD1~SD3 respectively.Belong to the same clock cycle in analyzing input data crossfire IDS
When one pulse, sampled signal SD1~SD3 is to indicate 3 continuous state switching points of this pulse (for example, the transition in Fig. 3
Point TP1~TP3) relativeness in time.
In this exemplary embodiment, sample circuit 421 includes D flip-flop (D-type flip-flop) 4210, sampling
Circuit 422 includes D flip-flop 4220, and sample circuit 423 includes D flip-flop 4230.Due to D flip-flop 4210~
4230, which are all based on the positive of input data crossfire IDS, triggers along (that is, rising edge) to be sampled to clock signal CS, therefore inputs
Data stream IDS can first pass through phase inverter (Inverter) nor gate (Not before being input to D flip-flop 4210
Gate) element is to carry out phasing back.Thereby, when analyzing pulse WV31 shown in Fig. 3, sample circuit 422 can be according to transition
Point TP1 carrys out sampling clock signal CS, and sample circuit 421 can be according to state switching points TP2 come sampling clock signal CS, and sample circuit
423 can be according to state switching points TP3 come sampling clock signal CS.
Bit data output circuit 43 includes counting circuit 431, counting circuit 432, comparison circuit 433 and output circuit
434.Counting circuit 431 can also be embodied as the same circuit or more circuit with counting circuit 432, and the present invention is not limited
System.Counting circuit 431 is obtained according to sampled signal SD1~SD3 in input data crossfire IDS with counting circuit 432
The relativeness of multiple continuous state switching points.Comparison circuit 433 according to this relativeness determining in input data crossfire IDS
The waveform of each pulse and the data bit representated by it.Output circuit 434 is to the ratio that is exported according to comparison circuit 433
Special data export corresponding data bit crossfire BDS.Come to bit data output circuit below according to the exemplary embodiment of Fig. 4
43 are described in detail.
Counting circuit 431 is electrically connected to sample circuit 421 and 422 and to receive sampled signal SD1 and SD2.Meter
Two state switching points indicated by sampled signal SD1 and SD2 can be calculated and export according to sampled signal SD1 and SD2 by calculating circuit 431
Time difference TD1.For example, in this exemplary embodiment, when analyzing pulse WV31 shown in Fig. 3, time difference TD1 is transition
The time difference of point TP1 and TP2.
Counting circuit 432 is electrically connected to sample circuit 422 and 423 and to receive sampled signal SD2 and SD3.Meter
Two state switching points indicated by sampled signal SD2 and SD3 can be calculated and export according to sampled signal SD2 and SD3 by calculating circuit 431
Time difference TD2.For example, in this exemplary embodiment, when analyzing pulse WV31 shown in Fig. 3, time difference TD2 is transition
The time difference of point TP1 and TP3.
Comparison circuit 433 is electrically connected to counting circuit 431 and 432.Comparison circuit 433 to receiving time difference TD1 with
TD2 and time difference TD1 is compared with a threshold value.According to the comparison result of time difference TD1 and this threshold value, compare
Circuit 433 can determine a corresponding bit data BD.In this exemplary embodiment, comparison circuit 433 can be by time difference TD2's
Half is as this threshold value.Thereby, when analyzing input data crossfire IDS shown in Fig. 3, comparison circuit 433 can judge the time
Whether poor TD1 is more than the half of time difference TD2；If time difference TD1 is more than the half of time difference TD2, comparison circuit 433 can determine
Export bit data " 0 "；If time difference TD1 is not more than the half of (for example, being less than or equal to) time difference TD2, comparison circuit
433 can determine output bit data " 1 ".Above-mentioned acquisition time difference TD1 is compared simultaneously with TD2, by time difference TD1 with threshold value
And determine that the operation of a corresponding bit data can be repeatedly executed according to this, until each in input data crossfire IDS
Until pulse is all analyzed.For example, correspond to input data crossfire IDS shown in Fig. 3, bit data " 1 ", " 0 ", " 0 ",
" 1 " and " 1 " can be determined and be exported.
Output circuit 434 is electrically connected to differential signal conversion circuit 41 with comparison circuit 433 and to receive input
Data stream IDS and bit data BD.Output circuit 434 can export ratio according to input data crossfire IDS and bit data BD
Special data stream BDS.Specifically, output circuit 434 is to be arrived according to the clock pulse of input data crossfire IDS to sample received in sequence
Bit data BD to export bit data crossfire BDS.Wherein, according to the clock pulse of input data crossfire IDS come sampling bits number
The clock pulse pair of the bit data BD and input data crossfire IDS that arrive 434 received in sequence of output circuit are similar to according to the operation of BD
Together.
It is noted that Fig. 4 is only one example of the present invention embodiment, the present invention is not by the layout type of sample circuit
It is limited to the layout type of sample circuit 42 as shown in Figure 4.If the electric connection mode of sample circuit 421~423 and/or its
Internal circuit design changes, then the state switching points sampled in each pulse where sample circuit 421~423 may change
Become, and the judgement operation that comparison circuit 433 executes may also can correspond to change.
Fig. 5 is the schematic diagram of the data sampling circuit module shown by another exemplary embodiment according to the present invention.
Please refer to Fig. 5, the difference of the exemplary embodiment of this exemplary embodiment and Fig. 4 is, in this exemplary embodiment
In, counting circuit 532 is electrically connected to sample circuit 421 and 423 and to receive sampled signal SD1 and SD3.Calculate electricity
Road 532 can according to sampled signal SD1 and SD3 come calculate and export two state switching points indicated by sampled signal SD1 and SD3 when
Between difference TD2.For example, in this exemplary embodiment, when analyzing pulse WV31 shown in Fig. 3, time difference TD2 is state switching points
The time difference of TP2 and TP3.Comparison circuit 533 can receiving time difference TD1 and TD2 and by time difference TD1 and a threshold value into
Row compares.According to the comparison result of time difference TD1 and this threshold value, comparison circuit 433 can determine a corresponding bit data
BD。
Another difference of this exemplary embodiment and the exemplary embodiment of Fig. 4 is, in this exemplary embodiment, compares
Circuit 533 can be using time difference TD2 as this threshold value.Thereby, more electric when analyzing input data crossfire IDS shown in Fig. 3
Road 533 can judge whether time difference TD1 is more than time difference TD2；If time difference TD1 is more than time difference TD2,533 meeting of comparison circuit
Determine output bit data " 0 "；If time difference TD1 is not more than (for example, being less than or equal to) time difference TD2, comparison circuit 533
It can determine output bit data " 1 ".Corresponding to input data crossfire IDS shown in Fig. 3, bit data " 1 ", " 0 ", " 0 ", " 1 "
And " 1 " can equally be determined and be exported by comparison circuit 533.
It is noted that although the exemplary embodiment of Fig. 5 is reached in a manner of the electric connection for changing sample circuit
Specific function can also be to be reached by changing the internal circuit configuration of sample circuit however, in another exemplary embodiment
To same or analogous function.For example, in another exemplary embodiment of Fig. 4, if by being originally arranged in sample circuit 421
Phase inverter nor gate element is removed and is changed to be arranged in sample circuit 422 with to the defeated of D flip-flop 4220 to be input to
Enter data stream IDS and execute phasing back, then equally can reach and change the function that the electric connection mode of sample circuit is provided.
In addition, Fig. 4 and the circuit structure of data sampling circuit module illustrated in fig. 5 are only example, any useful electronic component is all
It can be added into Fig. 4 and data sampling circuit module illustrated in fig. 5 by additional, to meet the demand in practice.
Fig. 6 is the flow chart of the data sampling method shown by an exemplary embodiment according to the present invention.
Fig. 6 is please referred to, in step s 601, differential signal is received and input data string is generated according to the differential signal
Stream.In step S602, according to multiple continuous state switching points of the input data crossfire come sampling clock signal and export adopt
Sample signal.In step S603, the bit data string corresponding to the input data crossfire is exported according to the sampled signal
Stream.
However, each step has been described in detail as above in Fig. 6, just repeat no more herein.It is worth noting that, respectively being walked in Fig. 6
Suddenly multiple programs or circuit are may be embodied as, the present invention does not limit.The example above in addition, method of Fig. 6 can arrange in pairs or groups
Embodiment uses, and can also be used alone, the present invention does not limit.
In this exemplary embodiment, data sampling circuit module set forth above is to be used for memory with data sampling method
In storage device (also referred to as, storage system), or for controlling the memory control of this memory storage apparatus
In circuit unit processed.However, in another exemplary embodiment, data sampling circuit module set forth above and data sampling method
Can also be not to be subject to for various electronic devices or communication device, the present invention such as smart mobile phone, tablet computer, laptops
Limitation.
In general, memory storage apparatus includes reproducible nonvolatile memorizer module and controller (also referred to as, control
Circuit processed).Being commonly stored device storage device is used together with host system, so that host system can write data into storage
Device storage device reads data from memory storage apparatus.
Fig. 7 is the signal of the host system and memory storage apparatus shown by an exemplary embodiment according to the present invention
Figure.Fig. 8 is the schematic diagram of the computer system and input/output device shown by an exemplary embodiment according to the present invention.Fig. 9 is
The schematic diagram of host system and memory storage apparatus shown by an exemplary embodiment according to the present invention.
Fig. 7 is please referred to, host system 1000 generally comprises computer 1100 and input/output (input/output, abbreviation I/
O) device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, abbreviation
RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 include as Fig. 2 mouse 1202,
Keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Fig. 8
1106, input/output device 1106 can further include other devices.
Memory storage apparatus 100 is electrically connected by data transmission interface 1110 and the other elements of host system 1000
It connects.By the operation of microprocessor 1102, random access memory 1104 and input/output device 1106 can write data into
Memory storage apparatus 100 reads data from memory storage apparatus 100.For example, memory storage apparatus 100 can be
What USB flash disk 1212, storage card 1214 or solid state disk (Solid State Drive, abbreviation SSD) 1216 as shown in Figure 8 waited can
Manifolding formula non-volatile memory storage device.
In general, host system 1000 is that can substantially coordinate with memory storage apparatus 100 to store appointing for data
Meaning system.Although in this exemplary embodiment, host system 1000 is explained with computer system, however, of the invention another
Host system 1000 can be digital camera, video camera, communication device, audio player or video playing in one exemplary embodiment
The systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage dress
Set is then its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF cards 1318 or embedded
Storage device 1320 (as shown in Figure 9).Embedded storage device 1320 includes embedded multi-media card (Embedded MMC, letter
Claim eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host system.
Figure 10 is the schematic block diagram for showing memory storage apparatus shown in Fig. 7.
Figure 10 is please referred to, memory storage apparatus 100 includes connecting interface unit 1002, memorizer control circuit unit
1004 with reproducible nonvolatile memorizer module 1006.
In this exemplary embodiment, connecting interface unit 1002 is compatible with Serial Advanced Technology Attachment (Serial
Advanced Technology Attachment, abbreviation SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited to
This, connecting interface unit 1002 can also be to meet parallel advanced technology annex (Parallel Advanced Technology
Attachment, abbreviation PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and
Electronic Engineers, abbreviation IEEE) 1394 standards, high speed peripheral component interlinkage (Peripheral Component
Interconnect Express, abbreviation PCI Express) standard, universal serial bus (Universal Serial Bus,
Abbreviation USB) standard, a ultrahigh speed generation (Ultra High Speed-I, abbreviation UHS-I) interface standard, two generation of ultrahigh speed
(Ultra High Speed-II, abbreviation UHS-II) interface standard, safe digital (Secure Digital, abbreviation SD) interface
Standard, memory stick (Memory Stick, abbreviation MS) interface standard, multimedia storage card (Multi Media Card, abbreviation
MMC) interface standard, compact flash (Compact Flash, abbreviation CF) interface standard, IDE (Integrated
Device Electronics, abbreviation IDE) standard or other suitable standards.In this exemplary embodiment, connecting interface unit
It can be encapsulated in memorizer control circuit unit in a chip, or be laid in a chip for including memorizer control circuit unit
Outside.
In an exemplary embodiment, above-mentioned data sampling circuit module 10,40 or 50 is disposed on connecting interface unit
In 1002, to can receive differential signal RXDP from host system 1000 and RXDN and export corresponding bit data string
BDS is flowed so that memorizer control circuit unit 1004 uses.
Memorizer control circuit unit 1004 to execute in the form of hardware or form of firmware implement multiple logic gates or
Control instruction, and data are carried out in reproducible nonvolatile memorizer module 1006 according to the instruction of host system 1000
Write-in, the operations such as read and erase.
Reproducible nonvolatile memorizer module 1006 is electrically connected to memorizer control circuit unit 1004, and
The data being written to host system 1000.Reproducible nonvolatile memorizer module 1006 is erased list including entity
First 304 (0)~304 (R).Entity erased cell 304 (0)~304 (R) can belong to the same memory crystal grain (die) or belong to
In different memory crystal grains.Each entity erased cell is respectively provided with a plurality of entity program units, wherein belonging to same
The entity program unit of a entity erased cell can be written independently and simultaneously be erased.In this exemplary embodiment,
Each entity erased cell is made of 64 entity program units.However, in other exemplary embodiments of the present invention, often
One entity erased cell is made of 128,256 entity program units or any other a entity program unit.
In more detail, entity program unit is the minimum unit of sequencing.That is, entity program unit is write-in number
According to minimum unit.For example, entity program unit is physical page or entity fan (sector).If entity program unit
For physical page, then each entity program unit generally includes data bit area and redundancy ratio special zone.It wraps in data bit area
Fanned containing multiple entities, to store the data of user, and redundancy ratio special zone to storage system data (for example, mistake is more
Code).In this exemplary embodiment, each data bit area includes that 32 entities are fanned, and the size of entity fan is 512
Byte (byte, abbreviation B).However, also may include 8,16 or number more in other exemplary embodiments, in data bit area
More or less entity fan, the present invention are not intended to limit the size and number of entity fan.On the other hand, entity erased cell is to smear
The least unit removed.Also that is, each entity erased cell contains the storage unit of minimal amount being erased together.For example, real
Body erased cell is physical blocks.
In this exemplary embodiment, reproducible nonvolatile memorizer module 1006 is multi-level unit (Multi Level
Cell, abbreviation MLC) NAND type flash memory module be (that is, can store quickly depositing for 2 bit datas in a storage unit
Memory modules).However, the invention is not limited thereto, it is single that reproducible nonvolatile memorizer module 1006 can also be single-order storage
First (Single Level Cell, SLC) NAND type flash memory module is (that is, can store 1 bit in a storage unit
The flash memory module of data), Complex Order storage unit (Trinary Level Cell, TLC) NAND type fast storage
Module (that is, the flash memory module of 3 bit datas can be stored in a storage unit), other flash memory modules or
Other memory modules with the same characteristics.
Figure 11 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Figure 11 is please referred to, memorizer control circuit unit 1004 includes memory management circuitry 202, host interface 204, deposits
Memory interface 206 and data sampling circuit module 208.
Memory management circuitry 202 to control memory control circuit unit 1004 integrated operation.Specifically, it deposits
Reservoir, which manages circuit 202, has multiple control instructions, and when memory storage apparatus 100 operates, these control instruction meetings
It is performed the operations such as to carry out the write-in of data, read and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is implemented with form of firmware.For example,
Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to
Order is programmed in so far read-only memory.When memory storage apparatus 100 operates, these control instructions can be by microprocessor
Unit is executed the operations such as to carry out the write-in of data, read and erase.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also program form deposit
The specific region of reproducible nonvolatile memorizer module 1006 is stored in (for example, being exclusively used in storage system in memory module
The system area of data) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only memory (not
Show) and random access memory (not shown).In particular, this read-only memory has driver, and work as memory control
When circuit unit 1004 processed is enabled, microprocessor unit can first carry out this driver section will be stored in duplicative it is non-easily
Control instruction in the property lost memory module 1006 is loaded into the random access memory of memory management circuitry 202.Later,
Microprocessor unit such as can run these control instructions to carry out the write-in of data, read and erase at the operations.
In addition, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also a hardware
Form is implemented.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity
Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity
Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores
Single Component Management circuit is managing the entity erased cell of reproducible nonvolatile memorizer module 1006；Memory write-in electricity
Road is non-easily to duplicative to write data into assign write instruction to reproducible nonvolatile memorizer module 1006
In the property lost memory module 1006；Memory reading circuitry to reproducible nonvolatile memorizer module 1006 assigning reading
Instruction fetch from reproducible nonvolatile memorizer module 1006 to read data；Memory erases circuit pair can make carbon copies
Formula non-volatile memory module 1006 assign erase instruction with by data from reproducible nonvolatile memorizer module 1006
In erase；And data processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 1006 and
The data read from reproducible nonvolatile memorizer module 1006.
Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identify host system
1000 instructions transmitted and data.That is, the instruction that host system 1000 is transmitted can pass through host interface with data
204 are sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible with SATA standard.So
And, it should be understood that the invention is not limited thereto, and host interface 204 can also be to be compatible with PATA standards, the marks of IEEE 1394
Standard, PCI Express standards, USB standard, UHS-I interface standards, UHS-II interface standards, SD standards, MS standards, MMC mark
Standard, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative
Property memory module 1006.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 1006 can be via
Memory interface 206 is converted to the 1006 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if depositing
When reservoir management circuit 202 will access reproducible nonvolatile memorizer module 1106, memory interface 206 can transmit correspondence
Instruction sequence.These instruction sequences may include one or more signals, or the data in bus.For example, being instructed reading
In sequence, the information such as identification code, the storage address of reading are will include.
In an exemplary embodiment, memorizer control circuit unit 1004 further includes buffer storage 252, power management electricity
Road 254 and error checking and correction circuit 256.
Buffer storage 252 is electrically connected to memory management circuitry 202 and is configured to temporarily store come from host system
1000 data and the data for instructing or coming from reproducible nonvolatile memorizer module 1006.
Electric power management circuit 254 is electrically connected to memory management circuitry 202 and stores to control memory fill
Set 100 power supply.
Error checking and correction circuit 256 is electrically connected to memory management circuitry 202 and to execute wrong inspection
It surveys with correction program to ensure the correctness of data.Specifically, it is connect from host system 1000 when memory management circuitry 202
When receiving write instruction, error checking and correction circuit 256 can be that the data of this corresponding write instruction generate corresponding mistake inspection
Survey and correcting code (Error Checking and Correcting Code, abbreviation ECC Code), and memory management electricity
The data of this corresponding write instruction can be written with corresponding error checking and correction code to duplicative is non-volatile and be deposited by road 202
In memory modules 1006.Later, it is read from reproducible nonvolatile memorizer module 1006 when memory management circuitry 202
This data corresponding error checking and correction code can be read when data simultaneously, and error checking and correction circuit 256 can foundation
This error checking and correction code executes error checking and correction program to read data.
It is noted that in an exemplary embodiment, if memorizer control circuit unit 1004 or memory storage dress
A wake-up signal can be sent extremely in non-normal workings pattern, host systems 1000 such as suspend mode, standby or low power consumptions by setting 100
Memory storage apparatus 100.This wake-up signal is to by memorizer control circuit unit 1004 or memory storage apparatus 100
It is waken up from the non-normal workings patterns such as suspend mode, standby or low power consumption.By above-mentioned data sampling circuit module 10,40 or 50,
Whether it is wake-up signal that memory management circuitry 202 can correctly identify out from the signal of host system 1000.If storage
It is wake-up signal that device, which manages the judgement of circuit 202 current from the signal of host system 1000, then memory management circuitry 202 can incite somebody to action
Memorizer control circuit unit 1004 or memory storage apparatus 100 are switched to normal mode of operation.
In an exemplary embodiment, the work in memorizer control circuit unit 1004 or memory storage apparatus 100 is reacted
Operation mode, data sampling circuit module 10,40 or 50 can decide whether to open voluntarily or by memorizer control circuit unit 1004
It is dynamic.For example, when to be in suspend mode, standby or low power consumption etc. non-for memorizer control circuit unit 1004 or memory storage apparatus 100
When normal mode of operation, data sampling circuit module 10,40 or 50 can be activated；And when memorizer control circuit unit 1004 or
When memory storage apparatus 100 is in normal mode of operation, data sampling circuit module 10,40 or 50 will not be activated.However,
In another exemplary embodiment, data sampling circuit module 10,40 or 50 is to be activated always.For example, reaction is storing
Device storage device 100 powers on or is switched on, and data sampling circuit module 10,40 or 50 will be activated, and is filled until memory stores
Set 100 be powered down or shut down until.
In conclusion after the differential signal received is converted to input data crossfire, the present invention can be defeated according to this
The sampled signal for entering multiple continuous state switching points of data stream to be sampled to a clock signal, and being obtained according to sampling
To generate the bit data crossfire corresponding to the input data crossfire.Thereby, the clock pulse of clock signal used in the present invention
Frequency can be lowered, and the efficiency handled the differential signal received can be promoted effectively.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (32)
1. a kind of data sampling circuit module, which is characterized in that including：
One differential signal conversion circuit, to receive a differential signal and generate an input data string according to the differential signal
Stream；
One sample circuit is electrically connected the differential signal conversion circuit, and wherein the sample circuit is to according to the input data string
Stream multiple continuous state switching points come sample a clock signal and export a sampled signal；And
One bit data output circuit is electrically connected the sample circuit and to be somebody's turn to do according to the sampled signal to export to correspond to
One bit data crossfire of input data crossfire,
Wherein those continuous state switching points are for codetermining a bit data in the bit data crossfire.
2. data sampling circuit module according to claim 1, which is characterized in that those continuous state switching points belong to same
Clock cycle, those continuous state switching points include one first state switching points, one second state switching points and a third state switching points, first transition
Point and the third state switching points are to belong to one of a rising edge and a failing edge, and second state switching points are belonged on this
It rises along wherein another with the failing edge.
3. data sampling circuit module according to claim 2, which is characterized in that the bit data output circuit includes：
An at least counting circuit, to obtain the relativeness between those continuous state switching points according to the sampled signal；And
One comparison circuit is electrically connected to an at least counting circuit and to according to the opposite pass between those continuous state switching points
It is to determine a bit data.
4. data sampling circuit module according to claim 3, which is characterized in that the bit data output circuit also wraps
It includes：
One output circuit is electrically connected to the differential signal conversion circuit with the comparison circuit and to according to the input data
Crossfire exports the bit data crossfire with the bit data.
5. data sampling circuit module according to claim 3, which is characterized in that an at least counting circuit includes one the
One counting circuit, first counting circuit according to the sampled signal calculating first state switching points and second state switching points
One is poor at the first time,
Wherein the comparison circuit poor with a threshold value and determines the ratio to compare the first time according to a comparison result
Special data.
6. data sampling circuit module according to claim 5, which is characterized in that at least a counting circuit further includes one for this
Second counting circuit,
Wherein second counting circuit is calculating the one of first state switching points and the third state switching points according to the sampled signal
Second time difference.
7. data sampling circuit module according to claim 6, which is characterized in that the comparison circuit compares the first time
It is poor to include with the threshold value and according to the comparison result to determine the operation of the bit data：
Judge the first time poor half for whether being more than second time difference；
If the first time poor half more than second time difference, exports one first bit data；And if this is at the first time
Difference is not more than the half of second time difference, exports one second bit data.
8. data sampling circuit module according to claim 5, which is characterized in that at least a counting circuit further includes one for this
Third counting circuit,
The wherein third counting circuit is calculating the one of second state switching points and the third state switching points according to the sampled signal
The third time difference.
9. data sampling circuit module according to claim 8, which is characterized in that the comparison circuit compares the first time
It is poor to include with the threshold value and according to the comparison result to determine the operation of the bit data：
Judge that the first time is poor whether more than the third time difference；
If this is poor more than the third time difference at the first time, one first bit data is exported；And
If this is poor no more than the third time difference at the first time, one second bit data is exported.
10. data sampling circuit module according to claim 2, which is characterized in that the sample circuit includes：
One first sample circuit, to sample the clock signal according to first state switching points and export one first hits
According to；
One second sample circuit, to sample the clock signal according to second state switching points and export one second hits
According to；And
One third sample circuit, to sample the clock signal according to the third state switching points and export a third hits
According to.
11. data sampling circuit module according to claim 10, which is characterized in that first sample circuit, this second
Sample circuit and the third sample circuit include respectively a D flip-flop.
12. a kind of data sampling method, which is characterized in that including：
It receives a differential signal and an input data crossfire is generated according to the differential signal；
A clock signal is sampled according to multiple continuous state switching points of the input data crossfire and exports a sampled signal；And
The bit data crossfire corresponding to the input data crossfire is exported according to the sampled signal,
Wherein those continuous state switching points are for codetermining a bit data in the bit data crossfire.
13. data sampling method according to claim 12, which is characterized in that when those continuous state switching points belong to same
Arteries and veins period, those continuous state switching points include one first state switching points, one second state switching points and a third state switching points, first state switching points
It is to belong to one of a rising edge and a failing edge, and second state switching points are to belong to the rising with the third state switching points
Along wherein another with the failing edge.
14. data sampling method according to claim 13, which is characterized in that corresponded to export according to the sampled signal
The step of bit data crossfire of the input data crossfire includes：
The relativeness between those continuous state switching points is obtained according to the sampled signal；And
A bit data is determined according to the relativeness between those continuous state switching points.
15. data sampling method according to claim 14, which is characterized in that corresponded to export according to the sampled signal
The step of bit data crossfire of the input data crossfire further includes：
The bit data crossfire is exported according to the input data crossfire and the bit data.
16. data sampling method according to claim 14, which is characterized in that obtain those companies according to the sampled signal
The step of relativeness between continuous state switching points includes：
It is poor come the first time for calculating first state switching points and second state switching points according to the sampled signal,
Wherein include the step of determining the bit data according to the relativeness between those continuous state switching points：
Compare the poor first time and a threshold value and a bit data is determined according to a comparison result.
17. data sampling method according to claim 16, which is characterized in that obtain those companies according to the sampled signal
The step of relativeness between continuous state switching points further includes：
One second time difference of first state switching points and the third state switching points is calculated according to the sampled signal.
18. data sampling method according to claim 17, which is characterized in that it is poor with the threshold value to compare the first time
And include the step of determining the bit data according to the comparison result：
Judge the first time poor half for whether being more than second time difference；
If the first time poor half more than second time difference, exports one first bit data；And if this is at the first time
Difference is not more than the half of second time difference, exports one second bit data.
19. data sampling method according to claim 16, which is characterized in that obtain those companies according to the sampled signal
The step of relativeness between continuous state switching points further includes：
The third time difference of second state switching points and the third state switching points is calculated according to the sampled signal.
20. data sampling method according to claim 19, which is characterized in that it is poor with the threshold value to compare the first time
And include the step of determining the bit data according to the comparison result：
Judge that the first time is poor whether more than the third time difference；
If this is poor more than the third time difference at the first time, one first bit data is exported；And
If this is poor no more than the third time difference at the first time, one second bit data is exported.
21. data sampling method according to claim 13, which is characterized in that according to those companies of the input data crossfire
Continuous state switching points sample the clock signal and the step of exporting the sampled signal includes：
The clock signal is sampled according to first state switching points and exports one first sampled data；
The clock signal is sampled according to second state switching points and exports one second sampled data；And
The clock signal is sampled according to the third state switching points and exports a third sampled data.
22. a kind of memory storage apparatus, which is characterized in that including：
One connecting interface unit, is electrically connected to a host system；
One reproducible nonvolatile memorizer module, including multiple entity erased cells；And
One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould
Block,
Wherein the connecting interface unit includes a data sampling circuit module, and the data sampling circuit module includes：
One differential signal conversion circuit, to receive a differential signal and generate an input data string according to the differential signal
Stream；
One sample circuit is electrically connected the differential signal conversion circuit, and wherein the sample circuit is to according to the input data string
Stream multiple continuous state switching points come sample a clock signal and export a sampled signal；And
One bit data output circuit is electrically connected the sample circuit and to be somebody's turn to do according to the sampled signal to export to correspond to
One bit data crossfire of input data crossfire,
Wherein those continuous state switching points are for codetermining a bit data in the bit data crossfire.
23. memory storage apparatus according to claim 22, which is characterized in that those continuous state switching points belong to same
Clock cycle, those continuous state switching points include one first state switching points, one second state switching points and a third state switching points, first transition
Point and the third state switching points are to belong to one of a rising edge and a failing edge, and second state switching points are belonged on this
It rises along wherein another with the failing edge.
24. memory storage apparatus according to claim 23, which is characterized in that the bit data output circuit includes：
An at least counting circuit, to obtain the relativeness between those continuous state switching points according to the sampled signal；And
One comparison circuit is electrically connected to an at least counting circuit and to according to the opposite pass between those continuous state switching points
It is to determine a bit data.
25. memory storage apparatus according to claim 24, which is characterized in that the bit data output circuit also wraps
It includes：
One output circuit is electrically connected to the differential signal conversion circuit with the comparison circuit and to according to the input data
Crossfire exports the bit data crossfire with the bit data.
26. memory storage apparatus according to claim 24, which is characterized in that an at least counting circuit includes one the
One counting circuit, first counting circuit according to the sampled signal calculating first state switching points and second state switching points
One is poor at the first time,
Wherein the comparison circuit poor with a threshold value and determines the ratio to compare the first time according to a comparison result
Special data.
27. memory storage apparatus according to claim 26, which is characterized in that at least a counting circuit further includes one for this
Second counting circuit,
Wherein second counting circuit is calculating the one of first state switching points and the third state switching points according to the sampled signal
Second time difference.
28. memory storage apparatus according to claim 27, which is characterized in that the comparison circuit compares the first time
It is poor to include with the threshold value and according to the comparison result to determine the operation of the bit data：
Judge the first time poor half for whether being more than second time difference；
If the first time poor half more than second time difference, exports one first bit data；And if this is at the first time
Difference is not more than the half of second time difference, exports one second bit data.
29. memory storage apparatus according to claim 26, which is characterized in that at least a counting circuit further includes one for this
Third counting circuit,
The wherein third counting circuit is calculating the one of second state switching points and the third state switching points according to the sampled signal
The third time difference.
30. memory storage apparatus according to claim 29, which is characterized in that the comparison circuit compares the first time
It is poor to include with the threshold value and according to the comparison result to determine the operation of the bit data：
Judge that the first time is poor whether more than the third time difference；
If this is poor more than the third time difference at the first time, one first bit data is exported；And
If this is poor no more than the third time difference at the first time, one second bit data is exported.
31. memory storage apparatus according to claim 23, which is characterized in that the sample circuit includes：
One first sample circuit, to sample the clock signal according to first state switching points and export one first hits
According to；
One second sample circuit, to sample the clock signal according to second state switching points and export one second hits
According to；And
One third sample circuit, to sample the clock signal according to the third state switching points and export a third hits
According to.
32. memory storage apparatus according to claim 31, which is characterized in that first sample circuit, this second adopts
Sample circuit and the third sample circuit include respectively a D flip-flop.
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| US6472913B2 (en) * | 2001-01-26 | 2002-10-29 | Oki Electric Industry Co., Ltd | Method and apparatus for data sampling |
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| US8464135B2 (en) * | 2010-07-13 | 2013-06-11 | Sandisk Technologies Inc. | Adaptive flash interface |
| US8903030B2 (en) * | 2012-11-07 | 2014-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Clock data recovery circuit with hybrid second order digital filter having distinct phase and frequency correction latencies |
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| TW200847636A (en) * | 2007-05-21 | 2008-12-01 | Faraday Tech Corp | Data fetch circuit and method thereof |
| CN102510328A (en) * | 2011-12-29 | 2012-06-20 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
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