CN102436842B - Memory storage device, memory controller and method for generating log likelihood ratio - Google Patents

Abstract

The invention provides a memory storage device, a memory controller and a method for generating log likelihood ratio. The method comprises the following steps of: acquiring reading data from a memory cell of a flash memory chip of the memory storage device by using at least one piece of bit data, wherein the reading data corresponds to a first storage state; executing an error correction program on the reading data to obtain a corresponding second storage state during writing of the reading data; acquiring storage error amount, corresponding to a storage state which is the second storage state during writing of the reading data and the first storage state during reading of the reading data, from the storage states which accord with error counting amount; and according to the error counting amount, the quantity of the storage states, and the storage error amount, performing logarithmic operation to generate the first log likelihood ratio of the reading data.

Description

The method of memorizer memory devices, Memory Controller and generation log-likelihood ratio

Technical field

The present invention relates to a kind of method of the generation log-likelihood ratio for error-correcting routine, and is particularly related to a kind of memorizer memory devices and Memory Controller of carrying out the method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the storage requirements of consumer's logarithmic code content is also increased rapidly.Because flash memory (Flash Memory) has that data is non-volatile, the little characteristic with machinery-free structure etc. of power saving, volume, applicable user carries the Storage Media as digital archives transmission and exchange.Solid state hard disc (Solid State Drive, SSD) is exactly an example using flash memory as Storage Media, and has been widely used in computer host system as Primary Hard Drive.

Current flash memory is mainly divided into two kinds, is respectively anti-or type flash memory (NOR Flash) and anti-and type flash memory (NAND Flash).Flash memory also can be divided into multistage memory cell (Multi-Level Cell, MLC) flash memory and single-order memory cell (Single-Level Cell, SLC) flash memory according to the storable data bit number of each memory cell.Each memory cell of SLC flash memory only can store 1 bit data, and each memory cell of MLC flash memory can store at least 2 above bit datas.For example, take 4 rank memory cell flash memories as example, each memory cell can store 2 bit datas (, " 11 ", " 10 ", " 00 " and " 01 ").

In flash memory, memory cell can be strung and formed a memory cell (memory cell array) by bit line (Bit Line) and character line (Word Line).In the time that the control circuit of controlling bit line and character line is reading or is writing data and arrives the appointment memory cell of memory cell, the floating voltage of other non-designated memory cells may be interfered (disturb) and then the bit that makes the mistake.That is to say, the data (also referred to as reading data) that control circuit reads from memory cell is different from original write data (also referred to as writing data).Or, when flash memory is because of long-term idle, storer electric leakage or repeatedly erase or when the factor such as write causes abrasion (Wear) situation, the floating voltage in memory cell also may change and the bit that makes the mistake.

In general, memorizer memory devices can carry out error recovery coding and carry out error correcting/decoding (also referred to as error-correcting routine), the bit of righting the wrong thus to reading data writing data by configuration error correcting circuit.Due to the relation (more its issuable wrong bits of bit number that is as storable in each memory cell of multistage memory cell flash memory are also many compared with SLC) of the evolution of processing procedure or the hardware framework of storer itself, sort memory storage device can need mistake in using calibration capability, and preferably error correction techniques is (for example, low density parity check code (Low Density Parity Check Code, LDPC code)) data is carried out to error-correcting routine.Memorizer memory devices stores a question blank and records soft information (SoftInformation) and this soft information and can correspond to the corresponding relation of 0 or 1 probability ratio (being referred to as log-likelihood ratio (LogLikelihood Ratio, LLR)).Therefore in the time using LDPC code to carry out error recovery, first memorizer memory devices obtains soft information from memory cell, and obtains according to question blank the log-likelihood ratio that soft information corresponds to, and then carries out the action of error correction with LDPC code again.After can utilizing training sample to write to read again, the log-likelihood ratio that question blank records adds up to obtain its numerical value.More correct log-likelihood ratio more can reduce iteration (iteration) number of times that carries out error recovery with LDPC code, and then shortens the time of carrying out error correcting/decoding to reading data.But, flash memory in memorizer memory devices can change its error property along with the increase of its storage number (erase-program times), if therefore will obtain best log-likelihood ratio, the error property that must constantly add up flash memory, this measure will cause sizable burden to system.

Summary of the invention

Given this, the invention provides a kind of method that produces log-likelihood ratio (Log Likelihood Ratio, LLR), reduction memorizer memory devices reads the computational burden of the corresponding log-likelihood ratio of data in estimation.

The invention provides a kind of Memory Controller, reduction memorizer memory devices reads the computational burden of the corresponding log-likelihood ratio of data in estimation.

The invention provides a kind of memorizer memory devices, in the time that the corresponding log-likelihood ratio of data is read in estimation, there is less computational burden.

The present invention proposes a kind of method that produces log-likelihood ratio, and for a memorizer memory devices, this memorizer memory devices comprises the flash chip with multiple memory cells.Wherein, each memory cell has multiple storing states, and above-mentioned storing state is to read voltage with at least one bit data to distinguish.The method comprises that use above-mentioned bit data to read voltage obtains one and read data from above-mentioned memory cell, and this reads corresponding the first storing state of data, and the first storing state be above-mentioned storing state one of them.The method also comprises and reads data and writing the second storing state of fashionable correspondence to obtain reading data execution error correction program, wherein the second storing state be above-mentioned storing state one of them.In the read storing state that meets error statistics sum, obtaining writing fashionable is the second storing state and be the storage mistake sum of the first storing state in the time reading.And according to the storing state quantity of error statistics sum, above-mentioned storing state, and store wrong sum execution one logarithm operation, and then produce the first log-likelihood ratio of the data that reads.

From another viewpoint, the present invention proposes a kind of Memory Controller, comprises host computer system interface, storer interface, memory management circuitry, Error-Correcting Circuit and log-likelihood ratio estimation circuit.Wherein host computer system interface is to couple host computer system, and storer interface is in order to couple a flash chip.This flash chip comprises that multiple memory cells and each memory cell have multiple storing states.Above-mentioned storing state is to read voltage with at least one bit data to distinguish.Memory management circuitry, be coupled to host computer system interface and storer interface, memory management circuitry receives the reading command from host computer system, and from above-mentioned memory cell, obtain the data that reads of corresponding reading command via storer interface, corresponding one first storing state of the data that wherein reads, one of them that this first storing state is above-mentioned storing state.Wherein, memory management circuitry comprises a log-likelihood ratio question blank.Error-Correcting Circuit couples memory management circuitry, in order to carry out an error-correcting routine and read data and writing fashionable corresponding the second storing state to obtain reading data, and the second storing state is above-mentioned storing state one of them.Log-likelihood ratio estimation circuit couples memory management circuitry and Error-Correcting Circuit, in order in the read storing state that meets error statistics sum, obtaining writing fashionable is the second storing state and be the storage mistake sum of the first storing state in the time reading, and according to the storing state quantity of error statistics sum, above-mentioned storing state, carry out a logarithm operation with storing wrong sum, and then produce the first log-likelihood ratio of the data that reads.

From another viewpoint, the present invention proposes a kind of memorizer memory devices, comprises connector, flash chip and Memory Controller.Connector is in order to couple host computer system.Flash chip comprises that multiple memory cells and each memory cell have multiple storing states, and above-mentioned storing state is to read voltage with at least one bit data to distinguish.Memory Controller is coupled to flash chip and connector.Memory Controller comprises a log-likelihood ratio question blank.Wherein, Memory Controller control flash chip uses above-mentioned bit data to read voltage and from memory cell, obtains one and read data, corresponding one first storing state of the data that wherein reads, and the first storing state be above-mentioned storing state one of them.Memory Controller reads data and is writing the second storing state of fashionable correspondence to obtain reading data execution error correction program, wherein the second storing state be above-mentioned storing state one of them.Memory Controller is in the read storing state that meets an error statistics sum, obtaining writing fashionable is the second storing state and be the storage mistake sum of the first storing state in the time reading, and according to the storing state quantity of error statistics sum, these storing states, carry out a logarithm operation with the wrong sum of storage, to produce the first log-likelihood ratio of the data of reading.

Based on above-mentioned, the instruction that the present invention assigns in memorizer memory devices Receiving Host system and carry out data while reading, utilize generation to store wrong data and estimate and upgrade this and read the corresponding log-likelihood ratio of data, reduce accordingly the computational burden of estimation log-likelihood ratio.And the log-likelihood specific energy producing reduces the iterations of error-correcting routine, thus the execution efficiency of increase error-correcting routine.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Figure 1A is the schematic diagram of the host computer system of the use memorizer memory devices shown in one exemplary embodiment according to the present invention.

Figure 1B is the schematic diagram of the shown computer of exemplary embodiment, input/output device and memorizer memory devices according to the present invention.

Fig. 1 C is the schematic diagram of the shown host computer system of another exemplary embodiment and memorizer memory devices according to the present invention.

Fig. 2 is the summary calcspar that the memorizer memory devices shown in Figure 1A is shown.

Fig. 3 is the schematic diagram that the storing state shown in one exemplary embodiment and bit data read voltage according to the present invention.

Fig. 4 is the summary calcspar of the Memory Controller shown in one exemplary embodiment according to the present invention.

Fig. 5 be continuity Fig. 3 exemplary embodiment shown in the corresponding relation that may store wrong storing state.

Fig. 6 is the process flow diagram of the method for the generation log-likelihood ratio shown in one exemplary embodiment according to the present invention.

Fig. 7 is the summary calcspar of the Memory Controller shown in another exemplary embodiment according to the present invention.

Fig. 8 is the process flow diagram of the method for the generation log-likelihood ratio shown in another exemplary embodiment according to the present invention.

Reference numeral:

1000: host computer system; 1100: computer;

1102: microprocessor; 1104: random access memory;

1106: input/output device; 1108: system bus;

1110: data transmission interface; 1202: slide-mouse;

1204: keyboard; 1206: display;

1208: printer; 1212: Portable disk;

1214: memory card; 1216: solid state hard disc;

1310: digital camera; 1312: safe digital card;

1314: multimedia memory card; 1316: memory stick;

1318: compact flash; 1320: embedded storage device;

100: memorizer memory devices; 102: connector;

104,104 ': Memory Controller; 106: flash chip;

VA: the first bit data reads voltage; VB: second bit data reads voltage;

VC: the 3rd bit data reads voltage; VD: nibble data reads voltage;

VE: the 5th bit data reads voltage; VF: the 6th bit data reads voltage;

VG: the 7th bit data reads voltage; 1041: host computer system interface;

1043: memory management circuitry; 1045: Error-Correcting Circuit;

1047: storer interface; 2002: memory buffer;

2004: electric power management circuit; 410: log-likelihood ratio question blank;

420: log-likelihood ratio estimation circuit; 430: wave filter;

610～640: each step of the method for the generation log-likelihood ratio described in one embodiment of the invention;

810～860: each step of the method for the generation log-likelihood ratio described in another embodiment of the present invention.

Embodiment

Figure 1A is the schematic diagram of the host computer system of the shown use memorizer memory devices of one exemplary embodiment according to the present invention.

Host computer system 1000 comprises computer 1100 and I/O (Input/Output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (Random Access Memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises slide-mouse 1202, keyboard 1204, display 1206 and printer 1208 as shown in Figure 1B.Figure 1B is the schematic diagram of the shown computer of exemplary embodiment, input/output device and memorizer memory devices according to the present invention.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

In exemplary embodiment of the present invention, memorizer memory devices 100 is to see through data transmission interface 1110 to couple with other elements of host computer system 1000.By the running of microprocessor 1102, random access memory 1104 and input/output device 1106, host computer system 1000 can write to data memorizer memory devices 100, or reads data from memorizer memory devices 100.For example, memorizer memory devices 100 can be memory card 1214, Portable disk 1212 or solid state hard disc (Solid StateDrive, SSD) 1216 as shown in Figure 1B.

Generally speaking, any system of host computer system 1000 for storing data.Although host computer system 1000 is to explain with computer system in this exemplary embodiment, but, in another exemplary embodiment of the present invention, host computer system 1000 can be also the systems such as mobile phone, digital camera, video camera, communication device, reproducing apparatus for phonotape or video signal player.For example, in the time that host computer system is digital camera 1310, memorizer memory devices is its safe digital using (Secure Digital, SD) card 1312, multimedia memory (Multimedia Card, MMC) card 1314, memory stick (Memory Stick, MEM STICK) 1316, compact flash (Compact Flash, CF) card 1318 or embedded storage device 1320 (as shown in Figure 1 C, Fig. 1 C is the schematic diagram of the shown host computer system of another exemplary embodiment and memorizer memory devices according to the present invention).Embedded storage device 1320 comprises embedded multi-media card (EmbeddedMMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly coupled on the substrate of host computer system 1000.

Fig. 2 is the summary calcspar that the memorizer memory devices 100 shown in Figure 1A is shown.Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and flash chip 106.

Connector 102 is coupled to Memory Controller 104, and in order to couple host computer system 1000.In this exemplary embodiment, the transmission interface kind that connector 102 is supported is USB (universal serial bus) (Universal Serial Bus, USB) interface.But in other exemplary embodiment, the transmission interface kind of connector 102 can be also Multi Media Card (Multimedia Card, MMC) interface, advanced annex (the Serial Advanced Technology Attachment of sequence, SATA) interface, parallel advanced annex (Parallel Advanced Technology Attachment, PATA) interface, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 interfaces, high-speed peripheral part connecting interface (Peripheral Component Interconnect Express, PCIExpress) interface, safe digital (Secure Digital, SD) interface, memory stick (Memory Stick, MS) interface, compact flash (Compact Flash, CF) interface, or integration drives electronics (IntegratedDrive Electronics, IDE) any applicable interface such as interface, do not limited at this.

Memory Controller 104 can be carried out multiple logic locks or the steering order with hardware pattern or firmware pattern implementation, and in flash chip 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.In addition, Memory Controller 104 produces and Dynamic Updating Mechanism in order to the log-likelihood ratio (Log Likelihood Ratio, LLR) of carrying out this exemplary embodiment more especially.

Flash chip 106 is coupled to Memory Controller 104.Flash chip 106 is in order to store as FAT (File Allocation Table, or enhanced file system (New TechnologyFile System FAT), the archives economy information such as NTFS), and store as general data such as word, image or voice files.In this exemplary embodiment, flash chip 106 is multistage memory cell (Multi LevelCell, MLC) nand flash memory chip, but the invention is not restricted to this, flash chip 106 can be also single-order memory cell (Single Level Cell, SLC) nand flash memory chip, other flash chips or any memory chip with identical characteristics.

In this exemplary embodiment, flash chip 106 comprises multiple memory cells, and is the data that represents multidigit unit (bits) with multiple floating voltages.Specifically, above-mentioned memory cell can form a memory cell, and has many bit lines and many character lines to connect these memory cells.Wherein, memory cell is to be configured on the point of crossing of bit line and character line with array way.Each memory cell has multiple storing states, and these storing states are to read voltage with at least one bit data to distinguish, and then makes these storing states meet a storing state order.

Fig. 3 is the schematic diagram that the storing state shown in one exemplary embodiment and bit data read voltage according to the present invention.In this exemplary embodiment, flash chip 106 is 8 rank memory cell NAND type flash memories, as shown in Figure 3, floating voltage system in each memory cell reads voltage VA according to the first bit data, second bit data reads voltage VB, the 3rd bit data reads voltage VC, nibble data reads voltage VD, the 5th bit data reads voltage VE, the 6th bit data reads voltage VF and the 7th bit data reads voltage VG and divides into 8 kinds of storing states, respectively " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ".Each storing state comprises least significant bit (LeastSignificant Bit, LSB), middle effectively bit (Center Significant Bit,, and these 3 bits of highest significant position unit (Most Significant Bit, MSB) CSB).For instance, the 1st bit that each storing state is counted from left side in this exemplary embodiment is LSB, and the 2nd bit of counting from left side is CSB, and the 3rd bit of counting from left side is MSB.Accordingly, each memory cell can store 3 bit datas, therefore the memory cell on same character line can form the storage area of 3 pages (, lower page, the middle page and the upper page).That is to say, the LSB of each memory cell is that the CSB of corresponding lower page, each memory cell is the page in correspondence, and the MSB of each memory cell is the corresponding upper page.In addition, several pages can form a physical blocks, and physical blocks is to carry out the least unit of the running of erasing.That is to say the memory cell of being erased in the lump that each physical blocks contains minimal amount.In this exemplary embodiment, the storing state order of these 8 kinds of storing states is sequentially " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 ", " 011 ".Should be noted that, storing state order may be different according to the design of Ge Jia flash chip manufacturer, do not limited at this.

Fig. 4 is the summary calcspar of the Memory Controller shown in one exemplary embodiment according to the present invention.Please refer to Fig. 4, Memory Controller 104 comprises host computer system interface 1041, memory management circuitry 1043, Error-Correcting Circuit 1045, log-likelihood ratio estimation circuit 420, and storer interface 1047.

Host computer system interface 1041 is coupled to memory management circuitry 1043, and sees through connector 102 to couple host computer system 1000.Host computer system interface 1041 is instruction and the data that transmit with identification host computer system 1000 in order to receive.Accordingly, the instruction that host computer system 1000 transmits and data can see through host computer system interface 1041 and be sent to memory management circuitry 1043.In this exemplary embodiment, the corresponding connector 102 of host computer system interface 1041 and be USB interface, and in other exemplary embodiment, host computer system interface 1041 can be also MMC interface, SATA interface, PATA interface, IEEE 1394 interfaces, PCI Express interface, SD interface, MS interface, CF interface, IDE interface or the interface that meets other interface standards.

Memory management circuitry 1043 comprises log-likelihood ratio question blank 410.Memory management circuitry 1043 is the overall operations in order to control store controller 104.Specifically, memory management circuitry 1043 has multiple steering orders, and in the time that memorizer memory devices 100 operates, above-mentioned steering order can be performed that flash chip 106 is carried out as operations such as data read, data writes, data is erased.

In an exemplary embodiment, the steering order of memory management circuitry 1043 is to carry out implementation with firmware pattern.For example, memory management circuitry 1043 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and above-mentioned steering order by burning in ROM (read-only memory).In the time that memorizer memory devices 100 operates, above-mentioned steering order can have been carried out the operation to flash chip 106 by microprocessor unit.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 1043 also can source code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in flash chip 106) of flash chip 106.In addition, memory management circuitry 1043 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Wherein, ROM (read-only memory) has the code of driving section, and in the time that Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in flash chip 106 is loaded in the random access memory of memory management circuitry 1043.Afterwards, microprocessor unit can turn round above-mentioned steering order so that flash chip 106 is operated.In addition,, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 1043 also can a hardware pattern be carried out implementation.

Error-Correcting Circuit 1045 is coupled to memory management circuitry 1043, in order to guarantee the correctness of data.Particularly, when host computer system 1000 sends reading command to Memory Controller 104, and memory management circuitry 1043 is while reading data according to reading command from flash chip 106, Error-Correcting Circuit 1045 can be carried out an error-correcting routine to read data.For instance, Error-Correcting Circuit 1045 is low density parity check (Low Density Parity Check, LDPC) circuit, in the time that memory management circuitry 1043 reads data from flash chip 106, the Error-Correcting Circuit 1045 first log-likelihood ratio question blank 410 in memory management circuitry 1043 is found out log-likelihood ratio corresponding to read data, then according to the data and the recently execution error correction program of this log-likelihood that read, and then obtain and read data and be written into flash chip 106 corresponding storing state at that time.

Log-likelihood ratio estimation circuit 420 couples memory management circuitry 1043 and Error-Correcting Circuit 1045.Log-likelihood ratio estimation circuit 420 is to realize the log-likelihood ratio generation mechanism of this exemplary embodiment.The detailed function mode of this log-likelihood ratio generation mechanism will explain at the following accompanying drawing that coordinates again.In an exemplary embodiment, log-likelihood ratio estimation circuit 420 is for example to become several steering orders with hardware pattern implementation.In other exemplary embodiment, log-likelihood ratio estimation circuit 420 can be also the steering order of firmware pattern implementation one-tenth or the steering order with source code pattern implementation one-tenth.

Storer interface 1047 is coupled to memory management circuitry 1043, with so that Memory Controller 104 is coupled to flash chip 106.Accordingly, Memory Controller 104 can be to flash chip 106 running of being correlated with.That is to say, the data of wanting to write to flash chip 106 can be converted to 106 receptible forms of flash chip via storer interface 1047.

In another exemplary embodiment of the present invention, Memory Controller 104 also comprises memory buffer 2002.Memory buffer 2002 is coupled to memory management circuitry 1043, in order to the temporary data that comes from host computer system 1000, or the temporary data that comes from flash chip 106.

In another exemplary embodiment of the present invention, Memory Controller 104 also comprises electric power management circuit 2004.Electric power management circuit 2004 is coupled to memory management circuitry 1043, in order to the power supply of control store storage device 100.

Because flash chip 106 is under situations such as leaving unused for a long time, leak electricity or be frequently used, the floating voltage of memory cell may change and the bit that makes the mistake.Therefore, the storing state of the data that flash chip 106 records in the time being read, being written into flash chip 106 storing state at that time with this data may be not identical.The storing state of this data in the time reading is different from the situation of writing fashionable storing state and is just referred to as to store mistake.In this exemplary embodiment, in the time that memory management circuitry 1043 is carried out data read operation according to the indication of host computer system 1000, log-likelihood ratio estimation circuit 420 can be in the read several storing states that meet an error statistics sum, obtain wrong sum occurs to store, and then the log-likelihood ratio of data is read in estimation.

In detail, in the time that the memory management circuitry 1043 in memorizer memory devices 100 sees through host computer system interface 1041 and receives the reading command from host computer system 1000, memory management circuitry 1043 is used at least one bit data to read voltage according to reading command indication flash chip 106 and from memory cell, obtains one and read data, and this reads data is one of them storing state (being referred to as below the first storing state) that corresponding memory cell has.

Next, Error-Correcting Circuit 1045 can be carried out an error-correcting routine (for example low density parity check decoding program) to reading data, reads data and is being written into flash chip 106 corresponding storing state (being referred to as below the second storing state) at that time to obtain this.In detail, the log-likelihood ratio question blank 410 in memory management circuitry 1043 records data and this data corresponds to 0 or 1 current log-likelihood ratio.And Error-Correcting Circuit 1045 is in the time of running, can inquire about log-likelihood ratio question blank 410 to obtain the current log-likelihood ratio of the data of reading, then utilize low density parity check decoding program to carry out the action of error recovery, just can obtain thus the second storing state of the data of reading.

Because flash chip 106 has, data is non-volatile and that its channel error rate (channel error rate) is suitable is low, is therefore less than 10 in channel error rate ^-2and the data that writes flash chip 106 has under the prerequisite of randomness, can reasonable assumption store wrong only can occurring between two storing states adjacent in storing state order, and the storing state of the memory cell of flash chip 106 presents and is evenly distributed.

Therefore, log-likelihood ratio estimation circuit 420 is obtaining after first storing state and the second storing state of the data of reading, and first judges that whether the first storing state is adjacent with the second storing state in storing state order.

If the first storing state and the second storing state are also non-conterminous in storing state order, 420 of log-likelihood ratio estimation circuit can be set as a log-likelihood ratio that reads the bit wherein included data that reads positive infinitely great or negative infinitely great.For example, in the time reading bit and be 0, log-likelihood ratio estimation circuit 420 can be set as log-likelihood ratio negative infinitely great, and in the time reading bit and be 1, log-likelihood ratio estimation circuit 420 is understood be set as positive infinity by log-likelihood ratio.It is worth mentioning that, above-mentioned corresponding relation is only the example of enumerating for convenience of description, in other exemplary embodiment, log-likelihood ratio estimation circuit 420 can be also the log-likelihood ratio that reads bit to be set as to positive infinity at 0 o'clock reading bit, and is the log-likelihood ratio that reads bit to be set as negative infinitely great at 1 o'clock reading bit.

If the first storing state and the second storing state are adjacent in storing state order, 420 of log-likelihood ratio estimation circuit can be in the read storing state that meets error statistics sum, and obtaining writing fashionable is the second storing state and be the storage mistake sum of the first storing state in the time reading.For instance, error statistics sum is for example the memory cell quantity on character line, but the present invention is not as limit.In the time that memory management circuitry 1043 reads a character line, whether the storing state when being written into is identical according to the storing state in the time being read of each memory cell on this character line for log-likelihood ratio estimation circuit 420, and then counts the storage mistake sum that storing state is not identical.

Then, the storing state quantity of the storing state that log-likelihood ratio estimation circuit 420 can have according to error statistics sum, each memory cell, and store wrong sum execution one logarithm operation, and then produce the first log-likelihood ratio of the data that reads.

It is below the detailed description of the logarithm operation performed about log-likelihood ratio estimation circuit 420.

According to statistics, the maximum posterior probability take bit as unit (maximum a posterior probability, MAP) decoding algorithm is to read data and judge that its value is as 0 or 1 quite effective mode from flash chip 106.The criterion of maximum posterior probability decoding is as shown in following formula (A):

${\hat{u}}_1=\arg \underset{u_1}{\max }P\left({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="HSA00000295965000042.png"\; state="\{\{state\}\}">u</figure-callout>}}_1\right|y)---\left(A\right)$

Wherein, u ₁for information bit (information bit, also can read fetch bit unit), y are for reading data, and P (u ₁| be y) in data y, to read bit u reading ₁posterior probability (posterior probability).Take 8 rank memory cell NAND type flash memories as example, read bit u ₁value can be 0 or 1.Therefore, formula (A) can be simplified as following formula (B):

${\hat{u}}_1=\left\{\begin{array}{c}1,L\left(u_1\right)\&GreaterEqual;0\\ 0,L\left(u_1\right)<0\end{array}\right.---\left(B\right)$

Wherein, L (u ₁) be logarithm posterior probability ratio (logarithmic a posteriori probability ratio, log-APP ratio), it is defined as follows shown in row formula (C):

$L\left(u_1\right)=\log \left[\frac{P({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="HSA00000295965000042.png"\; state="\{\{state\}\}">u</figure-callout>}}_1=1|y)}{P({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="HSA00000295965000042.png"\; state="\{\{state\}\}">u</figure-callout>}}_1=0|y)}\right]---\left(C\right)$

Logarithm posterior probability ratio also can be referred to as log-likelihood ratio.Base this, suppose that flash chip 106 is 8 rank memory cell NAND type flash memories, each memory cell wherein can store 3 bit datas.In the time that memory management circuitry 1043 is read the data of a character line from flash chip 106, the storing state that reads data y can be " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 ", " 011 " these 8 kinds of storing states one of them.This exemplary embodiment supposes that the LSB of each memory cell is that the CSB of corresponding lower page, each memory cell is the page in correspondence, and the MSB of each memory cell is the corresponding upper page.

As previously mentioned, because flash chip 106 is non-volatility memorizer, and there is quite low channel error rate and (be less than 10 ^-2), therefore formula (C) can be derived following formula (D):

$L\left(u_{\mathrm{low},1}\right|y=\mathrm{RS}2\&RightArrow;\mathrm{RS}1)=(2\&times;u_{\mathrm{low},1}-1)\&times;\log \left[\frac{\mathrm{amount}\_\mathrm{cbit}\_v_{\mathrm{low},1}}{\mathrm{amount}\_\mathrm{ebit}\_v_{\mathrm{low},1}}\right]---\left(D\right)$

Wherein, v _{low, 1}represent to read the bit data from the lower page of flash chip 106.Amount_cbit_v _{low, 1}be illustrated in fixing error statistics sum v _{low, 1}do not occur to store wrong quantity, and amount_ebit_v _{low, 1}be illustrated in error statistics sum v _{low, 1}have wrong quantity occurs to store.RS1 and RS2 be respectively read corresponding lower page in data y read bit u _{low, 1}first storing state of (being LSB) and the second storing state.Similarly, read bit u for what read in data y the page in correspondence _{mid, 1}(being CSB) and the corresponding upper page read bit u _{up, 1}(being MSB), also can derive the formula of similar formula (D), does not repeat them here.

When suitable low of channel error rate, and when the data that writes flash chip 106 has randomness, just can suppose to store and wrong only can occur between the storing state that storing state order is adjacent, and all storing states that in flash chip 106, memory cell has can present and are evenly distributed.Based on above-mentioned hypothesis, if reading the first storing state of data y is " 001 ", the second storing state that reads so data y may be only " 001 ", " 101 ", or " 000 ", and in error statistics sum N, the data quantity with storing state " 001 " is (N/8).Example accordingly, formula (D) can further be derived following formula (E):

$L\left(u_{\mathrm{low},1}\right|y=001)=-1\&times;\log \left[\frac{\frac{8}{N}-a(101\&RightArrow;001)}{a(101\&RightArrow;001)}\right]$

$\&ap;-1\&times;\left[\frac{\frac{8}{N}}{a(101\&RightArrow;001)}\right]$

$=-\left(\log \right[\frac{8}{N}]-\log [a(101\&RightArrow;001)\left]\right)---\left(E\right)$

Wherein, a (101 → 001) is illustrated in error statistics sum N, stores the wrong sum that occurs in LSB.

Due in 8 rank memory cell NAND type flash memories, the storing state that reads data y can be " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 ", or " 011 " these 8 kinds of states one of them, and the memory cell belonging on same character line can form these 3 pages of lower page, the middle page and the upper page.Therefore in this exemplary embodiment, for the storing state of the different data that reads and the different pages, can produce altogether 24 formulas that are similar to formula (E), these 24 formulas can represent by following general formula (1):

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein, N represents that error statistics sum, S represent storing state quantity, and W represents to store wrong sum.In this exemplary embodiment, log-likelihood ratio estimation circuit 420 can be calculated with formula (1) the first log-likelihood ratio LLR_c of the data of reading.

Fig. 5 is the corresponding relation that may store wrong storing state shown in the exemplary embodiment shown in continuity Fig. 3.In Fig. 5, the first storing state of data is read in the right-hand storing state representative that is indicated in " → ", and the storing state that is indicated in the left of " → " is the second storing state that reads data.

Please refer to Fig. 3 and Fig. 5, when the first storing state that reads data is during for " 000 ", the 2nd possible storing state is " 010 ", " 001 ".When the first storing state that reads data is during for " 001 ", the second possible storing state is " 101 ", " 000 ".And when the first storing state that reads data is during for " 010 ", the second possible storing state is " 000 ", " 011 ", by that analogy.

In Fig. 5, be denoted as " * " part, if represent, the data that reads is to should the first storing state in the time being read, and stores the wrong probability that occurs in this bit very little.For example, when the first storing state that reads data is during for " 100 ", wrongly occur in the second storing state that LSB represents the data that reads and should be " 000 " if store.But because this exemplary embodiment has supposed to store wrong only can occurring between the storing state that storing state order is adjacent, and the contrast known storing state of Fig. 3 " 000 " and storing state " 100 " non-conterminous, so in the time that the first storing state that reads data is " 100 ", store suitable low of the wrong probability that occurs in LSB, do not have the second storing state of the data of reading for the situation of " 000 " in this hypothesis, the log-likelihood ratio that namely LSB is 0 is for negative infinitely great.

In an exemplary embodiment, the first storing state of obtaining the data of reading when log-likelihood ratio estimation circuit 420 is that " 001 " and the second storing state are " 000 ", log-likelihood ratio estimation circuit 420 just can mistake of statistics be added up in those stored data of total memory cell, when the data of obtaining is written into, be storing state " 000 " but in the time being read, be that storing state is the storage mistake sum of " 001 ", and calculate the first log-likelihood ratio with above-mentioned formula (1).But, if the first storing state that reads data for " 001 " second storing state be " 100 ", because first, second storing state is also non-conterminous in storing state order, therefore log-likelihood ratio estimation circuit 420 can, according to the value that reads one of data and read bit, be set as the first log-likelihood ratio positive infinitely great or negative infinitely great.The storage mistake that corresponding relation shown in Fig. 5 can be used to calculate the data of reading occurs in the log-likelihood ratio of LSB, CSB or MSB.

Fig. 6 is the process flow diagram of the method for the generation log-likelihood ratio shown in one exemplary embodiment according to the present invention.

Receive after the reading command that host computer system 1000 assigns at memorizer memory devices 100, first as shown in step 610, memory management circuitry 1043 in Memory Controller 104 is indicated flash chip 106 to use bit data to read voltage and from memory cell, is obtained one and read data, and this reads corresponding the first storing state of data.

Then in step 620, the Error-Correcting Circuit 1045 in Memory Controller 104 is carried out an error-correcting routine and is read data and writing flash chip 106 corresponding the second storing state at that time to obtain reading data.

Next as shown in step 630, the log-likelihood ratio estimation circuit 420 in Memory Controller 104 is meeting in the storing state of error statistics sum, and obtaining writing fashionable is the second storing state and be that one of the first storing state stores wrong sum in the time reading.

Finally, in step 640, log-likelihood ratio estimation circuit 420 is according to the storing state quantity of error statistics sum, storing state, and the wrong sum execution of storage one logarithm operation, to produce the first log-likelihood ratio of the data of reading.

In above-mentioned exemplary embodiment, log-likelihood ratio estimation circuit 420 reads in generation after the first log-likelihood ratio of data, can directly utilize the first log-likelihood recently to upgrade the log-likelihood ratio question blank 410 in memory management circuitry 1043.That is to say, utilize the first log-likelihood ratio to replace in log-likelihood ratio question blank 410 and read the corresponding current log-likelihood ratio of data.

But because log-likelihood ratio estimation circuit 420 is to calculate the first log-likelihood ratio in the time reading data each time, the first log-likelihood ratio of therefore producing possibly cannot react the error pattern of all blocks in flash chip 106.The efficiency of proofreading and correct in order further to promote memorizer memory devices 100 execution errors, in following exemplary embodiment, the first log-likelihood ratio being produced by log-likelihood ratio estimation circuit 420 will can directly not be used for upgrading log-likelihood ratio question blank 410, the first log-likelihood ratios must first just can be used for upgrading the content of log-likelihood ratio question blank 410 after a filtering is processed.

Fig. 7 is the summary calcspar of the Memory Controller shown in another exemplary embodiment according to the present invention.Memory Controller 104 ' shown in Fig. 7 is similar in appearance to the Memory Controller 104 shown in Fig. 4, therefore only describe with regard to both difference places below.

In this exemplary embodiment, Memory Controller 104 ' also comprises wave filter 430.Wherein, wave filter 430 is coupled to memory management circuitry 1043 and log-likelihood ratio estimation circuit 420.Wave filter 430 can be finite impulse response (FIR) (Finite Impulse Response, FIR) wave filter or infinite impulse response (Infinite Impulse Response, IIR) wave filter etc., is not limited at this.

Produce and read after the first log-likelihood ratio of data in log-likelihood ratio estimation circuit 420, wave filter 430 will carry out a filtering processing to produce the second log-likelihood ratio to the first log-likelihood ratio, and utilize the second log-likelihood ratio to replace in log-likelihood ratio question blank 410 and read the corresponding current log-likelihood ratio of data.

In an exemplary embodiment, wave filter 430 can be obtained the corresponding current log-likelihood ratio of the data of reading from log-likelihood ratio question blank 410.Then, wave filter 430 carries out filtering processing to produce the second log-likelihood ratio to the first log-likelihood ratio and current log-likelihood ratio, then replaces in log-likelihood ratio question blank 410 and read the corresponding current log-likelihood ratio of data with the second log-likelihood ratio.For instance, wave filter 430 for example can carry out filtering processing to obtain the second log-likelihood ratio LLR_f that will be updated to log-likelihood ratio question blank with following formula (2):

LLR_f＝a×LLR_c+b×LLR_p (2)

Wherein, LLR_p is illustrated in log-likelihood ratio question blank 410 and reads data corresponding current log-likelihood ratio at present, and LLR_c is the first log-likelihood ratio, and a, b are filtering processing coefficients.In this exemplary embodiment, a, b's and be 1.

In another exemplary embodiment, wave filter 430 is iir filter, and is, with following formula (3), the first log-likelihood ratio is carried out to filtering processing, and then produces the second log-likelihood ratio LLR_f:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, m, n are IIR filtering processing coefficients, and LLR_c is the first log-likelihood ratio, and Z ^-1it is the delay disposal time.

The Memory Controller 104 ' of this exemplary embodiment is with wave filter 430, the first log-likelihood ratio to be carried out to the second log-likelihood that filtering processing produced recently to replace log-likelihood ratio old in log-likelihood ratio question blank 410.Thus, even if when under reading data, the error pattern of block and other blocks differ widely, the log-likelihood ratio that is updated to log-likelihood ratio question blank 410 still can reflect the error pattern of all blocks in flash chip 106, thereby reduces the processing time of error correction program.

Fig. 8 is the process flow diagram of the method for the generation log-likelihood ratio shown in another exemplary embodiment according to the present invention.Due to the step 810 of Fig. 8 to 840 with the step 610 of Fig. 6 to 640 same or similar, therefore do not repeat them here.

Produce and read after the first log-likelihood ratio of data in log-likelihood ratio estimation circuit 420, as shown in step 850, by wave filter 430, the first log-likelihood ratio is carried out to filtering processing to produce the second log-likelihood ratio.And as shown in step 860, wave filter 430 can replace in log-likelihood ratio question blank 410 and read the corresponding current log-likelihood ratio of data with the second log-likelihood ratio.

In sum, method, memorizer memory devices and the Memory Controller of generation log-likelihood ratio of the present invention is in the time reading the data in flash chip each time, utilizes the log-likelihood ratio that has the wrong data sum of generation storage to calculate the data of reading.According to statistics, flash chip generation bit stores wrong probability and is less than 1%, therefore only calculates the wrong data quantity of generation storage and can reduce the required system resource of generation log-likelihood ratio.In addition, the present invention further proposes to utilize the log-likelihood estimating recently to dynamically update log-likelihood ratio question blank.After particularly the log-likelihood ratio of generation being processed after filtering, upgrade log-likelihood ratio question blank, the log-likelihood specific energy of being upgraded to guarantee is more precise and stable again, and then the iterations that reduces error correction is to accelerate the processing speed of error correction.

Although the present invention discloses as above with embodiment; but it is not in order to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore working as the scope defining depending on claims, protection scope of the present invention is as the criterion.

Claims (13)

1. one kind produces the method for log-likelihood ratio, for a memorizer memory devices, this memorizer memory devices comprises a flash chip with multiple memory cells, wherein respectively this memory cell has multiple storing states, the plurality of storing state is to read voltage with at least one bit data to distinguish, it is characterized in that, the method comprises:

Use this at least one bit data to read voltage and from those memory cells, obtain one and read data, wherein this reads corresponding one first storing state of data, one of them that this first storing state is the plurality of storing state;

This is read data and carries out an error-correcting routine and read data and writing fashionable corresponding one second storing state to obtain this, wherein this second storing state be the plurality of storing state one of them;

In the read the plurality of storing state that meets an error statistics sum, obtain write fashionable for this second storing state in the time reading, be that one of this first storing state stores wrong sum; And

According to a storing state quantity of this error statistics sum, the plurality of storing state, and this storage mistake sum carries out a logarithm operation, calculates this and read one first log-likelihood ratio of data with formula (1),

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein LLR_c represents this first log-likelihood ratio, and N represents that this error statistics sum, S represent this storing state quantity, and W represents this storage mistake sum.

2. the method for generation log-likelihood ratio according to claim 1, it is characterized in that, the plurality of storing state has a storing state order, and in the read the plurality of storing state that meets an error statistics sum, obtain and also comprise writing a fashionable step that stores wrong sum that is this first storing state for this second storing state in the time reading:

Judge whether this first storing state and this second storing state be adjacent in this storing state order; And

If so, in the read the plurality of storing state that meets this error statistics sum, statistics is this second storing state this storage mistake sum that is this first storing state in the time reading writing fashionable.

3. the method for generation log-likelihood ratio according to claim 2, is characterized in that, judging that this first storing state and this second storing state are in this storing state order whether after adjacent step, the method also comprises:

If not, read the value that reads bit that data comprises and set this first log-likelihood ratio for positive infinitely great or negative infinitely great according to this.

4. the method for generation log-likelihood ratio according to claim 1, it is characterized in that, this memorizer memory devices has a log-likelihood ratio question blank, this log-likelihood ratio question blank records this and reads the corresponding current log-likelihood ratio of data, and according to a storing state quantity of this error statistics sum, the plurality of storing state, and this storage mistake sum execution one logarithm operation, after producing this step of one first log-likelihood ratio that reads data, the method also comprises:

Utilize this first log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

5. the method for generation log-likelihood ratio according to claim 1, it is characterized in that, this memorizer memory devices has a log-likelihood ratio question blank, this log-likelihood ratio question blank records this and reads the corresponding current log-likelihood ratio of data, and according to a storing state quantity of this error statistics sum, the plurality of storing state, and this storage mistake sum execution one logarithm operation, after producing this step of one first log-likelihood ratio that reads data, the method also comprises:

This first log-likelihood ratio is carried out to a filtering processing to produce one second log-likelihood ratio; And

Utilize this second log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

6. the method for generation log-likelihood ratio according to claim 5, is characterized in that, this first log-likelihood ratio is carried out to a filtering processing and comprise with formula (3) and calculating to produce the step of one second log-likelihood ratio:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, LLR_f represents that this second log-likelihood ratio, LLR_c represent this first log-likelihood ratio, and m, n represent respectively a filtering processing coefficient, and Z ^-1represent the delay disposal time.

7. the method for generation log-likelihood ratio according to claim 1, is characterized in that, these error statistics add up to the memory cell quantity on a character line (Word Line).

8. a Memory Controller, is characterized in that, comprising:

One host computer system interface, in order to couple a host computer system;

One storer interface, in order to couple a flash chip, this flash chip comprise multiple memory cells and respectively this memory cell there are multiple storing states, wherein the plurality of storing state is to read voltage with at least one bit data to distinguish;

One memory management circuitry, be coupled to this host computer system interface and this storer interface, this memory management circuitry receives the reading command from this host computer system, and via this storer interface from the plurality of memory cell, obtain to should reading command one read data, wherein this reads corresponding one first storing state of data, and one of them that this first storing state is those storing states, this memory management circuitry comprises a log-likelihood ratio question blank;

One Error-Correcting Circuit, couple this memory management circuitry, in order to this is read data and carries out an error-correcting routine and read data and writing fashionable corresponding one second storing state to obtain this, wherein this second storing state be the plurality of storing state one of them; And

One log-likelihood ratio estimation circuit, couple this memory management circuitry and this Error-Correcting Circuit, in order in the read the plurality of storing state that meets an error statistics sum, obtain write fashionable for this second storing state in the time reading, be that one of this first storing state stores wrong sum, and according to a storing state quantity of this error statistics sum, the plurality of storing state, and this storage mistake sum is carried out a logarithm operation, calculate this and read one first log-likelihood ratio of data with formula (1)

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein LLR_c represents this first log-likelihood ratio, and N represents that this error statistics sum, S represent this storing state quantity, and W represents this storage mistake sum.

9. Memory Controller according to claim 8, is characterized in that, this log-likelihood ratio question blank records this and reads the corresponding current log-likelihood ratio of data, and this Memory Controller also comprises:

One wave filter, couple this memory management circuitry and this log-likelihood ratio estimation circuit, in order to this first log-likelihood ratio is carried out to a filtering processing to produce one second log-likelihood ratio, and utilize this second log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

10. Memory Controller according to claim 9, is characterized in that, this wave filter is, with formula (3), this first log-likelihood ratio is carried out to this filtering processing to produce this second log-likelihood ratio:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, LLR_f represents that this second log-likelihood ratio, LLR_c represent this first log-likelihood ratio, and m, n represent respectively a filtering processing coefficient, and Z ^-1represent the delay disposal time.

11. 1 kinds of memorizer memory devices, is characterized in that, comprising:

A connector, in order to couple a host computer system;

One flash chip, comprise multiple memory cells and respectively this memory cell there are multiple storing states, wherein those storing states are to read voltage with at least one bit data to distinguish; And

One Memory Controller, be coupled to this flash chip and this connector, this Memory Controller comprises a log-likelihood ratio question blank, this this flash chip of Memory Controller control uses this at least one bit data to read voltage and from those memory cells, obtains one and read data, wherein this reads corresponding one first storing state of data, one of them that this first storing state is the plurality of storing state, this is read data and carries out an error-correcting routine and read data and writing fashionable corresponding one second storing state to obtain this, wherein this second storing state be the plurality of storing state one of them, in the read the plurality of storing state that meets an error statistics sum, obtain write fashionable for this second storing state in the time reading, be that one of this first storing state stores wrong sum, according to this error statistics sum, one storing state quantity of the plurality of storing state, and this storage mistake sum is carried out a logarithm operation, calculate this and read one first log-likelihood ratio of data with formula (1),

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein LLR_c represents this first log-likelihood ratio, and N represents that this error statistics sum, S represent this storing state quantity, and W represents this storage mistake sum.

12. memorizer memory devices according to claim 11, it is characterized in that, this log-likelihood ratio question blank records this and reads the corresponding current log-likelihood ratio of data, and this Memory Controller carries out a filtering processing to produce one second log-likelihood ratio to this first log-likelihood ratio, and utilize this second log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

13. memorizer memory devices according to claim 12, is characterized in that, this Memory Controller is, with formula (3), this first log-likelihood ratio is carried out to this filtering processing to produce this second log-likelihood ratio:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, LLR_f represents that this second log-likelihood ratio, LLR_c represent this first log-likelihood ratio, and m, n represent respectively a filtering processing coefficient, and Z ^-1represent the delay disposal time.

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