CN102436842A - Memory storage device, memory controller and method for generating log likelihood ratio - Google Patents

Abstract

The invention provides a memory storage device, a memory controller and a method for generating log likelihood ratio. The method comprises the following steps of: acquiring reading data from a memory cell of a flash memory chip of the memory storage device by using at least one piece of bit data, wherein the reading data corresponds to a first storage state; executing an error correction program on the reading data to obtain a corresponding second storage state during writing of the reading data; acquiring storage error amount, corresponding to a storage state which is the second storage state during writing of the reading data and the first storage state during reading of the reading data, from the storage states which accord with error counting amount; and according to the error counting amount, the quantity of the storage states, and the storage error amount, performing logarithmic operation to generate the first log likelihood ratio of the reading data.

Description

The method of memorizer memory devices, Memory Controller and generation log-likelihood ratio

Technical field

The present invention relates to a kind of method that is used for the generation log-likelihood ratio of error-correcting routine, and is particularly related to a kind of memorizer memory devices and Memory Controller of carrying out this method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, make the storage requirements of consumer's logarithmic code content also increase rapidly.Because flash memory (Flash Memory) has that data is non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., suitable user carries the Storage Media as digital archives transmission and exchange.(Solid State Drive is exactly with the example of flash memory as Storage Media SSD), and has been widely used in the computer host system as Primary Hard Drive solid state hard disc.

Present flash memory mainly is divided into two kinds, is respectively anti-or type flash memory (NOR Flash) and anti-and type flash memory (NAND Flash).Flash memory also can be divided into multistage memory cell (Multi-Level Cell, MLC) flash memory and single-order memory cell (Single-Level Cell, SLC) flash memory according to the storable data bit number of each memory cell.Each memory cell of SLC flash memory only can store 1 bit data, and each memory cell of MLC flash memory can store the bit data more than at least 2.For example, be example with 4 rank memory cell flash memories, each memory cell can store 2 bit datas (that is, " 11 ", " 10 ", " 00 " and " 01 ").

In flash memory, memory cell can be strung and formed a memory cell (memory cell array) by bit line (Bit Line) and character line (Word Line).When the control circuit of control bit line and character line is reading or is writing data and arrives the appointment memory cell of memory cell, the floating voltage of the memory cell of other non-appointments may be interfered (disturb) and then the bit that makes the mistake.That is to say that the data that control circuit is read (being also referred to as the data of reading) is different with original data that writes (being also referred to as the data of writing) from memory cell.Perhaps, when flash memory because of long-term idle, storer electric leakage or repeatedly erase or factor such as write when causing abrasion (Wear) situation, the floating voltage in the memory cell also possibly change and the bit that makes the mistake.

In general, memorizer memory devices can carry out the error recovery coding and carry out error correcting/decoding (being also referred to as error-correcting routine), the bit of righting the wrong thus to reading data writing data by the configuration error correcting circuit.Because the relation (also many) of the evolution of processing procedure or the hardware framework of storer itself than SLC like more its issuable wrong bits of the storable bit number of each memory cell of multistage memory cell flash memory; The sort memory storage device can need (for example to use the preferable error correction techniques of error correction capability; Low density parity check sign indicating number (Low Density Parity Check Code, LDPC code)) comes data is carried out error-correcting routine.Memorizer memory devices stores a question blank and writes down soft information (SoftInformation) and this soft information and can correspond to 0 or 1 probability ratio and (be referred to as the corresponding relation of log-likelihood ratio (LogLikelihood Ratio, LLR)).Therefore when using the LDPC sign indicating number to carry out error recovery, memorizer memory devices at first obtains soft information from memory cell, and obtains the log-likelihood ratio that soft information corresponds to according to question blank, then carries out the action of error correction again with the LDPC sign indicating number.Add up after the log-likelihood ratio that question blank write down training sample capable of using writes and reads and obtain its numerical value.Correct more log-likelihood ratio can reduce iteration (iteration) number of times that carries out error recovery with the LDPC sign indicating number more, and then shortens and carry out the time of error correcting/decoding to reading data.Yet; Flash memory in the memorizer memory devices can change its error property along with the increase of its storage number (erase-program times); Therefore if will obtain best log-likelihood ratio, then must constantly add up the error property of flash memory, this measure will cause sizable burden to system.

Summary of the invention

Given this, the present invention provides a kind of generation log-likelihood ratio (Log Likelihood Ratio, method LLR) reduces memorizer memory devices reads the pairing log-likelihood ratio of data in estimation computational burden.

The present invention provides a kind of Memory Controller, reduces memorizer memory devices reads the pairing log-likelihood ratio of data in estimation computational burden.

The present invention provides a kind of memorizer memory devices, when the pairing log-likelihood ratio of data is read in estimation, has less computational burden.

The present invention proposes a kind of method that produces log-likelihood ratio, is used for a memorizer memory devices, and this memorizer memory devices comprises the flash chip with a plurality of memory cells.Wherein, each memory cell has a plurality of storing states, and above-mentioned storing state is to read voltage with at least one bit data to distinguish.The method comprises that using above-mentioned bit data to read voltage obtains one and read data from above-mentioned memory cell, and this reads corresponding first storing state of data, and first storing state is above-mentioned storing state one of them.The method also comprises is writing second storing state of fashionable correspondence to reading data execution error correction program to obtain reading data, and wherein second storing state is one of them of above-mentioned storing state.In the storing state that meets error statistics sums that is read, obtaining writing fashionable is second storing state and be the storage mistake sum of first storing state when reading.And storing state quantity total according to error statistics, above-mentioned storing state, and store wrong sum execution one logarithm computing, and then first log-likelihood ratio of data is read in generation.

From another viewpoint, the present invention proposes a kind of Memory Controller, comprises host computer system interface, storer interface, memory management circuitry, Error-Correcting Circuit and log-likelihood ratio estimation circuit.Wherein the host computer system interface is in order to coupling host computer system, and the storer interface is in order to couple a flash chip.This flash chip comprises that a plurality of memory cells and each memory cell have a plurality of storing states.Above-mentioned storing state is to read voltage with at least one bit data to distinguish.Memory management circuitry; Be coupled to host computer system interface and storer interface; Memory management circuitry receives the reading command from host computer system; And from above-mentioned memory cell, obtain the data that reads of corresponding reading command via the storer interface, and corresponding one first storing state of the data that wherein reads, this first storing state is one of them of above-mentioned storing state.Wherein, memory management circuitry comprises a logarithm likelihood ratio question blank.Error-Correcting Circuit couples memory management circuitry, and in order to carrying out an error-correcting routine and writing fashionable pairing second storing state to obtain reading data reading data, and second storing state is above-mentioned storing state one of them.The log-likelihood ratio estimation circuit couples memory management circuitry and Error-Correcting Circuit; In order in the storing state that meets the error statistics sum that is read; Obtaining writing fashionable is second storing state and be the storage mistake sum of first storing state when reading; And storing state quantity total according to error statistics, above-mentioned storing state, carry out a logarithm computing with storing wrong sum, and then first log-likelihood ratio of data is read in generation.

From another viewpoint, the present invention proposes a kind of memorizer memory devices, comprises connector, flash chip and Memory Controller.Connector is in order to couple host computer system.Flash chip comprises that a plurality of memory cells and each memory cell have a plurality of storing states, and above-mentioned storing state is to read voltage with at least one bit data to distinguish.Memory Controller is coupled to flash chip and connector.Memory Controller comprises a logarithm likelihood ratio question blank.Wherein, Memory Controller control flash chip uses above-mentioned bit data to read voltage and from memory cell, obtains one and read data, corresponding one first storing state of the data that wherein reads, and first storing state is above-mentioned storing state one of them.Memory Controller is being write second storing state of fashionable correspondence to reading data execution error correction program to obtain reading data, and wherein second storing state is one of them of above-mentioned storing state.Memory Controller is in the storing state that meets error statistics sum that is read; Obtaining writing fashionable is second storing state and be the storage mistake sum of first storing state when reading; And storing state quantity total according to error statistics, these storing states; Carry out a logarithm computing with the wrong sum of storage, read first log-likelihood ratio of data with generation.

Based on above-mentioned; The present invention receives the instruction that host computer system assigns and carries out data when reading at memorizer memory devices; The data of utilizing generation to store mistake is estimated and is upgraded this and read the pairing log-likelihood ratio of data, reduces the computational burden of estimation log-likelihood ratio in view of the above.And the log-likelihood specific energy that is produced reduces the iterations of error-correcting routine, thereby increases the execution efficient of error-correcting routine.

For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.

Description of drawings

Figure 1A is the synoptic diagram of the host computer system of the use memorizer memory devices shown in one exemplary embodiment according to the present invention.

Figure 1B is the synoptic diagram of the shown computer of exemplary embodiment, input/output device and memorizer memory devices according to the present invention.

Fig. 1 C is the synoptic diagram of the shown host computer system of another exemplary embodiment and memorizer memory devices according to the present invention.

Fig. 2 is the summary calcspar that the memorizer memory devices shown in Figure 1A is shown.

Fig. 3 is the synoptic diagram that the storing state shown in one exemplary embodiment and bit data read voltage according to the present invention.

Fig. 4 is the summary calcspar of the Memory Controller shown in one exemplary embodiment according to the present invention.

Fig. 5 is the corresponding relation that possibly store wrong storing state shown in the exemplary embodiment of continuity Fig. 3.

Fig. 6 is the process flow diagram of the method for the generation log-likelihood ratio shown in one exemplary embodiment according to the present invention.

Fig. 7 is the summary calcspar of the Memory Controller shown in another exemplary embodiment according to the present invention.

Fig. 8 is the process flow diagram of the method for the generation log-likelihood ratio shown in another exemplary embodiment according to the present invention.

Reference numeral:

1000: host computer system; 1100: computer;

1102: microprocessor; 1104: RAS;

1106: input/output device; 1108: system bus;

1110: the data transmission interface; 1202: slide-mouse;

1204: keyboard; 1206: display;

1208: printer; 1212: carry-on dish;

1214: memory card; 1216: solid state hard disc;

1310: digital camera; 1312: safe digital card;

1314: the multimedia memory card; 1316: memory stick;

1318: compact flash; 1320: embedded storage device;

100: memorizer memory devices; 102: connector;

104,104 ': Memory Controller; 106: flash chip;

VA: first bit data reads voltage; VB: second bit data reads voltage;

VC: the 3rd bit data reads voltage; VD: the nibble data reads voltage;

VE: the 5th bit data reads voltage; VF: the 6th bit data reads voltage;

VG: the 7th bit data reads voltage; 1041: the host computer system interface;

1043: memory management circuitry; 1045: Error-Correcting Circuit;

1047: the storer interface; 2002: memory buffer;

2004: electric power management circuit; 410: the log-likelihood ratio question blank;

420: the log-likelihood ratio estimation circuit; 430: wave filter;

610～640: each step of the method for the described generation log-likelihood ratio of one embodiment of the invention;

810～860: each step of the method for the described generation log-likelihood ratio of another embodiment of the present invention.

Embodiment

Figure 1A is the synoptic diagram of the host computer system of the shown use memorizer memory devices of one exemplary embodiment according to the present invention.

Host computer system 1000 comprises computer 1100 and I/O (Input/Output, I/O) device 1106.Computer 1100 comprise microprocessor 1102, RAS (Random Access Memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises slide-mouse 1202, keyboard 1204, the display 1206 and printer 1208 shown in Figure 1B.Figure 1B is the synoptic diagram of the shown computer of exemplary embodiment, input/output device and memorizer memory devices according to the present invention.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

In exemplary embodiment of the present invention, memorizer memory devices 100 is that other elements that see through data transmission interface 1110 and host computer system 1000 couple.Through the running of microprocessor 1102, RAS 1104 and input/output device 1106, host computer system 1000 can write to memorizer memory devices 100 with data, or from memorizer memory devices 100, reads data.For example, memorizer memory devices 100 can be the memory card 1214 shown in Figure 1B, carry-on dish 1212 or solid state hard disc (Solid StateDrive, SSD) 1216.

Generally speaking, any system of host computer system 1000 for storing data.Though host computer system 1000 is to explain with computer system in this exemplary embodiment; Yet; In another exemplary embodiment of the present invention, host computer system 1000 also can be systems such as mobile phone, digital camera, video camera, communication device, message player or video signal player.For example; When host computer system is digital camera 1310; Memorizer memory devices then is its employed safe digital (Secure Digital; SD) card 1312, multimedia memory (Multimedia Card, MMC) card 1314, memory stick (Memory Stick, MEM STICK) 1316, compact flash (Compact Flash; CF) card 1318 or embedded storage device 1320 (shown in Fig. 1 C, Fig. 1 C is the synoptic diagram of the shown host computer system of another exemplary embodiment and memorizer memory devices according to the present invention).Embedded storage device 1320 comprise the built-in multimedia card (EmbeddedMMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be coupled on the substrate of host computer system 1000.

Fig. 2 is the summary calcspar that the memorizer memory devices 100 shown in Figure 1A is shown.Please with reference to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and flash chip 106.

Connector 102 is coupled to Memory Controller 104, and in order to couple host computer system 1000.In this exemplary embodiment, the transmission interface kind that connector 102 is supported is USB (Universal Serial Bus, USB) interface.Yet in other exemplary embodiment; The transmission interface kind of connector 102 also can be Multi Media Card (Multimedia Card; MMC) interface, sequence advanced annex (Serial Advanced Technology Attachment, SATA) interface, parallel advanced annex (Parallel Advanced Technology Attachment, PATA) interface, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers; IEEE) 1394 interfaces, high-speed peripheral part connect interface (Peripheral Component Interconnect Express; PCIExpress) interface, safe digital (Secure Digital, SD) interface, memory stick (Memory Stick, MS) interface, compact flash (Compact Flash; CF) interface; Or (IntegratedDrive Electronics, IDE) any suitable interface such as interface does not limit at this integrate to drive electronics.

Memory Controller 104 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and in flash chip 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.In addition, more special log-likelihood ratio (Log Likelihood Ratio, LLR) generation and the Dynamic Updating Mechanism of Memory Controller 104 in order to carry out this exemplary embodiment.

Flash chip 106 is coupled to Memory Controller 104.Flash chip 106 is in order to store like FAT (File Allocation Table; FAT) or (the New TechnologyFile System of enhanced file system; Archives economy information such as NTFS), and store like general data such as literal, image or voice files.In this exemplary embodiment; Flash chip 106 is multistage memory cell (Multi LevelCell; MLC) nand flash memory chip; But the invention is not restricted to this, flash chip 106 also can be single-order memory cell (Single Level Cell, SLC) nand flash memory chip, other flash chips or any memory chip with identical characteristics.

In this exemplary embodiment, flash chip 106 comprises a plurality of memory cells, and is to use a plurality of floating voltages to represent the data of multidigit unit (bits).Specifically, above-mentioned memory cell can be formed a memory cell, and has many bit lines and many character lines to connect these memory cells.Wherein, memory cell is to be configured on the point of crossing of bit line and character line with array way.Each memory cell all has a plurality of storing states, and these storing states are to read voltage with at least one bit data to distinguish, and then makes these storing states meet a storing state order.

Fig. 3 is the synoptic diagram that the storing state shown in one exemplary embodiment and bit data read voltage according to the present invention.In this exemplary embodiment; Flash chip 106 is 8 rank memory cell NAND type flash memories; As shown in Figure 3; Floating voltage in each memory cell system reads voltage VA, second bit data according to first bit data and reads voltage VB, the 3rd bit data and read voltage VC, nibble data and read that voltage VD, the 5th bit data read voltage VE, the 6th bit data reads voltage VF and the 7th bit data reads voltage VG and divides into 8 kinds of storing states, is respectively " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ".Each storing state all comprise least significant bit (LSB) unit (LeastSignificant Bit, LSB), middle effectively bit (Center Significant Bit, CSB), and highest significant position unit (Most Significant Bit, MSB) these 3 bits.For instance, the 1st bit that each storing state is counted from the left side in this exemplary embodiment is LSB, and the 2nd bit of counting from the left side is CSB, and the 3rd bit of counting from the left side is MSB.In view of the above, each memory cell can store 3 bit datas, so the memory cell on same character line can constitute the storage area of 3 pages (that is, lower page, the middle page and go up the page).That is to say that the LSB of each memory cell is that the CSB of corresponding lower page, each memory cell is the page in the correspondence, and the MSB of each memory cell is the corresponding page of going up.In addition, several pages can constitute a physical blocks, and physical blocks is for carrying out the least unit of the running of erasing.That is to say that each physical blocks contains the memory cell of being erased in the lump of minimal amount.In this exemplary embodiment, the storing state order of these 8 kinds of storing states is " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 ", " 011 " in regular turn.Mandatory declaration be that the storing state order may be different according to the design of each tame flash chip manufacturer, do not limit at this.

Fig. 4 is the summary calcspar of the Memory Controller shown in one exemplary embodiment according to the present invention.Please with reference to Fig. 4, Memory Controller 104 comprises host computer system interface 1041, memory management circuitry 1043, Error-Correcting Circuit 1045, log-likelihood ratio estimation circuit 420, and storer interface 1047.

Host computer system interface 1041 is coupled to memory management circuitry 1043, and sees through connector 102 to couple host computer system 1000.Host computer system interface 1041 is instruction and the data that transmitted with identification host computer system 1000 in order to receive.In view of the above, instruction that host computer system 1000 transmitted and data can see through host computer system interface 1041 and be sent to memory management circuitry 1043.In this exemplary embodiment; Host computer system interface 1041 corresponding connectors 102 and be the USB interface; And in other exemplary embodiment, host computer system interface 1041 also can be MMC interface, SATA interface, PATA interface, IEEE 1394 interfaces, PCI Express interface, SD interface, MS interface, CF interface, IDE interface or the interface that meets other interface standards.

Memory management circuitry 1043 comprises log-likelihood ratio question blank 410.Memory management circuitry 1043 is the overall operations in order to control store controller 104.Specifically, memory management circuitry 1043 has a plurality of steering orders, when memorizer memory devices 100 running, above-mentioned steering order can be performed with flash chip 106 is carried out as data read, operation such as data writes, data is erased.

In an exemplary embodiment, the steering order of memory management circuitry 1043 is to come real the work with the firmware pattern.For example, memory management circuitry 1043 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and above-mentioned steering order by burning in ROM (read-only memory).When memorizer memory devices 100 runnings, above-mentioned steering order can be carried out to accomplish the operation to flash chip 106 by microprocessor unit.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 1043 also can the source code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash chip 106) of flash chip 106.In addition, memory management circuitry 1043 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and RAS (not shown).Wherein, ROM (read-only memory) has the sign indicating number of driving section; And when Memory Controller 104 was enabled, microprocessor unit can be carried out this driving yard steering order that section will be stored in the flash chip 106 earlier and be loaded in the RAS of memory management circuitry 1043.Afterwards, microprocessor unit can turn round above-mentioned steering order so that flash chip 106 is operated.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 1043 also can a hardware pattern be come real the work.

Error-Correcting Circuit 1045 is coupled to memory management circuitry 1043, in order to guarantee the correctness of data.Particularly; When host computer system 1000 is sent reading command to Memory Controller 104; And memory management circuitry 1043 according to reading command when flash chip 106 reads data, Error-Correcting Circuit 1045 can be carried out an error-correcting routine to the data that is read.For instance; Error-Correcting Circuit 1045 is low density parity check (Low Density Parity Check; LDPC) circuit; When memory management circuitry 1043 when flash chip 106 reads data; The Error-Correcting Circuit 1045 at first log-likelihood ratio question blank 410 in memory management circuitry 1043 is found out the corresponding log-likelihood ratio of the data that read, then according to the data that is read and this log-likelihood execution error correction program recently, and then obtains to read data and is being written into the pairing at that time storing state of flash chip 106.

Log-likelihood ratio estimation circuit 420 couples memory management circuitry 1043 and Error-Correcting Circuit 1045.Log-likelihood ratio estimation circuit 420 is in order to realize the log-likelihood ratio generation mechanism of this exemplary embodiment.The detailed operation mode of this log-likelihood ratio generation mechanism will remake explanation in following conjunction with figs..In an exemplary embodiment, log-likelihood ratio estimation circuit 420 for example is with real several steering orders that makes of hardware pattern.In other exemplary embodiment, log-likelihood ratio estimation circuit 420 also can be the real steering order that makes of firmware pattern or with the real steering order that makes of source code pattern.

Storer interface 1047 is coupled to memory management circuitry 1043, with so that Memory Controller 104 is coupled to flash chip 106.In view of the above, Memory Controller 104 can be to flash chip 106 running of being correlated with.That is to say that the data of desiring to write to flash chip 106 can convert 106 receptible forms of flash chip into via storer interface 1047.

In another exemplary embodiment of the present invention, Memory Controller 104 also comprises memory buffer 2002.Memory buffer 2002 is coupled to memory management circuitry 1043, in order to the temporary data that comes from host computer system 1000, or the temporary data that comes from flash chip 106.

In another exemplary embodiment of the present invention, Memory Controller 104 also comprises electric power management circuit 2004.Electric power management circuit 2004 is coupled to memory management circuitry 1043, in order to the power supply of control store storage device 100.

Since flash chip 106 be in long-term idle, electric leakage or by situations such as frequent uses under, the floating voltage of memory cell may change and the bit that makes the mistake.Therefore, the storing state of data when being read that flash chip 106 is write down, being written into flash chip 106 storing state at that time with this data maybe be also inequality.The storing state of this data when reading is different from the situation of writing fashionable storing state and just is referred to as to store mistake.In this exemplary embodiment; When memory management circuitry 1043 is carried out the data read operation according to the indication of host computer system 1000; Log-likelihood ratio estimation circuit 420 can be in several storing states that meet error statistics sum that read; Obtain wrong sum takes place to store, and then the log-likelihood ratio of data is read in estimation.

At length say; When the memory management circuitry in the memorizer memory devices 100 1043 sees through host computer system interface 1041 and receives the reading command from host computer system 1000; Memory management circuitry 1043 is used at least one bit data to read voltage according to reading command indication flash chip 106 and from memory cell, is obtained one and read data, and this reads data is one of them storing state of having of corresponding memory cell (below be referred to as first storing state).

Next; Error-Correcting Circuit 1045 can be carried out an error-correcting routine (for example low density parity check decoding program) to reading data, reads data and is being written into the pairing at that time storing state of flash chip 106 (below be referred to as second storing state) to obtain this.Say that at length the log-likelihood ratio question blank 410 in the memory management circuitry 1043 records data and this data and corresponds to 0 or 1 current log-likelihood ratio.And Error-Correcting Circuit 1045 is when running; Can inquire about log-likelihood ratio question blank 410 to obtain the current log-likelihood ratio of the data of reading; Then utilize the low density parity check decoding program to carry out the action of error recovery, just can obtain second storing state of the data of reading thus.

Because it is non-volatile and that its channel error rate (channel error rate) is suitable is low that flash chip 106 has data, therefore in the channel error rate less than 10 ^-2And the data that writes flash chip 106 has under the prerequisite of randomness, can reasonable assumption stores wrong only can occurring between two adjacent in storing state order storing states, and the storing state of the memory cell of flash chip 106 appears and is evenly distributed.

Therefore, log-likelihood ratio estimation circuit 420 judges at first whether first storing state is adjacent with second storing state in the storing state order behind first storing state of obtaining the data of reading and second storing state.

If first storing state and second storing state be in the storing state order and non-conterminous, 420 of log-likelihood ratio estimation circuit can with the data that reads included wherein one read bit log-likelihood ratio be set at positive infinity or negative infinity.For example, when reading bit and be 0, log-likelihood ratio estimation circuit 420 can be set at log-likelihood ratio negative infinitely great, and when reading bit and be 1, log-likelihood ratio estimation circuit 420 is understood be set at positive infinity with log-likelihood ratio.What deserves to be mentioned is; Above-mentioned corresponding relation only is to explain for ease and the example enumerated; In other exemplary embodiment; Log-likelihood ratio estimation circuit 420 can be that the log-likelihood ratio that will read bit at 0 o'clock is set at positive infinity reading bit also, and is that the log-likelihood ratio that will read bit at 1 o'clock is set at negative infinitely great reading bit.

If first storing state is adjacent in the storing state order with second storing state; 420 of log-likelihood ratio estimation circuit can be in the storing state that meets the error statistics sum that is read, and obtaining writing fashionable is second storing state and be the storage mistake sum of first storing state when reading.For instance, the error statistics sum for example is the memory cell quantity on the character line, but the present invention is not as limit.When memory management circuitry 1043 reads a character line; Whether log-likelihood ratio estimation circuit 420 is identical according to the storing state when being read of each memory cell on this character line storing state when being written into, and then counts storing state storage mistake sum inequality.

Then, 420 meetings of log-likelihood ratio estimation circuit are according to the storing state quantity of the storing state that error statistics are total, each memory cell had, and the wrong sum execution of storage one logarithm computing, and then first log-likelihood ratio of data is read in generation.

It below is detailed description about the performed logarithm operation of log-likelihood ratio estimation circuit 420.

According to statistics, be that (maximum a posterior probability, MAP) decoding algorithm is to read data and judge that its value is 0 or 1 suitable effective and efficient manner from flash chip 106 for the maximum posterior probability of unit with the bit.The criterion of maximum posterior probability decoding is shown in following formula (A):

${\hat{u}}_1=\arg \underset{u_1}{\max }P\left({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="HSA00000295965000011.png,HSA00000295965000032.png"\; state="\{\{state\}\}">u</figure-callout>}}_1\right|y)---\left(A\right)$

Wherein, u ₁For information bit (information bit, but also read fetch bit unit), y for reading data, and P (u ₁| then be in reading data y, to read bit u y) ₁Posterior probability (posterior probability).With 8 rank memory cell NAND type flash memories is example, reads bit u ₁Value can be 0 or 1.Therefore, formula (A) can be simplified like following formula (B):

${\hat{u}}_1=\left\{\begin{array}{c}1,L\left(u_1\right)\&GreaterEqual;0\\ 0,L\left(u_1\right)<0\end{array}\right.---\left(B\right)$

Wherein, L (u ₁) be logarithm posterior probability ratio (logarithmic a posteriori probability ratio, log-APP ratio), it defines shown in following formula (C):

$L\left(u_1\right)=\log \left[\frac{P({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="HSA00000295965000011.png,HSA00000295965000032.png"\; state="\{\{state\}\}">u</figure-callout>}}_1=1|y)}{P({\mathrm{<figure-callout\; id="1"\; label="u"\; filenames="HSA00000295965000011.png,HSA00000295965000032.png"\; state="\{\{state\}\}">u</figure-callout>}}_1=0|y)}\right]---\left(C\right)$

Logarithm posterior probability ratio also can be referred to as log-likelihood ratio.The base this, suppose that flash chip 106 is 8 rank memory cell NAND type flash memories, each memory cell wherein can store 3 bit datas.When memory management circuitry 1043 when flash chip 106 is read the data of a character line, the storing state that reads data y can be " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 ", " 011 " these 8 kinds of storing states one of them.The LSB of each memory cell of this exemplary embodiment hypothesis is that the CSB of corresponding lower page, each memory cell is the page in the correspondence, and the MSB of each memory cell is the corresponding page of going up.

As previously mentioned, because flash chip 106 is a non-volatility memorizer, and has quite low channel error rate (less than 10 ^-2), so formula (C) can be derived following formula (D):

$L\left(u_{\mathrm{low},1}\right|y=\mathrm{RS}2\&RightArrow;\mathrm{RS}1)=(2\&times;u_{\mathrm{low},1}-1)\&times;\log \left[\frac{\mathrm{amount}\_\mathrm{cbit}\_v_{\mathrm{low},1}}{\mathrm{amount}\_\mathrm{ebit}\_v_{\mathrm{low},1}}\right]---\left(D\right)$

Wherein, v _{Low, 1}The bit data from the lower page of flash chip 106 is read in expression.Amount_cbit_v _{Low, 1}Be illustrated in the fixing error statistics sum v _{Low, 1}Do not take place to store wrong quantity, and amount_ebit_v _{Low, 1}Be illustrated in the error statistics sum v _{Low, 1}Have wrong quantity takes place to store.RS1 and RS2 be respectively read corresponding lower page among the data y read bit u _{Low, 1}First storing state of (being LSB) and second storing state.Likewise, read bit u to what read among the data y page in the correspondence _{Mid, 1}(being CSB) and corresponding go up the page read bit u _{Up, 1}(being MSB) also can be derived the formula of similar formula (D), repeats no more at this.

When suitable low of channel error rate; And when the data that writes flash chip 106 has randomness; Just can suppose to store wrong only can occurring between the adjacent storing state of storing state order, and all storing states that memory cell has in the flash chip 106 can present and are evenly distributed.Based on above-mentioned hypothesis; If reading first storing state of data y is " 001 ", second storing state that reads data y so only possibly be " 001 ", " 101 ", or " 000 "; And in error statistics sum N, the data quantity with storing state " 001 " is (N/8).Example in view of the above, formula (D) can further be derived following formula (E):

$L\left(u_{\mathrm{low},1}\right|y=001)=-1\&times;\log \left[\frac{\frac{8}{N}-a(101\&RightArrow;001)}{a(101\&RightArrow;001)}\right]$

$\&ap;-1\&times;\left[\frac{\frac{8}{N}}{a(101\&RightArrow;001)}\right]$

$=-\left(\log \right[\frac{8}{N}]-\log [a(101\&RightArrow;001)\left]\right)---\left(E\right)$

Wherein, a (101 → 001) is illustrated among the error statistics sum N, stores the wrong sum that occurs in LSB.

Because in 8 rank memory cell NAND type flash memories; The storing state that reads data y can be " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 "; Or " 011 " these 8 kinds of states one of them, can constitute lower page, the middle page and go up these 3 pages of the page and belong to same the memory cell on the character line.Therefore in this exemplary embodiment, the storing state and the different pages to the different data that reads can produce 24 formulas that are similar to formula (E) altogether, and these 24 formulas can be represented by following general formula (1):

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein, N representes that error statistics sum, S represent storing state quantity, and W representes to store wrong sum.In this exemplary embodiment, log-likelihood ratio estimation circuit 420 can be calculated the first log-likelihood ratio LLR_c of the data of reading with formula (1).

Fig. 5 is the corresponding relation that possibly store wrong storing state shown in the continuity exemplary embodiment shown in Figure 3.In Fig. 5, first storing state of data is read in the right-hand storing state representative that is indicated in " → ", and the storing state that is indicated in the left of " → " is second storing state that reads data.

Please consult Fig. 3 and Fig. 5 simultaneously, when first storing state that reads data was " 000 ", the 2nd possible storing state was " 010 ", " 001 ".When first storing state that reads data was " 001 ", the second possible storing state was " 101 ", " 000 ".And when first storing state that reads data was " 010 ", the second possible storing state was " 000 ", " 011 ", by that analogy.

In Fig. 5, be denoted as " * " part, expression is if the data that reads is to should first storing state when being read, and it is very little then to store the wrong probability that occurs in this bit.For example, when first storing state that reads data when " 100 ", wrongly occur in second storing state that LSB then representes the data that reads and should be " 000 " if store.But because this exemplary embodiment has supposed to store wrong only can occurring between the adjacent storing state of storing state order; And map 3 can be known storing state " 000 " and storing state " 100 " and non-conterminous; So when first storing state that reads data is " 100 "; Store suitable low of the wrong probability that occurs in LSB, do not have the situation of second storing state of the data of reading for " 000 " in this hypothesis, just LSB is that 0 log-likelihood ratio is for negative infinitely great.

In an exemplary embodiment; First storing state of obtaining the data of reading when log-likelihood ratio estimation circuit 420 is that " 001 " and second storing state are " 000 "; Log-likelihood ratio estimation circuit 420 just can mistake of statistics in stored those data of the memory cell of statistics sum; Be storing state " 000 " when the data of obtaining is written into but be that storing state is the storage mistake sum of " 001 " when being read, and calculate first log-likelihood ratio with above-mentioned formula (1).Yet; Be " 100 " if read first storing state of data for " 001 " second storing state; Because first, second storing state is also non-conterminous in the storing state order; Therefore log-likelihood ratio estimation circuit 420 can be set at positive infinity or negative infinitely great with first log-likelihood ratio according to reading the value that one of data reads bit.The storage mistake that corresponding relation shown in Figure 5 can be used to calculate the data of reading occurs in the log-likelihood ratio of LSB, CSB or MSB.

Fig. 6 is the process flow diagram of the method for the generation log-likelihood ratio shown in one exemplary embodiment according to the present invention.

After memorizer memory devices 100 receives the reading command that host computer system 1000 assigns; At first shown in step 610; Memory management circuitry 1043 indication flash chips 106 in the Memory Controller 104 use bit datas to read voltage and from memory cell, obtain one and read data, and this reads corresponding first storing state of data.

Then in step 620,1045 pairs of the Error-Correcting Circuits in the Memory Controller 104 read data and carry out an error-correcting routine and writing pairing at that time second storing state of flash chip 106 to obtain reading data.

Next shown in step 630, the log-likelihood ratio estimation circuit 420 in the Memory Controller 104 is in the storing state that meets the error statistics sum, and obtaining writing fashionable is second storing state and be that one of first storing state stores wrong sum when reading.

In step 640, log-likelihood ratio estimation circuit 420 is according to the storing state quantity of error statistics sum, storing state, and the wrong sum execution of storage one logarithm computing at last, reads first log-likelihood ratio of data with generation.

In above-mentioned exemplary embodiment, after log-likelihood ratio estimation circuit 420 reads first log-likelihood ratio of data in generation, can directly utilize first log-likelihood log-likelihood ratio question blank 410 in the updated stored management circuit 1043 recently.That is to say, utilize first log-likelihood ratio to replace in the log-likelihood ratio question blank 410 and read the pairing current log-likelihood ratio of data.

Yet because log-likelihood ratio estimation circuit 420 is when reading data each time, to calculate first log-likelihood ratio, first log-likelihood ratio that is therefore produced possibly can't react the error pattern of all blocks in the flash chip 106.In order further to promote the efficient that memorizer memory devices 100 execution errors are proofreaied and correct; In following exemplary embodiment; First log-likelihood ratio that is produced by log-likelihood ratio estimation circuit 420 will can directly not be used for upgrading log-likelihood ratio question blank 410, the first log-likelihood ratios must be earlier through just being used for upgrading the content of log-likelihood ratio question blank 410 after the Filtering Processing.

Fig. 7 is the summary calcspar of the Memory Controller shown in another exemplary embodiment according to the present invention.Memory Controller 104 ' shown in Figure 7 is similar in appearance to Memory Controller shown in Figure 4 104, thus below only just both difference places describe.

In this exemplary embodiment, Memory Controller 104 ' also comprises wave filter 430.Wherein, wave filter 430 is coupled to memory management circuitry 1043 and log-likelihood ratio estimation circuit 420.Wave filter 430 can be that (Finite Impulse Response, FIR) (Infinite Impulse Response, IIR) wave filter or the like does not limit at this for wave filter or IIR in finite impulse response (FIR).

After first log-likelihood ratio of data is read in 420 generations of log-likelihood ratio estimation circuit; Wave filter 430 will carry out a Filtering Processing producing second log-likelihood ratio to first log-likelihood ratio, and utilize second log-likelihood ratio to replace in the log-likelihood ratio question blank 410 and read the pairing current log-likelihood ratio of data.

In an exemplary embodiment, wave filter 430 can be obtained the pairing current log-likelihood ratio of the data of reading from log-likelihood ratio question blank 410.Then, 430 pairs first log-likelihood ratios of wave filter and current log-likelihood ratio carry out Filtering Processing to produce second log-likelihood ratio, replace in the log-likelihood ratio question blank 410 with second log-likelihood ratio and read the pairing current log-likelihood ratio of data.For instance, wave filter 430 for example can carry out Filtering Processing to obtain the second log-likelihood ratio LLR_f that will be updated to the log-likelihood ratio question blank with following formula (2):

LLR_f＝a×LLR_c+b×LLR_p (2)

Wherein, LLR_p is illustrated in the data that reads in the log-likelihood ratio question blank 410 pairing current log-likelihood ratio at present, and LLR_c then is first log-likelihood ratio, and a, b then are the Filtering Processing coefficients.In this exemplary embodiment, a, b's and be 1.

In another exemplary embodiment, wave filter 430 is an iir filter, and is with following formula (3) first log-likelihood ratio to be carried out Filtering Processing, and then produces the second log-likelihood ratio LLR_f:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, m, n then are IIR Filtering Processing coefficients, and LLR_c is first log-likelihood ratio, and Z ^-1Then be to postpone the processing time.

The Memory Controller 104 ' of this exemplary embodiment is to carry out second log-likelihood that Filtering Processing was produced with 430 pairs first log-likelihood ratios of wave filter recently to replace log-likelihood ratio old in the log-likelihood ratio question blank 410.Thus; Even if when the error pattern of block and other blocks differ widely under reading data; The log-likelihood ratio that is updated to log-likelihood ratio question blank 410 still can reflect the error pattern of all blocks in the flash chip 106, thereby reduces the processing time of error correction program.

Fig. 8 is the process flow diagram of the method for the generation log-likelihood ratio shown in another exemplary embodiment according to the present invention.Since the step 810 of Fig. 8 to 840 with the step 610 of Fig. 6 to 640 same or similar, so repeat no more at this.

After first log-likelihood ratio of data is read in 420 generations of log-likelihood ratio estimation circuit, shown in step 850, carry out Filtering Processing to produce second log-likelihood ratio by 430 pairs first log-likelihood ratios of wave filter.And shown in step 860, wave filter 430 can be to read the pairing current log-likelihood ratio of data in second log-likelihood ratio replacement log-likelihood ratio question blank 410.

In sum; The method of generation log-likelihood ratio of the present invention, memorizer memory devices and Memory Controller are when the data that reads each time in the flash chip, utilize to have the log-likelihood ratio that wrong data sum calculates the data of reading takes place to store.According to statistics, the probability of flash chip generation bit storage mistake is less than 1%, and therefore a wrong data quantity of calculating generation storage can reduce the required system resource of generation log-likelihood ratio.In addition, the present invention further proposes to utilize the log-likelihood that estimates recently to dynamically update the log-likelihood ratio question blank.Particularly the log-likelihood ratio that produces is upgraded the log-likelihood ratio question blank again through after the Filtering Processing, the log-likelihood specific energy of being upgraded to guarantee is more precise and stable, and then reduces the processing speed of the iterations of error correction with the quickening error correction.

Though the present invention discloses as above with embodiment; But it is not in order to limit the present invention; Those skilled in the art under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that accompanying claims defines.

Claims (16)

1. method that produces log-likelihood ratio; Be used for a memorizer memory devices; This memorizer memory devices comprises the flash chip with a plurality of memory cells, and wherein respectively this memory cell has a plurality of storing states, and these a plurality of storing states are to read voltage with at least one bit data to distinguish; It is characterized in that this method comprises:

Use this at least one bit data to read voltage and from those memory cells, obtain one and read data, wherein this reads corresponding one first storing state of data, and this first storing state is one of them of these a plurality of storing states;

This is read data carries out an error-correcting routine and read data and writing fashionable pairing one second storing state to obtain this, wherein this second storing state be these a plurality of storing states one of them;

In these a plurality of storing states that meet error statistics sum that read, obtain and writing fashionable this second storing state wrong sum of a storage for this first storing state when reading that is; And

According to a storing state quantity of this error statistics sum, these a plurality of storing states, and should store the wrong total logarithm computing of carrying out, to produce one first log-likelihood ratio that this reads data.

2. the method for generation log-likelihood ratio according to claim 1; It is characterized in that; These a plurality of storing states have a storing state order; And in this a plurality of storing states that meet error statistics sums that read, obtain writing and fashionablely when reading, also comprise for one of this first storing state stores wrong total step for this second storing state:

Judge whether this first storing state and this second storing state be adjacent in this storing state order; And

If then in these a plurality of storing states that meet this error statistics sum that read, statistics is being write fashionable this second storing state this storage mistake sum for this first storing state when reading that is.

3. whether adjacent the method for generation log-likelihood ratio according to claim 2 is characterized in that, judging this first storing state and this second storing state in this storing state order after the step, and this method also comprises:

If not, then according to this read that data comprises one read bit value set this first log-likelihood ratio for positive infinitely great or negative infinitely great.

4. the method for generation log-likelihood ratio according to claim 1; It is characterized in that; Storing state quantity according to this error statistics sum, these a plurality of storing states; And should store wrong sum and carry out a logarithm computing, comprise with formula (1) and calculating to produce this step that reads one first log-likelihood ratio of data:

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein LLR_c representes this first log-likelihood ratio, and N representes that this error statistics sum, S represent this storing state quantity, and W representes the wrong sum of this storage.

5. the method for generation log-likelihood ratio according to claim 1; It is characterized in that this memorizer memory devices has a logarithm likelihood ratio question blank, this reads data pairing one current log-likelihood ratio this log-likelihood ratio question blank record; And in the storing state quantity according to this error statistics sum, these a plurality of storing states; And should store wrong sum execution one logarithm computing, after the step that produces this one first log-likelihood ratio that reads data, this method also comprises:

Utilize this first log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

6. the method for generation log-likelihood ratio according to claim 1; It is characterized in that this memorizer memory devices has a logarithm likelihood ratio question blank, this reads data pairing one current log-likelihood ratio this log-likelihood ratio question blank record; And in the storing state quantity according to this error statistics sum, these a plurality of storing states; And should store wrong sum execution one logarithm computing, after the step that produces this one first log-likelihood ratio that reads data, this method also comprises:

This first log-likelihood ratio is carried out a Filtering Processing to produce one second log-likelihood ratio; And

Utilize this second log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

7. the method for generation log-likelihood ratio according to claim 6 is characterized in that, this first log-likelihood ratio is carried out a Filtering Processing comprise with formula (3) with the step that produces one second log-likelihood ratio and calculating:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, LLR_f representes that this second log-likelihood ratio, LLR_c represent this first log-likelihood ratio, and m, n represent a Filtering Processing coefficient respectively, and Z ^-1Expression one postpones the processing time.

8. the method for generation log-likelihood ratio according to claim 1 is characterized in that, these error statistics add up to the memory cell quantity on the character line (Word Line).

9. a Memory Controller is characterized in that, comprising:

One host computer system interface is in order to couple a host computer system;

One storer interface, in order to coupling a flash chip, this flash chip comprise a plurality of memory cells and respectively this memory cell have a plurality of storing states, wherein these a plurality of storing states are to read voltage with at least one bit data to distinguish;

One memory management circuitry; Be coupled to this host computer system interface and this storer interface; This memory management circuitry receives the reading command from this host computer system, and via this storer interface from these a plurality of memory cells, obtain to should reading command one read data, wherein this reads corresponding one first storing state of data; And this first storing state is those storing states one of them, and this memory management circuitry comprises a logarithm likelihood ratio question blank;

One Error-Correcting Circuit; Couple this memory management circuitry; Carry out an error-correcting routine and read data and writing fashionable pairing one second storing state in order to this is read data to obtain this, wherein this second storing state be these a plurality of storing states one of them; And

One logarithm likelihood ratio estimation circuit; Couple this memory management circuitry and this Error-Correcting Circuit; In order in these a plurality of storing states that meet error statistics sum that read; Obtain and writing fashionable this second storing state wrong sum of a storage for this first storing state when reading that is; And a storing state quantity total according to these error statistics, these a plurality of storing states, and should store wrong sum execution one logarithm computing, to produce one first log-likelihood ratio that this reads data.

10. Memory Controller according to claim 9 is characterized in that, this log-likelihood ratio estimation circuit is to calculate this first log-likelihood ratio that this reads data with formula (1):

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein LLR_c representes this first log-likelihood ratio, and N representes that this error statistics sum, S represent this storing state quantity, and W representes the wrong sum of this storage.

11. Memory Controller according to claim 9 is characterized in that, this reads data pairing one current log-likelihood ratio this log-likelihood ratio question blank record, and this Memory Controller also comprises:

One wave filter; Couple this memory management circuitry and this log-likelihood ratio estimation circuit; In order to this first log-likelihood ratio being carried out a Filtering Processing producing one second log-likelihood ratio, and utilize this second log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

12. Memory Controller according to claim 11 is characterized in that, this wave filter is with formula (3) this first log-likelihood ratio to be carried out this Filtering Processing to produce this second log-likelihood ratio:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, LLR_f representes that this second log-likelihood ratio, LLR_c represent this first log-likelihood ratio, and m, n represent a Filtering Processing coefficient respectively, and Z ^-1Expression one postpones the processing time.

13. a memorizer memory devices is characterized in that, comprising:

A connector is in order to couple a host computer system;

One flash chip, comprise a plurality of memory cells and respectively this memory cell have a plurality of storing states, wherein those storing states are to read voltage with at least one bit data to distinguish; And

One Memory Controller; Be coupled to this flash chip and this connector; This Memory Controller comprises a logarithm likelihood ratio question blank, and this flash chip of this Memory Controller control uses this at least one bit data to read voltage and from those memory cells, obtains one and read data, and wherein this reads data correspondence one first storing state; This first storing state is one of them of these a plurality of storing states; This is read data carries out an error-correcting routine and read data and writing fashionable pairing one second storing state to obtain this, wherein this second storing state be these a plurality of storing states one of them, in these a plurality of storing states that meet error statistics sum that read; Obtain and writing fashionable this second storing state wrong sum of a storage for this first storing state when reading that is; According to a storing state quantity of this error statistics sum, these a plurality of storing states, and should store the wrong total logarithm computing of carrying out, to produce one first log-likelihood ratio that this reads data.

14. memorizer memory devices according to claim 13 is characterized in that, this Memory Controller is to calculate this first log-likelihood ratio that this reads data with formula (1):

$\mathrm{LLR}\_c=-\left(\log \right[\frac{S}{N}]-\log [W\left]\right)---\left(1\right)$

Wherein LLR_c representes this first log-likelihood ratio, and N representes that this error statistics sum, S represent this storing state quantity, and W representes the wrong sum of this storage.

15. memorizer memory devices according to claim 13; It is characterized in that; This reads data pairing one current log-likelihood ratio this log-likelihood ratio question blank record; And this Memory Controller carries out a Filtering Processing producing one second log-likelihood ratio to this first log-likelihood ratio, and utilizes this second log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.

16. memorizer memory devices according to claim 15 is characterized in that, this Memory Controller is with formula (3) this first log-likelihood ratio to be carried out this Filtering Processing to produce this second log-likelihood ratio:

$\mathrm{LLR}\_f=\frac{n\&times;\mathrm{LLR}\_c}{1-m\&times;Z^{-1}}---\left(3\right)$

Wherein, LLR_f representes that this second log-likelihood ratio, LLR_c represent this first log-likelihood ratio, and m, n represent a Filtering Processing coefficient respectively, and Z ^-1Expression one postpones the processing time.

Images