CN111813591B - Data error correction method and device of Nand Flash, electronic equipment and storage medium - Google Patents
Data error correction method and device of Nand Flash, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The invention discloses a data error correction method of Nand Flash, which comprises the following steps: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; performing error correction coding on the data to be written by using a target error correction coding scheme to obtain correct coded data; storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area. By implementing the scheme, the accuracy of evaluating the error rate can be improved, different target error correction coding schemes are selected according to the error rate to carry out error correction coding, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Description
Technical Field
The invention relates to the technical field of Nand Flash data, in particular to a data error correction method and device of Nand Flash, electronic equipment and a storage medium.
Background
Nand Flash (Flash) chips of 3D (Three-dimensional) vertical design have gradually achieved a vertical stack of structural designs on a silicon chip, and Nand Flash has developed Multi-bit memory technology, such that chip memory technology has gradually evolved from Single-bit SLC (Single Level Cel) and two-bit MLC (Multi-Level Cell), three-bit, four-bit, and so on. However, when the Nand Flash chip is used, the abrasion of the tunnel oxide of the chip increases with the increase of the programming/erasing times, so that the loss of charges increases, and the bit error rate becomes high.
In order to solve the above problems, when the related technology performs error correction on the data of Nand Flash, the related technology mainly performs ECC code design based on the worst case, for example, performs ECC design based on the case that 1K byte contains 70 bits of errors, and the technology can reduce the error rate of the data of Nand Flash; however, in the initial use stage of Nand Flash, since the number of edits is small, the bit error rate is also low, that is, the use of different stages, the data retention time is different, and the bit error rate is also different, if the ECC code design is performed based on the worst case, the operation time and the storage space are wasted, so that the error correction efficiency of the Nand Flash processor is low.
Therefore, it is necessary to propose a new data error correction technique for Nand Flash.
Disclosure of Invention
The application provides a data error correction method and device for Nand Flash, electronic equipment and a storage medium, which can solve the technical problem of low error correction efficiency of a Nand Flash processor.
The first aspect of the invention provides a data error correction method of Nand Flash, which comprises the following steps:
when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate;
selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
performing error correction coding on the data to be written by using the target error correction coding scheme to obtain correct coded data;
storing the encoded data into a Nand Flash data area, and storing the target error correction encoding scheme into the Nand Flash redundant area.
Optionally, before the step of inputting the preset data retention time and the obtained editing times of the Nand Flash redundant area into the preset Nand Flash error rate model, the method includes:
receiving test data of a Nand Flash chip, wherein the test data comprises: a plurality of different mapping indexes and the error rates corresponding to the mapping indexes, wherein the mapping indexes comprise the editing times and the data retention time;
Modeling according to a preset polynomial fitting rule by using the mapping index and the corresponding error rate respectively to obtain the Nand Flash error rate model.
Optionally, inputting the preset data retention time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model, and obtaining the estimated error rate includes:
accessing the Nand Flash redundant area of the Nand Flash chip;
extracting the editing times in the Nand Flash redundant area;
and inputting the preset data retention time and the preset editing times into the Nand Flash error rate model to obtain the estimated error rate.
Optionally, the step of selecting the target error correction coding scheme in the preset error correction coding scheme list according to the estimated error rate includes:
calculating the number of error bits in the data according to the estimated error rate, wherein the error rate is the ratio of the number of error bits to the data to be written;
and comparing the error bit number with a preset error bit number threshold value, and selecting the target error correction coding scheme in the error correction coding scheme list according to a comparison result.
Optionally, the target error correction coding scheme includes: the step of comparing the error bit number with a preset error bit number threshold value according to the single-stage error correction coding scheme and the cascade error correction coding scheme, and selecting the target error correction coding scheme in the error correction coding scheme list according to the comparison result comprises the following steps:
Comparing the error bit number with a preset error bit number threshold;
if the comparison result is that the error bit number is smaller than or equal to the error bit number threshold value, selecting the single-stage error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme;
and if the comparison result is that the error bit number is larger than the error bit number threshold value, selecting the cascade error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme.
Optionally, the step of storing the encoded data in the Nand Flash data area and storing the target error correction coding scheme in the Nand Flash redundant area includes:
when a reading instruction is received, acquiring a target error correction coding scheme in the Nand Flash redundant area, and acquiring data to be decoded in the Nand Flash data area, wherein the data to be decoded is the coded data;
determining a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and decoding and correcting the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
The second aspect of the present invention provides a data error correction device for Nand Flash, the device comprising:
the evaluation module is used for inputting the preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model when a programming instruction is received, so as to obtain an evaluated error rate;
the selecting module is used for selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
the error correction module is used for carrying out error correction coding on the data to be written by utilizing the target error correction coding scheme to obtain correct coded data;
and the storage module is used for storing the encoded data into a Nand Flash data area and storing the target error correction encoding scheme into the Nand Flash redundant area.
Optionally, the apparatus further includes:
the acquisition module is used for acquiring a target error correction coding scheme in the Nand Flash redundant area and acquiring data to be decoded in the Nand Flash data area when a reading instruction is received, wherein the data to be decoded is the coded data;
a determining module, configured to determine a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
And the decoding module is used for decoding and correcting the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
A third aspect of the present invention provides an electronic apparatus, comprising: the system comprises a memory, a processor and a communication bus, wherein the communication bus is respectively in communication connection with the memory and the processor, a computer program is stored in the memory, and when the processor executes the computer program, the steps in the data error correction method of Nand Flash according to the first aspect are realized.
A fourth aspect of the present invention provides a storage medium, where the storage medium is a computer readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements each step in the data error correction method of Nand Flash according to the first aspect.
The data error correction method of Nand Flash provided by the invention comprises the following steps: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; performing error correction coding on the data to be written by using a target error correction coding scheme to obtain correct coded data; storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area. By implementing the scheme, the error rate is estimated through the editing times of Nand Flash and the data retention time, the accuracy of estimating the error rate is improved, different target error correction coding schemes are selected according to the error rate, error correction coding is carried out on data to be written by using the target error correction coding schemes, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other drawings may be obtained from them without inventive effort for a person skilled in the art.
FIG. 1a is a schematic diagram of a Nand Flash structure provided by an embodiment of the present invention;
FIG. 1b is a schematic diagram of a Nand Flash memory array structure according to an embodiment of the present invention
FIG. 2 is a schematic diagram of a Nand Flash error rate model provided by an embodiment of the invention;
FIG. 3 is a flow chart of steps of a data error correction method of Nand Flash provided by an embodiment of the invention;
FIG. 4 is a flowchart of a further step of the data error correction method of Nand Flash provided by the embodiment of the invention;
FIG. 5 is a flowchart of the refinement steps of the data error correction method of Nand Flash provided in FIG. 4;
FIG. 6 is a block diagram of a data error correction device of Nand Flash according to an embodiment of the present invention;
fig. 7 is a schematic diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention will be clearly described in conjunction with the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical problem of low error correction efficiency of the Nand Flash processor in the prior art is solved.
In order to solve the technical problems, the invention provides a data error correction method and device of Nand Flash, electronic equipment and a storage medium.
Referring to fig. 1a and fig. 1b, fig. 1a is a schematic structural diagram of a Nand Flash of the present invention, in which the schematic structural diagram is a LUN (Logical Unit Nunber) block diagram, a LUN represents a Nand Flash (Flash) chip, and in the schematic structural diagram of the Nand Flash, a Nand Flash chip includes two parts of a storage array structure 101 and a cache structure 102. In one aspect, the storage array structure 101 has two planes 1011 (parts or levels, etc.), each Plane1011 containing 2048 blocks (physical blocks or storage physical blocks), each LUN containing 4096 blocks, each block having 128 pages inside, each page containing 8.448K bytes.
Further, referring to fig. 1b, fig. 1b is a schematic diagram of a Nand Flash storage array structure provided in an embodiment of the present invention, where each page includes: the data area and the redundant area, wherein the data area comprises 8K bytes which can be stored, the redundant area comprises or stores 0.448K bytes, the data area is collectively called as a Nand Flash data area 10111, the redundant area is collectively called as a Nand Flash redundant area 10112, and each Plane comprises: a Nand Flash data area 10111 and a Nand Flash redundant area 10112.
It will be appreciated that Nand Flash data area 10111 is used to store written data, while Nand Flash redundant area 10112 is used to store: address mapping information, chip editing times, ECC check codes, bad block management and other information; on the other hand, the cache structure 102 includes: the Cache Register1021 (Cache memory) and the Data Register1022 (Data Register) can be understood that the storage array structure is logically divided into two planes 1011, each Plane1011 is divided into 2048 blocks, each block is divided into 128 pages, each page contains 8.448K bytes, and the Cache structure 102 is correspondingly divided into the same array, so as to realize the Data in the storage array structure and the address mapping in the Cache structure, so as to improve the speed of Data processing, such as Data reading, storing or testing, but not limited thereto, and other Nand Flash Data processing modes also belong to the scope of the present embodiment.
Two factors that lead to reliability degradation of Nand Flash are: the number of edits (number of programming/erasing) of data in Nand Flash and Nand Flash employ a multi-bit storage technique. On one hand, editing Nand Flash memory array data can cause degradation of a tunneling oxide layer, specifically, editing operation mainly depends on charge transmission through a thin oxide layer and tunneling in and out of the memory layer through Fowler Nordheim (FN), and after tunneling, traps are charged to an oxide and interface state to physically abrade tunnel oxide of a silicon nitride film; may cause charge to be trapped in the tunnel oxide or excess charge to flow into/out of the memory layer, thereby lowering the threshold voltage of the memory cell and reducing reliability. On the other hand, after the multi-bit storage technology is adopted, the change field of the gate threshold voltage is divided into a plurality of small areas, so that the fault tolerance between the areas is too small, and the threshold voltages between adjacent areas are easily influenced by each other, so that error bits are generated; the original error rate of Nand Flash storage is directly reduced by 10-3 orders of magnitude from SLC to TLC, which reduces reliability, so in order to ensure the read-out correctness of Nand Flash storage data, ECC (Error Correcting Code, error correction code) is usually introduced into Nand Flash processor, and the error rate is reduced.
The design of the ECC error correction scheme of the embodiment of the invention is determined based on the error rate, so that the error rate of data in the Nand Flash storage array needs to be analyzed. Since different programming/erasing times and data retention time affect the bit error rate of Nand Flash data, in order to accurately evaluate the bit error rate, the following operations need to be performed:
1. first, chip testing is required to test the effect of different editing times and data retention time on bit error rate. Generally, the number of edits to the 3D Nand Flash is about 3000, the test scheme is set according to the number of edits, and the test process is as follows: 1. programming and writing a 0x55 vector into an odd page of the Nand Flash chip, programming and writing a 0xAA vector into an even page, reading out data after programming, and then storing the data as an independent file; 2. performing 100 programming/erasing cycles on Nand Flash; 3. the aging of the chip is accelerated by adopting a high-temperature environment to shorten the test time, nand Flash is placed in a high-temperature box at 125 ℃, 1 data reading operation is carried out every 5 minutes, the reading result is compared with an independent file, and the number of error bits is recorded; 4. stopping the test when the test time reaches 100 hours (equivalent of 10 years at 55 ℃); 5. step 3 and step 4 are repeated by adding 100 programming/erasing cycles to Nand Flash each time; 6. when the number of Nand Flash programming/erasing cycles reaches 3000, ending the test; 7. the obtained test data (the editing times, the data holding time and the error rate) are built into a table or recorded into the table, and the drawing and recording of the table are not repeated in the embodiment, so long as common influence factors of the editing times and the data holding time serving as the error rate are embodied, and the change of the error rate under the influence of the common factors is embodied. Through testing the chip in the stage, the error rate change condition under the common influence of the editing times and the data retention time can be analyzed, and the accuracy of evaluating the error rate is improved.
2. And carrying out modeling fitting on the error rate distribution condition of Nand Flash according to the test data, and specifically carrying out modeling in a polynomial fitting mode to obtain a Nand Flash error rate model. After modeling, the processor can estimate the error rate when writing or programming data according to the current editing times and the data holding time of Nand Flash.
3. Referring to fig. 2, a schematic diagram of a Nand Flash error rate model provided by an embodiment of the present invention is shown; the number of editing times and the data retention time of the Nand Flash are acquired, the acquired number of editing times and the data retention time of the Nand Flash storage array are input into the Nand Flash error rate model 201, the corresponding estimated error rate can be obtained, and the efficiency and accuracy of acquiring the error rate can be improved by means of the Nand Flash error rate model 201 of the embodiment.
Referring to fig. 3, which is a step flowchart of a data error correction method of Nand Flash provided by the embodiment of the present invention, the embodiment of the present invention provides a data error correction method of Nand Flash, which is implemented by using a Nand Flash storage array shown in fig. 1 as an example, evaluating an error rate of the Nand Flash storage array shown in fig. 1, and selecting an error correction coding scheme based on the error rate, specifically, when a processor corresponding to the Nand Flash executes a program, the method of data error correction of Nand Flash of the embodiment is implemented, and includes the following steps:
Step S301: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate.
Specifically, the programming instruction may be a programming start instruction input by a person, or a programming start instruction triggered by a person, where the programming instruction is received by a processor, and the processor is a processor of a computer, or may be a control unit or a data processing unit that is specially applied to data editing of Nand Flash.
The Nand Flash error rate model comprises different mapping indexes and the mapping relation of the error rate, wherein the mapping indexes comprise editing times and data retention time. It can be understood that the Nand Flash error rate model uses the editing times and the data holding time as mapping indexes, and the corresponding error rate can be obtained through the mapping indexes. It should be noted that, the bit error rate obtained by using the mapping index through the Nand Flash bit error rate model is the Nand Flash or the current bit error rate of the chip, if the current Nand Flash chip is programmed or data is written, the Nand Flash chip after programming or writing will have the number of error bits corresponding to the current estimated bit error rate. Therefore, before programming or writing data into the Nand Flash chip, the current error rate of the Nand Flash or chip needs to be evaluated, and through this step S301, the accuracy of obtaining the error rate of the Nand Flash chip can be improved.
Step S302: and selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate.
Specifically, the preset error correction coding scheme list includes a plurality of error correction coding schemes, wherein the error correction coding schemes include ECC (Error Correcting Code, error correction code) codes and coding modes, and the ECC error correction codes and the coding modes adopted by the plurality of error correction coding schemes are different. Preferably, the present embodiment includes two error correction coding schemes, such as: the single-stage error correction coding scheme and the cascade error correction coding scheme are different in ECC error correction code and coding mode, for example, the single-stage error correction coding scheme adopts a single-stage coding mode, and the adopted error correction code is a BCH code; the cascade error correction coding scheme adopts a cascade encoding mode, and the adopted error correction code is a combination of an RS code and a BCH code, and in addition, the cascade error correction coding scheme can also adopt other error correction codes such as a combination of the RS code and the LDPC code; it should be noted that, after encoding and correcting the data to be written, the encoded data is stored in the Nand Flash data area, and the encoded error correction coding scheme is stored in the Nand Flash redundancy area, because the lengths of the error correction codes of different error correction coding schemes are different, if a longer ECC error correction code is adopted, the processor needs to spend more operation time, and can compress the storage of other information (such as the information data of the editing times, etc.), therefore, the error correction coding scheme which is suitable for error correction and has a shorter error correction code needs to be selected according to the estimated error rate, so as to realize the saving of the storage space of the Nand Flash redundancy area after encoding. Further, selecting a target error correction coding scheme in a preset error correction coding scheme list according to error rates with different complexity, wherein the target error correction coding scheme is an error correction coding scheme corresponding to the error rate before a single error. By implementing the scheme of the step, the corresponding error correction coding scheme can be selected according to different error rates, so that the operation time can be reduced, and the storage space can be saved.
Step S303: and performing error correction coding on the data to be written by using the target error correction coding scheme to obtain correct coded data.
Specifically, after the error correction coding scheme is selected, the error correction coding scheme is utilized to perform error correction coding on the data to be written, and the accurate coded data after error correction coding can be obtained. For example, when the error rate is lower, the error correction coding scheme is a single-stage error correction coding scheme, the single-stage error correction coding scheme is a simpler error correction coding scheme, and has the characteristic of short operation time, the error correction code is a BCH code, that is, the code length of the error correction code of the single-stage error correction coding scheme is shorter, the single-stage error correction coding scheme is applied to the life period of Nand Flash with lower error rate, and it is required to be noted that the life period of Nand Flash is related to the editing times and the data retention time of Nand Flash, and because the error rate of the data in the initial use stage of the Nand Flash chip is lower, the error correction coding can be completed by adopting the single-stage error correction coding scheme; when the error rate is higher than a specific value, a cascade error correction coding scheme is selected, the error correction code can be selected as a combination of an RS code and a BCH code, the cascade error correction coding scheme has the advantage of strong error correction capability, the operation of the cascade error correction coding scheme is complex, more operation time is required, and the cascade error correction coding scheme is suitable for error correction coding of data to be written under the condition of larger error rate. Therefore, no matter how many error bits are corresponding to the bit error rate in the data, a complete ECC algorithm needs to be run to complete the verification (error correction coding). By implementing the scheme, the data to be written can be encoded according to the selected target error correction encoding scheme, the accuracy of the data can be improved, the situation that the data to be written have errors after encoding is prevented, and the reliability is high.
Step S304: storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area.
Specifically, after error correction coding is performed on data to be written, the obtained coded data and a target error correction coding scheme are stored in a Nand Flash storage array structure, wherein the Nand Flash storage array structure comprises: the Nand Flash data area and the Nand Flash redundant area. Storing the coded data into a Nand Flash data area and storing a target error correction coding scheme into a Nand Flash redundant area so as to realize the storage of the data and the target error correction coding scheme and provide a decoding basis for decoding the data to be decoded and the decoding error correction scheme for error correction decoding; it should be noted that, when the encoded data is stored in the Nand Flash data area, and the target error correction encoding scheme is stored in the Nand Flash redundant area, it indicates that one time of editing (data erasing and programming after erasing) is completed on the Nand Flash, then the number of edits of the Nand Flash redundant area is increased by 1, so that each time of editing (erasing and programming after erasing) of the Nand Flash, the number of edits of the Nand Flash redundant area will be updated. By implementing the technology of the step, the storage of the coded data and the target error correction coding scheme can be realized, and the reliability of Nand Flash is improved.
The embodiment provides a data error correction method of Nand Flash, which comprises the following steps: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and the mapping relation of the error rate, and the mapping indexes comprise the editing times and the data retention time; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; performing error correction coding on the data to be written by using a target error correction coding scheme to obtain correct coded data; storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area. By implementing the scheme, the error rate is estimated through the editing times of Nand Flash and the data retention time, the accuracy of estimating the error rate is improved, different target error correction coding schemes are selected according to the error rate, error correction coding is carried out on data to be written by using the target error correction coding schemes, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Referring to fig. 4, a flowchart of a further step of the data error correction method of Nand Flash provided by the embodiment of the present invention is shown, where the data error correction method of Nand Flash provided by another embodiment of the present invention includes:
s401: receiving test data of a Nand Flash chip, wherein the test data comprises: and the error rates corresponding to the mapping indexes are obtained by the plurality of mapping indexes.
In step S401, test data after testing the Nand Flash chip is received, where the test data specifically includes: the system comprises a Nand Flash chip, a plurality of editing times, a plurality of data holding times, a plurality of bit error rates corresponding to a plurality of mapping indexes combined by the plurality of editing times and the plurality of data holding times, wherein the plurality of data are obtained by testing the Nand Flash chip, namely, the data after the Nand Flash chip is erased and programmed after the Nand Flash chip is erased, the programmed data are read to calculate the bit error rate, continuous erasing/programming operation is carried out to test the bit error rate of the Nand Flash chip under different editing times (the times of programming after the Nand Flash chip is erased) and different data holding times, and the bit error rate distribution condition of the Nand Flash chip series under the factors of the editing times and the data holding times can be analyzed through the test data.
S402: and modeling according to a preset polynomial fitting rule by using the mapping index and the corresponding error rate respectively to obtain a Nand Flash error rate model.
Specifically, modeling and fitting are carried out on the error rate distribution condition of Nand Flash according to the test data, and modeling is carried out according to a preset polynomial fitting rule by using the mapping index and the corresponding error rate, so as to obtain a Nand Flash error rate model. The scheme of the step can improve the efficiency and accuracy of evaluating the error rate.
S403: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and the mapping relation of the error rate, and the mapping indexes comprise the editing times and the data retention time.
S404: and selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate.
S405: and performing error correction coding on the data to be written by using the target error correction coding scheme to obtain correct coded data.
S406: storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area.
In the embodiment of the present invention, steps S403 to S406 are technical features that are the same as or similar to steps S301 to S304 in the data error correction method of Nand Flash provided in the previous embodiment, and the detailed description of steps S403 to S406 refers to the description of steps S301 to S304, which is not limited further in this embodiment.
Optionally, step S403 includes:
and accessing the Nand Flash redundant area. Specifically, the Nand Flash comprises a Nand Flash data area and a Nand Flash redundant area, wherein the Nand Flash data area is used for storing written coded data, and the coded data can be understood as data to be stored; the Nand Flash redundant area is used for storing: the data such as the target error correction coding scheme and the editing times need to be obtained, and the Nand Flash redundant area needs to be accessed first in order to evaluate the current error rate of the Nand Flash.
Further, the editing times in the Nand Flash redundant area are extracted. And after the Nand Flash redundant area is accessed, extracting the editing times in the Nand Flash redundant area. It can be understood that the number of edits is the number of edits after the last writing of data to Nand Flash, i.e., the number of edits after the last programming.
Further, inputting the preset data retention time and the preset editing times into a Nand Flash error rate model to obtain an estimated error rate.
Specifically, the data retention time is the total storage time in Nand Flash after the data to be written is estimated to be programmed before the editing, for example, when the Nand Flash is used for the first time, the data is written into the Nand Flash until the data is deleted or erased, the time period is the corresponding data retention time each time, and the data retention time can be used for determining the required retention time of the data after each programming or the frequency of the data updating/reprogramming after the programming. After the editing times in the Nand Flash redundant area are obtained, the editing times and the preset data retention time are input into a pre-established Nand Flash error rate model, and the Nand Flash error rate model is calculated or mapped according to the editing times and the data retention time to obtain the error rate of corresponding evaluation, so that the accuracy of obtaining the Nand Flash or chip error rate is improved.
Referring to fig. 5, fig. 5 is a flowchart illustrating a refinement step of a data error correction method of Nand Flash provided in fig. 4, where the method includes:
s401: receiving test data of a Nand Flash chip, wherein the test data comprises: and the error rates corresponding to the mapping indexes are obtained by the plurality of mapping indexes.
S402: and modeling according to a preset polynomial fitting rule by using the mapping index and the corresponding error rate respectively to obtain a Nand Flash error rate model.
S403: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and the mapping relation of the error rate, and the mapping indexes comprise the editing times and the data retention time.
Further, step S404 includes:
s4041: calculating the number of error bits in the data to be written according to the estimated error rate, wherein the error rate is the ratio of the number of error bits to the data to be written;
s4042: and comparing the error bit number with a preset error bit number threshold value, and selecting a target error correction coding scheme in an error correction coding scheme list according to a comparison result.
In step S404, after the estimated bit error rate is obtained, calculating or predicting the number of error bits of the data to be written by using the estimated bit error rate, where the data to be written is data programmed and stored in the Nand Flash data area, for example, the Nand Flash data area may store 8 kbytes, and the bit error rate may be the bit error rate corresponding to every 1 kbyte; the bit error rate is used to evaluate or budget the number of erroneous bits occurring in the data to be written, and the number of erroneous bits in the unit transfer data can be calculated from the bit error rate. Further, the number of error bits is compared with a preset threshold value of the number of error bits, the threshold value of the number of error bits is a preset threshold value, the threshold value of the number of error bits is used for judging whether the number of error bits in the data to be written contains serious errors or not, a comparison result can be obtained through comparison, and then a target error correction coding scheme in an error correction coding scheme list is selected according to the comparison result, so that the corresponding error correction coding scheme is selected according to different error rates, the operation time can be reduced, and the storage space is saved.
S405: and carrying out error correction coding on the data to be written by using the target error correction coding scheme to obtain correct coded data.
S406: storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area.
Further, the target error correction coding scheme includes: the step S4042 specifically includes:
comparing the number of error bits with a preset threshold value of the number of error bits;
if the comparison result is that the error bit number is smaller than or equal to the error bit number threshold value, selecting a single-stage error correction coding scheme in the error correction coding scheme list as a target error correction coding scheme;
and if the comparison result is that the error bit number is larger than the error bit number threshold value, selecting a cascade error correction coding scheme in the error correction coding scheme list as a target error correction coding scheme.
Specifically, the target error correction coding scheme includes: single-level error correction coding schemes and concatenated error correction coding schemes. Comparing the number of error bits with a preset threshold value of the number of error bits, if the preset threshold value of the number of error bits is set to be 30, and when the number of error bits is 31, 40, 70 and other values, the number of error bits is larger than the threshold value of the number of error bits 30, and if the number of error bits is determined to be serious errors, the unit transmission data is a more complex number of error bits, and a cascade error correction coding scheme (the error correction coding scheme comprising the combination of the BCH code and the RS code) in the error correction coding scheme list is selected as a target error correction coding scheme. If the number of error bits is 10, 20, 29, 30 or the like, which is less than or equal to the value of 30, which is less than or equal to the error bit number threshold value of 30, it is determined that the number of error bits is a slightly erroneous data, the unit transmission data appears as a simpler number of error bits, and a single-level error correction coding scheme (the above-described error correction coding scheme including the BCH code) in the error correction coding scheme list is selected as the target error correction coding scheme.
Further, after step S304 or step S406, the method includes:
when a reading instruction is received, acquiring a target error correction coding scheme in a Nand Flash redundant area, and acquiring data to be decoded in a Nand Flash data area, wherein the data to be decoded is coded data;
determining a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and decoding and correcting the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
Specifically, the data error correction method of Nand Flash in the above embodiment of the present invention further includes: the decoding and error correction are carried out on the data written into the Nand Flash storage array, the decoding process can be a data reading process, the decoding can be carried out to accurately read the encoded data in the Nand Flash storage array, and the decoding process is not a process of deleting/erasing the data in the Nand Flash data area, in particular to a process of analyzing and interpreting the data in the data reading process. When receiving a reading instruction, extracting a target error correction coding scheme in a Nand Flash redundant area, wherein the target error correction coding scheme is an error correction coding scheme when data is written into the Nand Flash last time, and it is required to say that the Nand Flash storage array comprises a plurality of data, the target error correction coding scheme extracted into the Nand Flash redundant area is an error correction coding scheme corresponding to the data required to be decoded, wherein the data required to be decoded is the data to be decoded, and the data to be decoded is written into a Nand Flash data area in the Nand Flash before the current decoding operation. Further, determining a target error correction decoding scheme corresponding to the data to be decoded according to the extracted target error correction coding scheme, specifically, analyzing the extracted target error correction coding scheme to obtain a coding mode and an error correction code of the target error correction coding scheme, for example, when the target error correction coding scheme is a single-stage error correction coding scheme, the coding mode is a single-stage error correction coding mode, the error correction code is a BCH code, and determining the single-stage error correction decoding scheme as the target error correction decoding scheme according to the coding mode and the error correction code; when the target error correction coding scheme is a cascade error correction coding scheme, the coding mode is a cascade error correction coding mode, the error correction code is a combined code of a BCH code and an RS code, and the cascade error correction decoding scheme is determined to be the target error correction decoding scheme according to the coding mode and the error correction code. In addition, the decoding and error correction are carried out on the data to be decoded according to the target error correction decoding scheme, so that correct decoding data are obtained, and the decoding data obtained through decoding and error correction are accurate readable data, can be read by a user, and have reliability.
It should be noted that, the data reading operation does not belong to editing (erasing/programming) of Nand Flash, after the decoding process is completed, the data stored in the Nand Flash data area can be read, and the editing frequency of the Nand Flash redundant area is not increased.
Referring to fig. 6, fig. 6 is a data error correction device of Nand Flash, which corresponds to the data error correction method of Nand Flash, according to an embodiment of the present invention, and the device 600 includes:
the evaluation module 601 is configured to input a preset data retention time and an obtained edit frequency of the Nand Flash redundant area into a preset Nand Flash error rate model when a programming instruction is received, so as to obtain an evaluated error rate, where the Nand Flash error rate model includes mapping relations between different mapping indexes and error rates, and the mapping indexes include the edit frequency and the data retention time;
a selecting module 602, configured to select a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
the encoding module 603 is configured to perform error correction encoding on the data to be written by using a target error correction encoding scheme, so as to obtain correct encoded data;
the storage module 604 is configured to store the encoded data in the Nand Flash data area, and store the target error correction encoding scheme in the Nand Flash redundancy area.
The invention provides a data error correction device of Nand Flash, comprising: the device comprises an evaluation module 601, a selection module 602, an encoding module 603 and a storage module 604. When a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model through an evaluation module 601 to obtain an evaluated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and the mapping relation of the error rate, and the mapping indexes comprise the editing times and the data retention time; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate through a selecting module 602; performing error correction coding on the data to be written by using a target error correction coding scheme through a coding module 603 to obtain correct coded data; the encoded data is stored to the Nand Flash data area by the storage module 604, and the target error correction encoding scheme is stored to the Nand Flash redundancy area. By implementing the scheme, the error rate is estimated through the estimation module 601 according to the editing times and the data retention time of Nand Flash, the accuracy of estimating the error rate is improved, different target error correction coding schemes are selected through the selection module 602 according to the error rate, error correction coding is carried out on data to be written by using the target error correction coding schemes, the occupation of resources and the power consumption are reduced, and the error correction coding efficiency of a Nand Flash processor under different error rates is improved.
Further, the apparatus 600 further includes: the obtaining module 605, the determining module 606, and the decoding module 607 are specifically as follows:
and the obtaining module 605 is configured to obtain, when receiving the read instruction, the target error correction coding scheme in the Nand Flash redundant area, and obtain data to be decoded in the Nand Flash data area, where the data to be decoded is encoded data.
A determining module 606 is configured to determine a target error correction decoding scheme for the data to be decoded according to the target error correction encoding scheme.
The decoding module 607 is configured to perform decoding error correction on the data to be decoded according to the target error correction decoding scheme, so as to obtain correct decoded data.
The data error correction device of the programming instruction Nand Flash provided by the invention further comprises: the acquisition module 605, the determination module 606 and the decoding module 607 are used for decoding and editing the data written into the Nand Flash storage array, the decoding process can be a data reading process, and the decoding process can be used for accurately reading the encoded data in the Nand Flash storage array. Specifically, when receiving the read instruction, the acquiring module 605 acquires the target error correction coding scheme in the Nand Flash redundant area, where the target error correction coding scheme is the error correction coding scheme when the data is written into the Nand Flash last time, or is another target error correction coding scheme before the current decoding and editing, it should be noted that the Nand Flash storage array includes a plurality of data, the target error correction coding scheme extracted from the Nand Flash redundant area is the error correction coding scheme corresponding to the data to be decoded, where the data to be decoded is the data to be decoded, and the data to be decoded is written into the Nand Flash data area in the Nand Flash before the current decoding and editing. Further, the determining module 606 determines a target error correction decoding scheme corresponding to the data to be decoded according to the extracted target error correction coding scheme, for example, analyzes the extracted target error correction coding scheme to obtain a coding mode and an error correction code of the target error correction coding scheme, for example, when the target error correction coding scheme is a single-stage error correction coding scheme, the coding mode is a single-stage error correction coding mode, the error correction code is a BCH code, and determines that the single-stage error correction decoding scheme is the target error correction decoding scheme according to the coding mode and the error correction code; when the target error correction coding scheme is a cascade error correction coding scheme, the coding mode is a cascade error correction coding mode, the error correction code is a combined code of a BCH code and an RS code, and the cascade error correction decoding scheme is determined to be the target error correction decoding scheme according to the coding mode and the error correction code. Finally, decoding and correcting the data to be decoded according to the target error correction decoding scheme by the decoding module 607 to obtain correct decoded data, wherein the decoded data obtained by decoding and correcting are accurate readable data. The acquisition module 605, the determination module 606 and the decoding module 607 provided by the device execute the decoding process to obtain accurate decoded data, which can be read by a user and has reliability.
The invention provides an electronic device, please refer to fig. 7, which is a structural diagram of the electronic device according to an embodiment of the invention, the electronic device includes: the memory 701, the processor 702 and the communication bus 703, the communication bus 703 is respectively connected with the memory 701 and the processor 702 in a communication way, the memory 701 is coupled with the processor 702, the memory 701 stores a computer program, and the processor 702 executes the computer program to implement each step in the data error correction method of Nand Flash in the above embodiment.
The computer program of the data error correction method of Nand Flash mainly comprises: when a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; performing error correction coding on the data to be written by using a target error correction coding scheme to obtain correct coded data; storing the coded data into a Nand Flash data area, and storing a target error correction coding scheme into a Nand Flash redundant area. In addition, a computer program may also be divided into one or more modules, one or more modules being stored in a memory and executed by a processor to accomplish the present invention. One or more modules may be a series of computer program instruction segments capable of performing particular functions to describe execution of a computer program in a computing device. For example, the computer program may be divided into an evaluation module 601, a selection module 602, an encoding module 603, a storage module 604, an acquisition module 605, a determination module 606, and a decoding module 607 as shown in fig. 6.
The processor 702 may be a central processing module (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The invention also provides a storage medium, which is a computer readable storage medium, and the computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the data error correction method of Nand Flash in the embodiment are realized.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.
The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing describes a method, apparatus, electronic device and storage medium for error correction of Nand Flash provided by the present invention, and those skilled in the art will change the specific implementation and application range according to the ideas of the embodiments of the present invention, so that the disclosure should not be construed as limiting the present invention.
Claims (8)
1. The data error correction method of Nand Flash is characterized by comprising the following steps:
When a programming instruction is received, inputting a preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate;
selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
performing error correction coding on the data to be written by using the target error correction coding scheme to obtain correct coded data;
storing the encoded data into a Nand Flash data area, and storing the target error correction encoding scheme into a Nand Flash redundant area;
the step of selecting the target error correction coding scheme in the preset error correction coding scheme list according to the estimated error rate comprises the following steps:
calculating the number of error bits in the data to be written according to the estimated error rate, wherein the error rate is the ratio of the number of error bits to the data to be written;
comparing the error bit number with a preset error bit number threshold value, and selecting the target error correction coding scheme in the error correction coding scheme list according to a comparison result;
if the target error correction coding scheme includes: the step of comparing the error bit number with a preset error bit number threshold value according to the single-stage error correction coding scheme and the cascade error correction coding scheme, and selecting the target error correction coding scheme in the error correction coding scheme list according to the comparison result comprises the following steps:
Comparing the error bit number with a preset error bit number threshold;
if the comparison result is that the error bit number is smaller than or equal to the error bit number threshold value, selecting the single-stage error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme;
and if the comparison result is that the error bit number is larger than the error bit number threshold value, selecting the cascade error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme.
2. The method for correcting data of Nand Flash according to claim 1, wherein the step of inputting the preset data holding time and the obtained editing times of the Nand Flash redundant area into the preset Nand Flash error rate model comprises:
receiving test data of a Nand Flash chip, wherein the test data comprises: a plurality of different mapping indexes and the error rates corresponding to the mapping indexes, wherein the mapping indexes comprise the editing times and the data retention time;
modeling according to a preset polynomial fitting rule by using the mapping index and the corresponding error rate respectively to obtain the Nand Flash error rate model.
3. The method for correcting data of Nand Flash according to claim 1, wherein the step of inputting the preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain the estimated error rate comprises:
accessing the Nand Flash redundant area of the Nand Flash chip;
extracting the editing times in the Nand Flash redundant area;
and inputting the preset data retention time and the preset editing times into the Nand Flash error rate model to obtain the estimated error rate.
4. The method for correcting data of Nand Flash according to claim 1, wherein the storing the encoded data in the Nand Flash data area and the storing the target error correction coding scheme in the Nand Flash redundant area comprises:
when a reading instruction is received, acquiring a target error correction coding scheme in the Nand Flash redundant area, and acquiring data to be decoded in the Nand Flash data area, wherein the data to be decoded is the coded data;
determining a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and decoding and correcting the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
5. The data error correction device of Nand Flash is characterized by comprising:
the evaluation module is used for inputting the preset data retention time and the acquired editing times of the Nand Flash redundant area into a preset Nand Flash error rate model when a programming instruction is received, so as to obtain an evaluated error rate;
the selecting module is used for selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
the error correction module is used for carrying out error correction coding on the data to be written by utilizing the target error correction coding scheme to obtain correct coded data;
the storage module is used for storing the encoded data into a Nand Flash data area and storing the target error correction encoding scheme into the Nand Flash redundant area;
the selecting module is specifically configured to: calculating the number of error bits in the data to be written according to the estimated error rate, wherein the error rate is the ratio of the number of error bits to the data to be written; comparing the error bit number with a preset error bit number threshold value, and selecting the target error correction coding scheme in the error correction coding scheme list according to a comparison result; if the target error correction coding scheme comprises a single-stage error correction coding scheme and a cascade error correction coding scheme, comparing the error bit number with a preset error bit number threshold; if the comparison result is that the error bit number is smaller than or equal to the error bit number threshold value, selecting the single-stage error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme; and if the comparison result is that the error bit number is larger than the error bit number threshold value, selecting the cascade error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme.
6. The Nand Flash data error correction device of claim 5, wherein the device further comprises:
the acquisition module is used for acquiring a target error correction coding scheme in the Nand Flash redundant area and acquiring data to be decoded in the Nand Flash data area when a reading instruction is received, wherein the data to be decoded is the coded data;
a determining module, configured to determine a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and the decoding module is used for decoding and correcting the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
7. An electronic device, comprising: the Nand Flash data error correction method is characterized in that the memory stores a computer program, and the processor executes the computer program to realize the steps in the Nand Flash data error correction method according to any one of claims 1 to 4.
8. A storage medium, which is a computer-readable storage medium, wherein the computer-readable storage medium has a computer program stored thereon, and the computer program, when executed by a processor, implements the steps of the data error correction method of Nand Flash according to any one of claims 1 to 4.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103269230A (en) * | 2013-05-28 | 2013-08-28 | 中国科学院自动化研究所 | Fault-tolerant system and method for adjusting error correcting codes adaptively |
| CN106685431A (en) * | 2016-12-05 | 2017-05-17 | 华南理工大学 | LDPC soft information decoding method and coder-decoder based on Nand Flash |
| CN106776104A (en) * | 2016-11-11 | 2017-05-31 | 大唐微电子技术有限公司 | A kind of method of Nand Flash controllers and terminal and control Nand Flash |
| CN107562563A (en) * | 2016-07-01 | 2018-01-09 | 龙芯中科技术有限公司 | Nand Flash control methods and device |
| CN107590021A (en) * | 2017-08-22 | 2018-01-16 | 华中科技大学 | A kind of coding and decoding device and coding and decoding method for reducing the flash memory bit error rate |
| CN108845890A (en) * | 2018-05-07 | 2018-11-20 | 西安电子科技大学 | Data verification method based on Nand flash storage array |
| CN111061592A (en) * | 2019-11-22 | 2020-04-24 | 山东航天电子技术研究所 | Universal Nand Flash bit reversal error correction method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008086237A2 (en) * | 2007-01-05 | 2008-07-17 | California Institute Of Technology | Codes for limited magnitude asymmetric errors in flash memories |
| US10901840B2 (en) * | 2018-06-28 | 2021-01-26 | Western Digital Technologies, Inc. | Error correction decoding with redundancy data |
-
2020
- 2020-07-03 CN CN202010630517.4A patent/CN111813591B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103269230A (en) * | 2013-05-28 | 2013-08-28 | 中国科学院自动化研究所 | Fault-tolerant system and method for adjusting error correcting codes adaptively |
| CN107562563A (en) * | 2016-07-01 | 2018-01-09 | 龙芯中科技术有限公司 | Nand Flash control methods and device |
| CN106776104A (en) * | 2016-11-11 | 2017-05-31 | 大唐微电子技术有限公司 | A kind of method of Nand Flash controllers and terminal and control Nand Flash |
| CN106685431A (en) * | 2016-12-05 | 2017-05-17 | 华南理工大学 | LDPC soft information decoding method and coder-decoder based on Nand Flash |
| CN107590021A (en) * | 2017-08-22 | 2018-01-16 | 华中科技大学 | A kind of coding and decoding device and coding and decoding method for reducing the flash memory bit error rate |
| CN108845890A (en) * | 2018-05-07 | 2018-11-20 | 西安电子科技大学 | Data verification method based on Nand flash storage array |
| CN111061592A (en) * | 2019-11-22 | 2020-04-24 | 山东航天电子技术研究所 | Universal Nand Flash bit reversal error correction method |
Non-Patent Citations (2)
| Title |
|---|
| 一种降低NAND Flash滞留错误的纠错方案;金令旭等;通信技术;141-145 * |
| 面向Nand Flash自适应纠错码方案研究与设计;周懿;计算机工程与设计;289-293 * |
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