CN111813591A - Data error correction method and device for Nand Flash, electronic equipment and storage medium - Google Patents
Data error correction method and device for Nand Flash, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN111813591A CN111813591A CN202010630517.4A CN202010630517A CN111813591A CN 111813591 A CN111813591 A CN 111813591A CN 202010630517 A CN202010630517 A CN 202010630517A CN 111813591 A CN111813591 A CN 111813591A
- Authority
- CN
- China
- Prior art keywords
- error correction
- data
- nand flash
- correction coding
- coding scheme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012937 correction Methods 0.000 title claims abstract description 331
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000013507 mapping Methods 0.000 claims description 39
- 238000012360 testing method Methods 0.000 claims description 26
- 230000014759 maintenance of location Effects 0.000 claims description 19
- 238000004590 computer program Methods 0.000 claims description 16
- 238000011156 evaluation Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 238000004891 communication Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000013598 vector Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a data error correction method of Nand Flash, which comprises the following steps: when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; carrying out error correction coding on data to be written by utilizing a target error correction coding scheme to obtain correct coded data; and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area. By implementing the scheme, the accuracy of evaluating the error rate can be improved, different target error correction coding schemes are selected for error correction coding according to the error rate, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Description
Technical Field
The invention relates to the technical field of Nand Flash data, in particular to a data error correction method and device of Nand Flash, electronic equipment and a storage medium.
Background
A Nand Flash (Flash memory) chip of a 3D (Three dimensional) vertical design has gradually implemented a structural design of vertical stacking on a silicon chip, and the Nand Flash has developed a Multi-bit storage technology, so that the chip storage technology has been gradually developed from a Single-bit SLC (Single Level cell) and a two-bit MLC (Multi-Level cell), a Three-bit MLC, a four-bit MLC, and the like. However, when the Nand Flash chip is used, the wear of the tunnel oxide of the chip increases with the increase of the number of programming/erasing times, so that the loss of charges is increased, and the error rate is increased.
In order to solve the problems, when data of Nand Flash is corrected, the related technology mainly performs ECC code design based on the worst case, for example, the ECC design is performed based on the case that 1 Kbyte contains 70-bit errors, and the technology can reduce the error rate of the data of the Nand Flash; however, in the initial use stage of Nand Flash, because the number of times of editing is small, the error rate is low, that is, the use in different stages has different data retention times and different error rates, if ECC code design is performed based on the worst case, the waste of operation time and storage space is caused, so that the error correction efficiency of the Nand Flash processor is low.
Therefore, it is necessary to provide a new data error correction technology of Nand Flash.
Disclosure of Invention
The application provides a data error correction method and device of Nand Flash, electronic equipment and a storage medium, which can solve the technical problem of low error correction efficiency of a Nand Flash processor.
The first aspect of the invention provides a data error correction method of Nand Flash, which comprises the following steps:
when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate;
selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
carrying out error correction coding on data to be written by utilizing the target error correction coding scheme to obtain correct coded data;
and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into the Nand Flash redundant area.
Optionally, the step of inputting the preset data holding time and the obtained editing times of the Nand Flash redundant area into the preset Nand Flash error rate model includes:
receiving test data of a Nand Flash chip, wherein the test data comprises: a plurality of different mapping indexes and the error rates corresponding to the mapping indexes, wherein the mapping indexes comprise the editing times and the data holding time;
and modeling according to a preset polynomial fitting rule by respectively utilizing the mapping indexes and the corresponding error rates to obtain the Nand Flash error rate model.
Optionally, the step of inputting the preset data retention time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain the estimated error rate includes:
accessing the Nand Flash redundant area of the Nand Flash chip;
extracting the editing times in the Nand Flash redundant area;
and inputting the preset data holding time and the preset editing times into the Nand Flash error rate model to obtain the estimated error rate.
Optionally, the step of selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate includes:
calculating the error bit number according to the estimated error rate, wherein the error rate is the ratio of the error bit number to the data to be written;
and comparing the error bit number with a preset error bit number threshold, and selecting the target error correction coding scheme in the error correction coding scheme list according to the comparison result.
Optionally, the target error correction coding scheme includes: the single-stage error correction coding scheme and the cascade error correction coding scheme, the step of comparing the error bit number with a preset error bit number threshold value according to the error bit number and selecting the target error correction coding scheme in the error correction coding scheme list according to the comparison result comprises the following steps:
comparing the error bit number with a preset error bit number threshold;
if the comparison result is that the error bit number is less than or equal to the error bit number threshold, selecting the single-level error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme;
and if the comparison result shows that the error bit number is greater than the threshold value of the error bit number, selecting the cascade error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme.
Optionally, after the steps of storing the encoded data in a Nand Flash data area and storing the target error correction coding scheme in the Nand Flash redundant area, the method includes:
when a reading instruction is received, acquiring a target error correction coding scheme in the Nand Flash redundant area and acquiring data to be decoded in the Nand Flash data area, wherein the data to be decoded is the coded data;
determining a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and carrying out decoding error correction on the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
The second aspect of the present invention provides a data error correction device for Nand Flash, which comprises:
the evaluation module is used for inputting the preset data holding time and the obtained editing times of the NandFlash redundant area into a preset NandFlash error rate model when a programming instruction is received, so as to obtain an evaluated error rate;
the selecting module is used for selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
the error correction module is used for carrying out error correction coding on data to be written by utilizing the target error correction coding scheme to obtain correct coded data;
and the storage module is used for storing the coded data to a Nand Flash data area and storing the target error correction coding scheme to the Nand Flash redundant area.
Optionally, the apparatus further comprises:
the acquisition module is used for acquiring a target error correction coding scheme in the Nand Flash redundant area and acquiring data to be decoded in the Nand Flash data area when a reading instruction is received, wherein the data to be decoded is the coded data;
a determining module, configured to determine a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and the decoding module is used for carrying out decoding error correction on the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
A third aspect of the present invention provides an electronic device comprising: the data error correction method of the Nand Flash comprises a memory, a processor and a communication bus, wherein the communication bus is respectively in communication connection with the memory and the processor, the memory is stored with a computer program, and when the processor executes the computer program, each step in the data error correction method of the Nand Flash in the first aspect is realized.
A fourth aspect of the present invention provides a storage medium, which is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium, and when being executed by a processor, the computer program implements each step in the data error correction method for Nand Flash according to the first aspect.
The data error correction method of Nand Flash provided by the invention comprises the following steps: when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; carrying out error correction coding on data to be written by utilizing a target error correction coding scheme to obtain correct coded data; and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area. By implementing the scheme, the error rate is estimated through the editing times and the data retention time of the Nand Flash, the accuracy of the estimated error rate is improved, different target error correction coding schemes are selected according to the error rate, the data to be written are subjected to error correction coding by using the target error correction coding schemes, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1a is a schematic diagram of a Nand Flash structure according to an embodiment of the present invention;
FIG. 1b is a schematic diagram of a Nand Flash memory array structure provided in an embodiment of the present invention
FIG. 2 is a schematic diagram of a Nand Flash error rate model according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating steps of a data error correction method for Nand Flash according to an embodiment of the present invention;
FIG. 4 is a flowchart of another step of the data error correction method for Nand Flash according to the embodiment of the present invention;
FIG. 5 is a flowchart of a detailed procedure of the data error correction method of Nand Flash provided in FIG. 4;
FIG. 6 is a block diagram of a data error correction device of Nand Flash according to an embodiment of the present invention;
fig. 7 is an architecture diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Due to the technical problem that the error correction efficiency of the Nand Flash processor in the prior art is low.
In order to solve the technical problem, the invention provides a data error correction method and device for Nand Flash, electronic equipment and a storage medium.
Referring to fig. 1a and fig. 1b, fig. 1a is a schematic structural diagram of a Flash Nand Flash according to an embodiment of the present invention, where the schematic structural diagram is a structural diagram of a LUN (logical Unit nuber), and one LUN represents a Nand Flash (Flash memory) chip, and in the schematic structural diagram of the Nand Flash, one Nand Flash chip includes two parts, namely, a storage array structure 101 and a cache structure 102. In one aspect, the memory array structure 101 has two planes 1011 (sections or stages, etc.), each Plane1011 contains 2048 blocks (physical blocks or memory physical blocks), each LUN contains 4096 blocks, each block has 128 pages inside, and each page contains 8.448 Kbytes.
Further, referring to fig. 1b, fig. 1b is a schematic diagram of a Nand Flash memory array structure according to an embodiment of the present invention, where each page includes: the embodiment of the present invention collectively refers to the data area as Nand Flash data area 10111 and the redundant area as Nand Flash redundant area 10112, where each Plane includes: a Nand Flash data area 10111 and a Nand Flash redundant area 10112.
It is understood that Nand Flash data area 10111 is used to store written data, and Nand Flash redundant area 10112 is used to store: address mapping information, chip editing times, ECC check codes, bad block management and the like; in another aspect, the cache structure 102 includes: cache Register1021 (Cache memory) and Data Register1022 (Data Register), it can be understood that the memory array structure is logically divided into two planes 1011, each Plane1011 is divided into 2048 blocks, each block is divided into 128 pages, each page contains 8.448 kbytes, and the Cache structure 102 is also correspondingly divided into the same array, so as to implement mapping of Data in the memory array structure and address in the Cache structure, so as to improve the speed of Data processing, such as Data reading, storing or testing, but not limited thereto, other Nand Flash Data processing manners also belong to the scope included in the present embodiment.
Two factors that contribute to the degradation of the reliability of Nand Flash are: the Nand Flash and the edit times (programming/erasing times) of data adopt a multi-bit storage technology. On one hand, data editing of the Nand Flash memory array can cause degradation of a tunneling oxide layer, specifically, editing operation mainly depends on charge transmission through a thin oxide layer and Fowler Nordheim (FN) tunneling in and out of a memory layer, and after tunneling, traps are charged to an oxide state and an interface state to physically abrade the tunneling oxide of a silicon nitride film; it may cause a charge to be trapped in the tunnel oxide or an excessive charge to flow into/out of the memory layer, thereby lowering the threshold voltage of the memory cell and lowering reliability. On the other hand, after the multi-bit storage technology is adopted, the change field of the grid threshold voltage is divided into a plurality of small areas, so that the fault tolerance rate between the areas is too small, the threshold voltages between adjacent areas are easily influenced mutually, and error bits are generated; from SLC to TLC, the original error rate of Nand Flash storage is directly reduced by 10-3 orders of magnitude, which reduces reliability, so that in order to ensure the reading correctness of Nand Flash storage data, an ECC (error correcting Code) is usually introduced into a Nand Flash processor to reduce the error rate.
The design of the ECC correction scheme of the embodiment of the invention is determined based on the error rate, so that the error rate of data in the NandFlash memory array needs to be analyzed. Because different programming/erasing times and data retention time can influence the error rate of NandFlash data, in order to accurately evaluate the error rate, the following operations need to be executed:
firstly, a chip test is required to test the influence of different editing times and data retention time on the error rate. Generally, the editing times of 3D Nand Flash are about 3000 times, the test scheme is set according to the editing times, and the test process is as follows: 1. programming and writing '0 x 55' vectors into odd pages of the Nand Flash chip, programming and writing '0 xAA' vectors into even pages, reading data after programming, and storing the data as an independent file; 2. performing programming/erasing circulation on the Nand Flash for 100 times; 3. the aging of the chip is accelerated in a high-temperature environment to shorten the testing time, the Nand Flash is placed in a high-temperature box with the temperature of 125 ℃, 1 data reading operation is set to be carried out every 5 minutes, the reading result is compared with an independent file, and the number of error bits is recorded; 4. when the test time reaches 100 hours (equivalent to 10 years at 55 ℃), the test is stopped; 5. adding 100 times of programming/erasing circulation to the Nand Flash every time, and repeating the steps 3 and 4; 6. when the Nand Flash programming/erasing cycle times reach 3000 times, the test is finished; 7. the obtained test data (the number of times of editing, the data retention time, and the error rate) is built into a table or recorded into the table, and further description is not given to drawing and recording of the table in this embodiment, as long as the common influence factor of the error rate, which is the number of times of editing and the data retention time, is embodied, and the change of the error rate under the influence of the common factor is embodied. By testing the chip at this stage, the change condition of the bit error rate under the common influence of the editing times and the data retention time can be analyzed, and the accuracy of evaluating the bit error rate is improved.
And secondly, modeling and fitting the error rate distribution condition of the Nand Flash according to the test data, specifically modeling in a polynomial fitting mode, and obtaining a Nand Flash error rate model. After modeling, the processor can predict the error rate when writing or programming data according to the current editing times and data retention time of NandFlash.
Referring to fig. 2, a schematic diagram of a Nand Flash error rate model according to an embodiment of the present invention is shown; the method comprises the steps of obtaining the editing times and the data holding time of Nand Flash, inputting the obtained editing times and the data holding time of a Nand Flash memory array into a Nand Flash error rate model 201, and obtaining a corresponding estimated error rate.
Referring to fig. 3, which is a flow chart of steps of a data error correction method of Nand Flash according to an embodiment of the present invention, the embodiment of the present invention provides a data error correction method of Nand Flash, which is applied to the Nand Flash memory array shown in fig. 1 as an example, evaluates the error rate of the Nand Flash memory array shown in fig. 1, and selects an error correction coding scheme based on the error rate, and specifically, when a processor corresponding to the Nand Flash executes a program, the method of data error correction of Nand Flash according to the embodiment is implemented, and includes the following steps:
step S301: and when a programming instruction is received, inputting the preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate.
Specifically, the programming instruction can be an input programming start instruction or a human-triggered programming start instruction, the programming instruction is received through a processor, the processor is a processor of a computer and can also be a control unit or a data processing unit specially applied to Nand Flash data editing, when the programming instruction of the processor is processed, a Nand Flash redundant area in a Nand Flash storage array is accessed, the current editing times are obtained from the Nand Flash redundant area, and the corresponding error rate is evaluated through a Nand Flash error rate model by utilizing the editing times and the preset data holding time.
The Nand Flash error rate model comprises different mapping indexes and mapping relations of the error rate, and the mapping indexes comprise editing times and data holding time. It can be understood that the Nand Flash error rate model uses the editing times and the data retention time as mapping indexes, and the corresponding error rate can be obtained through the mapping indexes. It should be noted that the error rate obtained by using the mapping index through the Nand Flash error rate model is the current error rate of the Nand Flash or the chip, and if the current Nand Flash chip is programmed or written with data, the programmed or written Nand Flash chip has the error bit number corresponding to the currently estimated error rate. Therefore, before programming or writing data into the Nand Flash chip, the current error rate of the Nand Flash or the chip needs to be evaluated, and the accuracy of obtaining the error rate of the Nand Flash chip can be improved through the step S301.
Step S302: and selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate.
Specifically, the preset Error correction coding scheme list includes a plurality of Error correction coding schemes, where the Error correction coding schemes include an ECC (Error correction Code) Code and a coding mode, and the ECC Error correction codes and the coding modes adopted in the plurality of Error correction coding schemes are different. Preferably, the present embodiment includes two error correction coding schemes, such as: the single-stage error correction coding scheme and the cascade error correction coding scheme adopt different ECC (error correction code) and coding modes, for example, the single-stage error correction coding scheme adopts a single-stage coding mode, and the adopted error correction code is a BCH (broadcast channel) code; the cascade error correction coding scheme adopts a cascade coding mode, the adopted error correction code is the combination of an RS code and a BCH code, and in addition, the cascade error correction coding scheme can also adopt other error correction codes such as the combination of the RS code and the LDPC code; it should be noted that, after the data to be written is encoded and error-corrected, the encoded data is stored in the Nand Flash data area, and the encoded error-correction coding scheme is stored in the Nand Flash redundant area, because the lengths of the error-correction codes of different error-correction coding schemes are different, if a longer ECC error-correction code is adopted, the processor needs to spend more operation time, and can compress the storage of other information (such as information data of editing times and the like), therefore, an error-correction coding scheme including a shorter error-correction code suitable for error correction needs to be selected according to the estimated error rate, so as to save the storage space of the Nand Flash redundant area after encoding. Further, a target error correction coding scheme in a preset error correction coding scheme list is selected according to the error rates with different complexity degrees, and the target error correction coding scheme is an error correction coding scheme corresponding to the error rate before the single error correction coding scheme. By implementing the scheme of the step, the corresponding error correction coding scheme can be selected according to different error rates, so that the operation time can be reduced, and the storage space can be saved.
Step S303: and carrying out error correction coding on the data to be written by utilizing a target error correction coding scheme to obtain correct coded data.
Specifically, after the error correction coding scheme is selected, the error correction coding scheme is used to perform error correction coding on the data to be written, so that the accurate coded data subjected to error correction coding can be obtained. For example, when the error rate is low, the selected error correction coding scheme is a single-stage error correction coding scheme, the single-stage error correction coding scheme is a simpler error correction coding scheme, and the error correction coding scheme has the characteristic of short operation time, the error correction code is a BCH code, that is, the code length of the error correction code of the single-stage error correction coding scheme is shorter, the single-stage error correction coding scheme is applied to the Nand Flash life period with the low error rate, it needs to be noted that the Nand Flash life period is related to the editing times and the data retention time of the Nand Flash, and because the error rate of data in the initial use stage of the Nand Flash chip is low, the single-stage error correction coding scheme is adopted, and the error correction coding can be; when the error rate is higher than the specific value, a cascade error correction coding scheme is selected, the error correction code can be selected to be the combination of the RS code and the BCH code, the cascade error correction coding scheme has the advantage of strong error correction capability, the operation of the cascade error correction coding scheme is complex, more operation time is needed, and the cascade error correction coding scheme is suitable for error correction coding of data to be written under the condition of high error rate. Therefore, no matter the number of error bits corresponding to the error rate in the data, the complete ECC algorithm needs to be run to complete the check (error correction coding). By implementing the scheme of the step, the data to be written can be coded according to the selected target error correction coding scheme, the accuracy of the data can be improved, the situation that the data to be written has errors after being coded is prevented, and the reliability is higher.
Step S304: and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area.
Specifically, after error correction coding is performed on data to be written, the obtained coded data and a target error correction coding scheme are stored in a Nand Flash memory array structure, wherein the Nand Flash memory array structure comprises: a Nand Flash data area and a Nand Flash redundant area. The data and the target error correction coding scheme are saved by storing the coded data into a Nand Flash data area and storing the target error correction coding scheme into a Nand Flash redundant area, so that a decoding basis of the data to be decoded and the decoding error correction scheme is provided for error correction decoding; it should be noted that, when the encoded data is stored in the Nand Flash data area and the target error correction coding scheme is stored in the Nand Flash redundant area, indicating that one editing (programming after data erasure and erasure) is completed on the Nand Flash, the number of editing times in the Nand Flash redundant area is increased by 1, so that each editing (programming after erasure and erasure) on the Nand Flash will update the number of editing times in the Nand Flash redundant area. By implementing the technology of the step, the storage of the coded data and the target error correction coding scheme can be realized, and the reliability of the NandFlash is improved.
The embodiment provides a data error correction method of Nand Flash, which comprises the following steps: when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and mapping relations of the error rate, and the mapping indexes comprise the editing times and the data holding time; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; carrying out error correction coding on data to be written by utilizing a target error correction coding scheme to obtain correct coded data; and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area. By implementing the scheme, the error rate is estimated through the editing times and the data retention time of the Nand Flash, the accuracy of the estimated error rate is improved, different target error correction coding schemes are selected according to the error rate, the data to be written are subjected to error correction coding by using the target error correction coding schemes, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Referring to fig. 4, which is a flowchart illustrating another step of the data error correction method for Nand Flash according to an embodiment of the present invention, the data error correction method for Nand Flash according to another embodiment of the present invention includes:
s401: receiving test data of the Nand Flash chip, wherein the test data comprises the following steps: and a plurality of mapping indexes and error rates corresponding to the mapping indexes.
In step S401, test data after testing the Nand Flash chip is received, where the test data specifically includes: the method comprises the steps of obtaining a plurality of editing times and a plurality of data holding times, and further comprising a plurality of error rates corresponding to a plurality of mapping indexes combining the plurality of editing times and the plurality of data holding times, wherein the plurality of data are data obtained by testing a Nand Flash chip, namely, the Nand Flash chip is erased and programmed after being erased, the programmed data are read to calculate the error rate, the error rates of the Nand Flash chip under different editing times (the times of programming after being erased and erased) and different data holding times are tested through continuous erasing/programming operation, and the error rate distribution conditions of the Nand Flash chip series under the editing times and the data holding time factors can be analyzed through the test data.
S402: and modeling according to a preset polynomial fitting rule by using the mapping indexes and the corresponding error rates respectively to obtain a Nand Flash error rate model.
Specifically, modeling fitting is carried out on the error rate distribution condition of the Nand Flash according to the test data, modeling is carried out according to a preset polynomial fitting rule by utilizing the mapping indexes and the corresponding error rates, and a Nand Flash error rate model is obtained. The scheme of the step can improve the efficiency and the accuracy of evaluating the error rate.
S403: when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and mapping relations of the error rate, and the mapping indexes comprise the editing times and the data holding time.
S404: and selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate.
S405: and carrying out error correction coding on the data to be written by utilizing a target error correction coding scheme to obtain correct coded data.
S406: and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area.
In the embodiment of the present invention, steps S403 to S406 are the same as or similar to the technical features of steps S301 to S304 in the data error correction method for Nand Flash provided in the foregoing embodiment, and the detailed descriptions of steps S403 to S406 refer to the descriptions of steps S301 to S304, which is not further limited in this embodiment.
Optionally, step S403 includes:
and accessing the Nand Flash redundant area. Specifically, the Nand Flash comprises a Nand Flash data area and a Nand Flash redundant area, wherein the Nand Flash data area is used for storing written coded data, and the coded data can be further understood as data needing to be stored; and the Nand Flash redundant area is used for storing: and data such as a target error correction coding scheme, editing times and the like, therefore, in order to evaluate the current error rate of the Nand Flash, the Nand Flash redundant area needs to be accessed firstly if the written data needs to be acquired or the editing times and the data retention time before coding are carried out.
Further, the editing times in the Nand Flash redundant area are extracted. And after accessing the Nand Flash redundant area, extracting the editing times in the Nand Flash redundant area. It can be understood that the number of edits is the number of edits made after the data was written into NandFlash last time, that is, the number of edits made after the last programming.
Furthermore, preset data holding time and editing times are input into a Nand Flash error rate model to obtain an estimated error rate.
Specifically, the data retention time is the total storage time in Nand Flash after the programming of the data to be written is estimated before the current editing, for example, when the Nand Flash is used for the first time, the time period from the time when the data is written into the Nand Flash to the time when the data is deleted or erased is the corresponding data retention time for each time, and the data retention time can be used for determining the required storage time of the data after each programming or the frequency of updating/reprogramming of the data after the programming. After the editing times in the Nand Flash redundant area are obtained, the editing times and the preset data holding time are input into a pre-established Nand Flash error rate model, and the Nand Flash error rate model calculates or maps according to the editing times and the data holding time to obtain a corresponding estimated error rate, so that the accuracy of obtaining the Nand Flash or the chip error rate is improved.
Referring to fig. 5, fig. 5 is a flowchart illustrating a detailed procedure of the data error correction method of Nand Flash provided in fig. 4, where the method includes:
s401: receiving test data of the Nand Flash chip, wherein the test data comprises the following steps: and a plurality of mapping indexes and error rates corresponding to the mapping indexes.
S402: and modeling according to a preset polynomial fitting rule by using the mapping indexes and the corresponding error rates respectively to obtain a Nand Flash error rate model.
S403: when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and mapping relations of the error rate, and the mapping indexes comprise the editing times and the data holding time.
Further, step S404 includes:
s4041: calculating the error bit number in the data to be written according to the estimated error rate, wherein the error rate is the ratio of the error bit number to the data to be written;
s4042: and comparing the error bit number with a preset error bit number threshold, and selecting a target error correction coding scheme in the error correction coding scheme list according to the comparison result.
In step S404, after obtaining the estimated error rate, calculating or estimating an error bit number of data to be written by using the estimated error rate, where the data to be written is data stored in a Nand Flash data area in a programming manner, for example, the Nand Flash data area can store 8K bytes, and the error rate can be an error rate corresponding to every 1K bytes; the bit error rate is used for evaluating or budgeting the number of error bits appearing in the data to be written, and the number of error bits in unit transmission data can be calculated according to the bit error rate. Furthermore, the error bit number is compared with a preset error bit number threshold, the error bit number threshold is a preset threshold and is used for judging whether the error bit number in the data to be written is a condition that the data contains serious errors or not, a comparison result can be obtained through comparison, and then a target error correction coding scheme in an error correction coding scheme list is selected according to the comparison result, so that the corresponding error correction coding scheme is selected according to different error rates, the operation time can be reduced, and the storage space can be saved.
S405: and carrying out error correction coding on the data to be written by utilizing a target error correction coding scheme to obtain correct coded data.
S406: and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area.
Further, the target error correction coding scheme includes: a single-level error correction coding scheme and a cascade error correction coding scheme, step S4042 specifically includes:
comparing the error bit number with a preset error bit number threshold;
if the comparison result is that the error bit number is less than or equal to the threshold value of the error bit number, selecting a single-level error correction coding scheme in the error correction coding scheme list as a target error correction coding scheme;
and if the comparison result shows that the number of error bits is larger than the threshold of the number of error bits, selecting a cascade error correction coding scheme in the error correction coding scheme list as a target error correction coding scheme.
Specifically, the target error correction coding scheme includes: a single-level error correction coding scheme and a concatenated error correction coding scheme. Comparing the error bit number with a preset error bit number threshold, if the preset error bit number threshold is set to be 30, and if the error bit number is greater than the error bit number threshold 30 when the error bit number is 31, 40, 70 and the like, determining that the error bit number is the condition that the data contains serious errors, and the unit transmission data is a more complex error bit number, and selecting a cascade error correction coding scheme (the error correction coding scheme containing the BCH code and the RS code) in an error correction coding scheme list as a target error correction coding scheme. If the number of error bits is a value of 10, 20, 29, 30 or the like which is less than or equal to 30, and the number of error bits is less than or equal to the error bit number threshold 30, it is determined that the number of error bits is a case where the data includes a mild error, the unit transmission data appears as a simpler number of error bits, and a single-stage error correction coding scheme (the above-described error correction coding scheme including the BCH code) in the error correction coding scheme list is selected as the target error correction coding scheme.
Further, after step S304 or step S406, the method includes:
when a reading instruction is received, acquiring a target error correction coding scheme in a Nand Flash redundant area, and acquiring data to be decoded in a Nand Flash data area, wherein the data to be decoded is coded data;
determining a target error correction decoding scheme of data to be decoded according to the target error correction coding scheme;
and carrying out decoding error correction on the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
Specifically, the data error correction method of Nand Flash according to the embodiment of the present invention further includes: the decoding and error correction are carried out on the data written into the NandFlash storage array, the decoding process can be a data reading process, the encoded data in the NandFlash storage array can be accurately read through decoding, and it needs to be noted that the decoding process does not delete/erase the data in the NandFlash data area, and specifically is a process of analyzing and interpreting the data in the data reading process. When a reading instruction is received, extracting a target error correction coding scheme in a Nand Flash redundant area, wherein the target error correction coding scheme is an error correction coding scheme when data is written into Nand Flash last time, it needs to be noted that a Nand Flash storage array contains a plurality of data, the target error correction coding scheme extracted from the Nand Flash redundant area is an error correction coding scheme corresponding to the data to be decoded, the data to be decoded is data to be decoded, and the data to be decoded is written into a Nand Flash data area in the Nand Flash before the decoding operation. Further, a target error correction decoding scheme corresponding to the data to be decoded is determined according to the extracted target error correction coding scheme, specifically, the extracted target error correction coding scheme is analyzed to obtain a coding mode and an error correction code of the target error correction coding scheme, for example, when the target error correction coding scheme is a single-stage error correction coding scheme, the coding mode is a single-stage error correction coding mode, the error correction code is a BCH code, and the single-stage error correction decoding scheme is determined to be the target error correction decoding scheme according to the coding mode and the error correction code; and when the target error correction coding scheme is the cascade error correction coding scheme, the coding mode is the cascade error correction coding mode, the error correction code is a combined code of a BCH code and an RS code, and the cascade error correction decoding scheme is determined to be the target error correction decoding scheme according to the coding mode and the error correction code. In addition, the data to be decoded is decoded and error-corrected according to the target error correction decoding scheme to obtain correct decoded data, and the decoded data obtained through decoding and error correction is accurate readable data which can be read by a user and has reliability.
It should be noted that the data reading operation does not belong to the editing (erasing/programming) of Nand Flash, and after the decoding process is completed, the data stored in the Nand Flash data area can be read, and the editing times of the Nand Flash redundant area cannot be increased.
Referring to fig. 6, fig. 6 is a data error correction device of Nand Flash according to an embodiment of the present invention, where the device corresponds to the data error correction method of Nand Flash described above, and the device 600 includes:
the evaluation module 601 is used for inputting preset data holding time and the obtained editing times of the NandFlash redundant area into a preset Nand Flash error rate model to obtain an evaluated error rate when a programming instruction is received, wherein the Nand Flash error rate model comprises different mapping indexes and mapping relations of the error rate, and the mapping indexes comprise the editing times and the data holding time;
a selecting module 602, configured to select a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
the encoding module 603 is configured to perform error correction encoding on data to be written by using a target error correction encoding scheme to obtain correct encoded data;
and the storage module 604 is used for storing the coded data into a Nand Flash data area and storing the target error correction coding scheme into a Nand Flash redundant area.
The invention provides a data error correction device of Nand Flash, which comprises: an evaluation module 601, a selection module 602, an encoding module 603, and a storage module 604. When a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model through an evaluation module 601 to obtain an evaluated error rate, wherein the Nand Flash error rate model comprises different mapping indexes and mapping relations of the error rate, and the mapping indexes comprise the editing times and the data holding time; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate through a selection module 602; error correction coding is performed on data to be written by using a target error correction coding scheme through a coding module 603 to obtain correct coded data; the encoded data is stored in the Nand Flash data area and the target error correction coding scheme is stored in the Nand Flash redundant area through the storage module 604. By implementing the scheme, the error rate is evaluated by the evaluation module 601 according to the editing times and the data retention time of the Nand Flash, the accuracy of the evaluation of the error rate is improved, different target error correction coding schemes are selected by the selection module 602 according to the error rate, the data to be written is subjected to error correction coding by using the target error correction coding schemes, the resource occupation and the power consumption are reduced, and the error correction coding efficiency of the Nand Flash processor under different error rates is improved.
Further, the apparatus 600 further includes: the obtaining module 605, the determining module 606, and the decoding module 607 are as follows:
the obtaining module 605 is configured to, when receiving the reading instruction, obtain a target error correction coding scheme in the Nand Flash redundant area, and obtain data to be decoded in the Nand Flash data area, where the data to be decoded is coded data.
A determining module 606, configured to determine a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme.
The decoding module 607 is configured to perform decoding and error correction on the data to be decoded according to the target error correction decoding scheme, so as to obtain correct decoded data.
The data error correction device of the programming instruction Nand Flash provided by the invention also comprises: the data reading device comprises an acquisition module 605, a determination module 606 and a decoding module 607, which are used for decoding and editing the data written into the Nand Flash storage array, wherein the decoding process can be a data reading process, and the encoded data in the Nand Flash storage array can be accurately read through decoding. Specifically, when a reading instruction is received, the obtaining module 605 obtains a target error correction coding scheme in the Nand Flash redundant area, where the target error correction coding scheme is an error correction coding scheme when data is written into the Nand Flash last time or another target error correction coding scheme before the current decoding and editing, and it needs to be noted that the Nand Flash storage array contains multiple data, the target error correction coding scheme extracted from the Nand Flash redundant area is an error correction coding scheme corresponding to the data to be decoded, where the data to be decoded is data to be decoded, and the data to be decoded is a Nand Flash data area written into the Nand Flash before the current decoding and editing. Further, the determining module 606 determines a target error correction decoding scheme corresponding to the data to be decoded according to the extracted target error correction coding scheme, for example, analyzes the extracted target error correction coding scheme to obtain a coding mode and an error correction code of the target error correction coding scheme, for example, when the target error correction coding scheme is a single-stage error correction coding scheme, the coding mode is a single-stage error correction coding mode, the error correction code is a BCH code, and the single-stage error correction decoding scheme is determined to be the target error correction decoding scheme according to the coding mode and the error correction code; and when the target error correction coding scheme is the cascade error correction coding scheme, the coding mode is the cascade error correction coding mode, the error correction code is a combined code of a BCH code and an RS code, and the cascade error correction decoding scheme is determined to be the target error correction decoding scheme according to the coding mode and the error correction code. Finally, the decoding module 607 decodes and corrects the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data, and the decoded data obtained through decoding and correcting are accurate readable data. The acquisition module 605, the determination module 606 and the decoding module 607 provided by the device execute the decoding process to obtain accurate decoding data which can be read by a user and has reliability.
The present invention provides an electronic device, please refer to fig. 7, which is an architecture diagram of the electronic device according to an embodiment of the present invention, and the electronic device includes: the memory 701, the processor 702 and the communication bus 703, the communication bus 703 is respectively connected to the memory 701 and the processor 702 in a communication manner, the memory 701 is coupled to the processor 702, a computer program is stored on the memory 701, and when the processor 702 executes the computer program, each step in the data error correction method of Nand Flash in the above embodiment is implemented.
Illustratively, the computer program of the data error correction method of Nand Flash mainly includes: when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate; selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate; carrying out error correction coding on data to be written by utilizing a target error correction coding scheme to obtain correct coded data; and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into a Nand Flash redundant area. In addition, the computer program may also be divided into one or more modules, which are stored in the memory and executed by the processor to accomplish the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing certain functions, the instruction segments being used to describe the execution of a computer program in a computing device. For example, the computer program may be divided into an evaluation module 601, a selection module 602, an encoding module 603, a storage module 604, an acquisition module 605, a determination module 606, and a decoding module 607 as shown in fig. 6.
The Processor 702 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The invention further provides a storage medium, the storage medium is a computer-readable storage medium, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps in the data error correction method of Nand Flash in the embodiment are realized.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the above description, for a person skilled in the art, according to the idea of the embodiment of the present invention, there are changes in the specific implementation and application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A data error correction method of Nand Flash is characterized by comprising the following steps:
when a programming instruction is received, inputting preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate;
selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
carrying out error correction coding on data to be written by utilizing the target error correction coding scheme to obtain correct coded data;
and storing the coded data into a Nand Flash data area, and storing the target error correction coding scheme into the Nand Flash redundant area.
2. The Nand Flash data error correction method of claim 1, wherein the step of inputting the preset data retention time and the obtained edit times of the Nand Flash redundant area into a preset Nand Flash error rate model comprises:
receiving test data of a Nand Flash chip, wherein the test data comprises: a plurality of different mapping indexes and the error rates corresponding to the mapping indexes, wherein the mapping indexes comprise the editing times and the data holding time;
and modeling according to a preset polynomial fitting rule by respectively utilizing the mapping indexes and the corresponding error rates to obtain the Nand Flash error rate model.
3. The Nand Flash data error correction method as claimed in claim 1, wherein the step of inputting the preset data retention time and the obtained edit times of the Nand Flash redundant area into a preset Nand Flash error rate model to obtain an estimated error rate comprises:
accessing the Nand Flash redundant area of the Nand Flash chip;
extracting the editing times in the Nand Flash redundant area;
and inputting the preset data holding time and the preset editing times into the Nand Flash error rate model to obtain the estimated error rate.
4. The data error correction method of Nand Flash as claimed in claim 1, wherein the step of selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate comprises:
calculating the error bit number in the data to be written according to the estimated error rate, wherein the error rate is the ratio of the error bit number to the data to be written;
and comparing the error bit number with a preset error bit number threshold, and selecting the target error correction coding scheme in the error correction coding scheme list according to the comparison result.
5. The data error correction method of Nand Flash as claimed in claim 4, wherein the target error correction coding scheme comprises: the single-stage error correction coding scheme and the cascade error correction coding scheme, the step of comparing the error bit number with a preset error bit number threshold value according to the error bit number and selecting the target error correction coding scheme in the error correction coding scheme list according to the comparison result comprises the following steps:
comparing the error bit number with a preset error bit number threshold;
if the comparison result is that the error bit number is less than or equal to the error bit number threshold, selecting the single-level error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme;
and if the comparison result shows that the error bit number is greater than the threshold value of the error bit number, selecting the cascade error correction coding scheme in the error correction coding scheme list as the target error correction coding scheme.
6. The Nand Flash data error correction method as claimed in claim 1, wherein the steps of storing the encoded data into a Nand Flash data area and storing the target error correction coding scheme into the Nand Flash redundant area are followed by:
when a reading instruction is received, acquiring a target error correction coding scheme in the Nand Flash redundant area and acquiring data to be decoded in the Nand Flash data area, wherein the data to be decoded is the coded data;
determining a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and carrying out decoding error correction on the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
7. A data error correction device of Nand Flash is characterized by comprising:
the evaluation module is used for inputting the preset data holding time and the obtained editing times of the Nand Flash redundant area into a preset Nand Flash error rate model when a programming instruction is received, so as to obtain an evaluated error rate;
the selecting module is used for selecting a target error correction coding scheme in a preset error correction coding scheme list according to the estimated error rate;
the error correction module is used for carrying out error correction coding on data to be written by utilizing the target error correction coding scheme to obtain correct coded data;
and the storage module is used for storing the coded data to a Nand Flash data area and storing the target error correction coding scheme to the Nand Flash redundant area.
8. The data error correction device of Nand Flash as claimed in claim 7, wherein the device further comprises:
the acquisition module is used for acquiring a target error correction coding scheme in the Nand Flash redundant area and acquiring data to be decoded in the Nand Flash data area when a reading instruction is received, wherein the data to be decoded is the coded data;
a determining module, configured to determine a target error correction decoding scheme of the data to be decoded according to the target error correction coding scheme;
and the decoding module is used for carrying out decoding error correction on the data to be decoded according to the target error correction decoding scheme to obtain correct decoded data.
9. An electronic device, comprising: the Nand Flash data error correction method is characterized in that a computer program is stored in the memory, and when the computer program is executed by the processor, each step in the Nand Flash data error correction method is realized according to any one of claims 1 to 6.
10. A storage medium which is a computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps in the data error correction method of Nand Flash as set forth in any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010630517.4A CN111813591B (en) | 2020-07-03 | 2020-07-03 | Data error correction method and device of Nand Flash, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010630517.4A CN111813591B (en) | 2020-07-03 | 2020-07-03 | Data error correction method and device of Nand Flash, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111813591A true CN111813591A (en) | 2020-10-23 |
| CN111813591B CN111813591B (en) | 2023-12-29 |
Family
ID=72856737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010630517.4A Active CN111813591B (en) | 2020-07-03 | 2020-07-03 | Data error correction method and device of Nand Flash, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111813591B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115562902A (en) * | 2022-01-11 | 2023-01-03 | 荣耀终端有限公司 | Storage area coding method and device and related equipment |
| CN116467131A (en) * | 2023-06-19 | 2023-07-21 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
| CN116521432A (en) * | 2023-04-06 | 2023-08-01 | 珠海妙存科技有限公司 | Method for improving reliability of flash memory, controller and computer storage medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080168320A1 (en) * | 2007-01-05 | 2008-07-10 | California Institute Of Technology | Codes For Limited Magnitude Asymetric Errors In Flash Memories |
| CN103269230A (en) * | 2013-05-28 | 2013-08-28 | 中国科学院自动化研究所 | Fault-tolerant system and method for adjusting error correcting codes adaptively |
| CN106685431A (en) * | 2016-12-05 | 2017-05-17 | 华南理工大学 | LDPC soft information decoding method and coder-decoder based on Nand Flash |
| CN106776104A (en) * | 2016-11-11 | 2017-05-31 | 大唐微电子技术有限公司 | A kind of method of Nand Flash controllers and terminal and control Nand Flash |
| CN107562563A (en) * | 2016-07-01 | 2018-01-09 | 龙芯中科技术有限公司 | Nand Flash control methods and device |
| CN107590021A (en) * | 2017-08-22 | 2018-01-16 | 华中科技大学 | A kind of coding and decoding device and coding and decoding method for reducing the flash memory bit error rate |
| CN108845890A (en) * | 2018-05-07 | 2018-11-20 | 西安电子科技大学 | Data verification method based on Nand flash storage array |
| US20200004627A1 (en) * | 2018-06-28 | 2020-01-02 | Western Digital Technologies, Inc. | Error correction decoding with redundancy data |
| CN111061592A (en) * | 2019-11-22 | 2020-04-24 | 山东航天电子技术研究所 | Universal Nand Flash bit reversal error correction method |
-
2020
- 2020-07-03 CN CN202010630517.4A patent/CN111813591B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080168320A1 (en) * | 2007-01-05 | 2008-07-10 | California Institute Of Technology | Codes For Limited Magnitude Asymetric Errors In Flash Memories |
| CN103269230A (en) * | 2013-05-28 | 2013-08-28 | 中国科学院自动化研究所 | Fault-tolerant system and method for adjusting error correcting codes adaptively |
| CN107562563A (en) * | 2016-07-01 | 2018-01-09 | 龙芯中科技术有限公司 | Nand Flash control methods and device |
| CN106776104A (en) * | 2016-11-11 | 2017-05-31 | 大唐微电子技术有限公司 | A kind of method of Nand Flash controllers and terminal and control Nand Flash |
| CN106685431A (en) * | 2016-12-05 | 2017-05-17 | 华南理工大学 | LDPC soft information decoding method and coder-decoder based on Nand Flash |
| CN107590021A (en) * | 2017-08-22 | 2018-01-16 | 华中科技大学 | A kind of coding and decoding device and coding and decoding method for reducing the flash memory bit error rate |
| CN108845890A (en) * | 2018-05-07 | 2018-11-20 | 西安电子科技大学 | Data verification method based on Nand flash storage array |
| US20200004627A1 (en) * | 2018-06-28 | 2020-01-02 | Western Digital Technologies, Inc. | Error correction decoding with redundancy data |
| CN111061592A (en) * | 2019-11-22 | 2020-04-24 | 山东航天电子技术研究所 | Universal Nand Flash bit reversal error correction method |
Non-Patent Citations (2)
| Title |
|---|
| 周懿: "面向Nand Flash自适应纠错码方案研究与设计", 计算机工程与设计, pages 289 - 293 * |
| 金令旭等: "一种降低NAND Flash滞留错误的纠错方案", 通信技术, pages 141 - 145 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115562902A (en) * | 2022-01-11 | 2023-01-03 | 荣耀终端有限公司 | Storage area coding method and device and related equipment |
| CN116521432A (en) * | 2023-04-06 | 2023-08-01 | 珠海妙存科技有限公司 | Method for improving reliability of flash memory, controller and computer storage medium |
| CN116521432B (en) * | 2023-04-06 | 2024-01-09 | 珠海妙存科技有限公司 | Method for improving reliability of flash memory, controller and computer storage medium |
| CN116467131A (en) * | 2023-06-19 | 2023-07-21 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
| CN116467131B (en) * | 2023-06-19 | 2023-08-25 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111813591B (en) | 2023-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8751726B2 (en) | System and methods employing mock thresholds to generate actual reading thresholds in flash memory devices | |
| US10521292B2 (en) | Error correction code unit, self-test method and associated controller applied to flash memory device for generating soft information | |
| US8386860B2 (en) | Methods of calculating compensation voltage and adjusting threshold voltage and memory apparatus and controller | |
| US8429501B2 (en) | Memory storage device, memory controller thereof, and method thereof for generating log likelihood ratio | |
| US9257204B2 (en) | Read voltage setting method, and control circuit, and memory storage apparatus using the same | |
| CN111813591B (en) | Data error correction method and device of Nand Flash, electronic equipment and storage medium | |
| JP2016177860A (en) | Reading level grouping for increased flash performance | |
| CN109164978B (en) | Flash memory management method, flash memory storage device and computer readable storage medium | |
| CN111192620A (en) | Method for optimizing NAND Flash read reference voltage in SSD | |
| CN114639436A (en) | Flash memory chip data reading method | |
| CN112331249A (en) | Method and device for predicting service life of storage device, terminal equipment and storage medium | |
| CN107146638A (en) | Interpretation method, internal storing memory and memory control circuit unit | |
| CN114968837A (en) | Data compression method and flash memory device | |
| CN107331420A (en) | Coding/decoding method, memory storage apparatus and memorizer control circuit unit | |
| CN104679441A (en) | Time estimation method, memory storage device and memory control circuit unit | |
| CN115509799B (en) | Memory reading optimization method based on combination of copy and LDPC hybrid decoding | |
| CN115509798B (en) | Memory reading optimization method combining refreshing, copy and LDPC hybrid decoding | |
| CN109783001B (en) | Data encoding method, data decoding method, and storage controller | |
| TWI751620B (en) | Memory control method, memory storage device and memory control circuit unit | |
| CN102436842A (en) | Memory storage device, memory controller and method for generating log likelihood ratio | |
| CN111858137B (en) | Read level applying method for original bit error rate sensing | |
| CN113342569B (en) | Equal-length coding and decoding method for eliminating unreliable state of flash memory cell | |
| Li et al. | Data archiving in 1x-nm NAND flash memories: Enabling long-term storage using rank modulation and scrubbing | |
| CN116364163B (en) | Error correction method and system based on NAND flash memory controller | |
| CN117608501B (en) | Voltage adjustment method, memory storage device and memory control circuit unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |