CN102831932B - Method for reading data, Memory Controller and memorizer memory devices - Google Patents
Method for reading data, Memory Controller and memorizer memory devices Download PDFInfo
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Abstract
A kind of method for reading data, Memory Controller and memorizer memory devices, method for reading data is for having the type nonvolatile module of multiple physical blocks.Each physical blocks has multiple physical page.Method for reading data comprises the steps.Splitting each physical page is multiple bit Data districts.In each physical page, at least one bit Data district has different data lengths from other bit Data districts.Write data are to bit Data district.The data of each meta-data region are a corresponding error-correcting code frame.Data are read, because its data length is shorter therefore can increase the error correction capability of data and being read of guaranteeing that data can be correct from the error-correcting code frame in this at least one bit Data district.And then, obtain an error bit metamessage according to read data.According to error bit metamessage adjustment log-likelihood ratio question blank or threshold value voltage.
Description
Technical field
The present invention relates to a kind of accumulator system, particularly relate to a kind of method for reading data with preferably wrong bit calibration capability, and use Memory Controller and the memorizer memory devices of the method.
Background technology
Current flash memory is mainly divided into two kinds, is respectively anti-or flash memory (NORFlashMemory) and anti-and flash memory (NANDFlashMemory).Wherein, anti-and flash memory also exists two kinds of different storage modes, i.e. multilayered memory unit (Multi-LevelCell, MLC) and individual layer storage unit (Single-LevelCell, SLC).Individual layer storage unit stores 1 data bit element in each storage unit, and multilayered memory unit then can store the data bit element of more than 2 in each storage unit.
Generally speaking, the memory cell array (memorycellarray) strung by data bit element line (BitLine) and character line (WordLine), it is in reading or when writing data to the storage unit of specifying, all the other non-designated storage unit then can be interfered (disturb), and then change the critical voltage of these storage unit write.In addition, idle, storer leaks electricity or repeatedly uses (EraseorProgram) and cause the situations such as abrasion (Wear) for a long time, and the critical voltage that storage unit also can be made to write changes.Now, write data will be caused to make a mistake when reading.
On the other hand, memorizer memory devices can need mistake in calibration capability, and preferably error correction techniques is (such as, low density parity check code (LowDensityParityCheckCode, LDPCcode)) error-correcting routine is carried out to data.Memorizer memory devices obtains according to the question blank stored by it log-likelihood ratio (LogLikelihoodRatio, LLR) that Soft Inform ation (SoftInformation) corresponds to, and then carries out the action of error correction again with LDPC code.But, type nonvolatile in memorizer memory devices can change its error property along with the increase of its storage number (erase-programtimes), therefore to obtain best log-likelihood ratio, then constantly must add up the error property of type nonvolatile, this measure will cause sizable burden to system.
Summary of the invention
In view of this, the invention provides a kind of method for reading data, it has preferably wrong bit calibration capability, and optionally can adjust the threshold value voltage of log-likelihood ratio question blank or storage unit according to acquired error bit metamessage.
The invention provides a kind of Memory Controller, it has preferably wrong bit calibration capability, and optionally can adjust the threshold value voltage of log-likelihood ratio question blank or storage unit according to acquired error bit metamessage.
The invention provides a kind of memorizer memory devices, it has preferably wrong bit calibration capability, and optionally can adjust the threshold value voltage of log-likelihood ratio question blank or storage unit according to acquired error bit metamessage.
The invention provides a kind of method for reading data, for a type nonvolatile module.Type nonvolatile module has multiple physical blocks, and each physical blocks has multiple physical page.Method for reading data comprises the steps.Splitting each physical page is multiple bit Data districts.In the middle of each physical page, at least one bit Data district has different data lengths compared to other bit Data districts.Write data to bit Data district, wherein the corresponding error-correcting code frame of each meta-data region, and in the middle of error-correcting code frame, the error-correcting code frame corresponding at least one bit Data district is have shorter data length.Self-alignment meta-data region reads data.A data processor is performed to obtain an error bit metamessage according to read data.According to error bit metamessage, adjust at least one threshold value voltage of a log-likelihood ratio question blank or storage unit.
The invention provides a kind of Memory Controller, comprise a host system interface, a memory interface, a memory management circuitry and a log-likelihood ratio estimation circuit.Host system interface couples a host computer system.Memory interface couples a type nonvolatile module.Type nonvolatile module has multiple physical blocks, and each physical blocks has multiple physical page.Memory management circuitry is coupled to host system interface and memory interface.It is multiple bit Data districts that memory management circuitry splits each physical page; Write data to bit Data district; Self-alignment meta-data region reads data; A data processor is performed according to read data; And according to error bit metamessage, at least one threshold value voltage of adjustment storage unit.Log-likelihood ratio estimation circuit coupled memory management circuit.Log-likelihood ratio estimation circuit adjusts a log-likelihood ratio question blank according to error bit metamessage.In the middle of each physical page, at least one bit Data district has different data lengths compared to other bit Data districts.And the corresponding error-correcting code frame of each meta-data region, in the middle of error-correcting code frame, the error-correcting code frame in corresponding at least one bit Data district is have shorter data length.
The invention provides a kind of memorizer memory devices, comprise a connector, a type nonvolatile module and a Memory Controller.Connector couples a host computer system.Type nonvolatile module has multiple physical blocks, and each physical blocks has multiple physical page.Memory Controller is coupled to type nonvolatile module and connector.It is multiple bit Data districts that Memory Controller splits each physical page; Write data to bit Data district; Self-alignment meta-data region reads data; A data processor is performed according to read data; And according to error bit metamessage, adjust at least one threshold value voltage of a log-likelihood ratio question blank or storage unit.In the middle of each physical page, a bit Data district at least wherein has different data lengths compared to other bit Data districts, and the corresponding error-correcting code frame of each meta-data region, in the middle of error-correcting code frame, the error-correcting code frame corresponding at least one bit Data district is have shorter data length.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is the host computer system using type nonvolatile storage device according to the embodiment of the present invention.
Figure 1B is the schematic diagram of computing machine, input/output device and memorizer memory devices according to exemplary embodiment of the present invention.
Fig. 1 C is the schematic diagram of host computer system according to another exemplary embodiment of the present invention and memorizer memory devices.
Fig. 2 is the summary block scheme of the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary block scheme of the Memory Controller according to exemplary embodiment of the present invention.
Fig. 4 is the configuration diagram in the bit Data district of type nonvolatile module physical page according to exemplary embodiment of the present invention.
Fig. 5 is the summary block scheme of the memorizer memory devices according to exemplary embodiment of the present invention.
Fig. 6 is the process flow diagram of the method for adjustment threshold value voltage according to exemplary embodiment of the present invention.
Fig. 7 is the summary block scheme of the memorizer memory devices according to exemplary embodiment of the present invention.
Fig. 8 is the schematic diagram that storing state according to exemplary embodiment of the present invention and bit Data read voltage.
Fig. 9 is the various corresponding relation that the storing state storing mistake may occur in the exemplary embodiment shown in Fig. 8.
Figure 10 is the process flow diagram of the method for adjustment log-likelihood ratio according to exemplary embodiment of the present invention.
Figure 11 is the process flow diagram of the method for reading data according to exemplary embodiment of the present invention.
Reference numeral:
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: Portable disk
1214: memory card
1216: solid state hard disc
1310: digital camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104,104 ': Memory Controller
106: type nonvolatile module
202,202 ': memory management circuitry
204: host interface
206: memory interface
252: storage element
254: electric power management circuit
256: bug check and correcting circuit
502: memory cell array
504: character line control circuit
506: bit line control circuit
508: column decoder
510: data input/output (i/o) buffer
512: control circuit
702: log-likelihood ratio estimation circuit
704: log-likelihood ratio question blank
VA: the first bit Data reads voltage
VB: second bit digital independent voltage
VC: the three bit Data reads voltage
VD: the nibble digital independent voltage
VE: the five bit Data reads voltage
VF: the six bit Data reads voltage
VG: the seven bit Data reads voltage
S602, S604, S606, S608, S610: the method step of adjustment threshold value voltage
S1010, S1020, S1030, S1040, S1050: the method step of adjustment log-likelihood ratio
S1100, S1102, S1104, S1106, S1108: the step of method for reading data
Embodiment
In this announcement, there is in each physical page at least one data bit element district and from other data bit element districts, there is different data lengths.Corresponding to the error-correcting code frame that data bit element district data length is shorter, there is preferably wrong bit calibration capability.Therefore, when memorizer memory devices carries out error-correcting routine to read data, can guarantee that these data can be corrected effectively.And then memorizer memory devices according to obtained error bit metamessage, can optionally adjust the threshold value voltage of log-likelihood ratio question blank or storage unit.Below will be described in more detail the present invention with several exemplary embodiment and accompanying drawing.
Figure 1A is the host computer system using type nonvolatile storage device according to the embodiment of the present invention.
Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (randomaccessmemory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
Type nonvolatile storage device 100 is coupled by data transmission interface 1110 other elements with host computer system 1000 in embodiments of the present invention.Data can be write to type nonvolatile storage device 100 by microprocessor 1102, random access memory 1104 with the process of input/output device 1106 or read data from type nonvolatile storage device 100.Such as, type nonvolatile storage device 100 can be Portable disk 1212, memory card 1214 or solid state hard disc (SolidStateDrive, SSD) 1216 as shown in Figure 1B.
Generally speaking, main frame 1000 can be can any system of storage data substantially.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then its SD card 1312 used, mmc card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multimedia card (EmbeddedMMC, eMMC).It is worth mentioning that, embedded multimedia card is directly coupled on the substrate of host computer system.
Fig. 2 is the summary block scheme of the memorizer memory devices shown in Figure 1A.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and type nonvolatile module 106.
In this exemplary embodiment, connector 102 is compatible to advanced annex (SerialAdvancedTechnologyAttachment, the SATA) standard of serial.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be meet Institute of Electrical and Electric Engineers (InstituteofElectricalandElectronicEngineers, IEEE) 1394 standards, parallel advanced annex (ParallelAdvancedTechnologyAttachment, PATA) standard, high-speed peripheral component connecting interface (PeripheralComponentInterconnectExpress, PCIExpress) standard, USB (universal serial bus) (UniversalSerialBus, USB) standard, safe digital (SecureDigital, SD) interface standard, memory stick (MemoryStick, MS) interface standard, Multi Media Card (MultiMediaCard, MMC) interface standard, non-volatile (the CompactFlash of small-sized duplicative, CF) interface standard, integrated form drives electrical interface (IntegratedDeviceElectronics, IDE) standard or other standards be applicable to.
Memory Controller 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in type nonvolatile module 106 data write, read and the running such as to erase.
Type nonvolatile module 106 is coupled to Memory Controller 104, and in order to store the data that host computer system 1000 writes.In this exemplary embodiment, type nonvolatile module 106 is multi-level cell memory (MultiLevelCell, MLC) NAND flash memory module.But, the present invention is not limited thereto, type nonvolatile module 106 also single-order storage unit (SingleLevelCell, SLC) NAND flash memory module, other type nonvolatile modules or other there is the memory module of identical characteristics.
Fig. 3 is the summary block scheme of the Memory Controller according to exemplary embodiment of the present invention.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering order, and when memorizer memory devices 100 operates, this little steering order can be performed to carry out data write, read and the running such as to erase.
In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memorizer memory devices 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as to erase.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of type nonvolatile module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has driving code, and when Memory Controller 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in type nonvolatile module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the running such as to erase.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 a hardware pattern can also carry out implementation.
Host interface 204 is coupled to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 can also be compatible to PATA standard, IEEE1394 standard, PCIExpress standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 206 is coupled to memory management circuitry 202 and in order to access type nonvolatile module 106.That is, the data for writing to type nonvolatile module 106 can be converted to the receptible form of type nonvolatile module 106 via memory interface 206.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises a storage element 252.Storage element 252 be coupled to memory management circuitry 202 can in order to stocking system data, temporary come from the data and instruction of host computer system 1000 or come from the data of type nonvolatile module 106.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is coupled to memory management circuitry 202 and in order to the power supply of control store storage device 100.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 are coupled to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 256 can be that the corresponding data that this writes instruction produce corresponding error-correcting code (ErrorCheckingandCorrectingCode, ECCCode), and memory management circuitry 202 data of this write instruction corresponding can be write in type nonvolatile module 106 with corresponding error-correcting code.Afterwards, can read error-correcting code corresponding to these data when memory management circuitry 202 reads data from type nonvolatile module 106, and bug check and correcting circuit 256 can according to this error-correcting code to read data execution error inspection and correction programs simultaneously.
What deserves to be explained is, in one example of the present invention embodiment, each physical page bit Data district at least wherein of type nonvolatile module has different data lengths from other bit Data districts.Corresponding to the error-correcting code frame that bit Data district data length is shorter, there is preferably wrong bit calibration capability.Therefore, when bug check and correcting circuit 256 carry out error-correcting routine to read data, can guarantee that these data effectively can be examined and correct.And then memory management circuitry 202 according to obtained error bit metamessage, can optionally adjust the threshold value voltage of log-likelihood ratio question blank or storage unit.
Generally speaking, take length as the physical page of 8KB be example, if this physical page is on average divided into 8 bit Data districts by memory management circuitry 202, then the storable data length of each meta-data region is about 1KB.But, in such cases, even if the error-correcting code frame of collocation 42 bit Data BCH code (Bose, Ray-Chaudhuri, Hocquenghemcode), the decoding that its calibration capability (correctioncapability) still cannot reach 10-14 bit error rate (biterrorrate, BER) exports (decoderoutput).
Fig. 4 is the configuration diagram of the bit district data of type nonvolatile module physical page according to exemplary embodiment of the present invention.
Please refer to Fig. 4, the memory management circuitry 202 of the present embodiment, when splitting each physical page, is divided into the bit Data district with different data lengths.Particularly, the shorter bit Data district of data length is configured at the initial position of each physical page, and the error-correcting code frame wherein corresponding to this shorter bit Data district of data length has preferably wrong bit calibration capability.
For example, in the present embodiment, each physical page is divided into 6 bit Data districts by memory management circuitry 202.In the middle of these bit Data districts, the bit Data section length of initial position is 0.5KB, and other bit Data section length is then 1.5KB.At this, arrange in pairs or groups each meta-data region person, is the error-correcting code frame of 56 bit Data BCH code.Therefore, be the bit Data district of 0.5KB for length, the error-correcting code frame of 56 bit Data BCH code has preferably wrong bit calibration capability.The error-correcting code frame in the bit Data district that corresponding data length is shorter can be referred to as " leader's error-correcting code frame " (leadingECCframe).
For the bit Data district that length is shorter, leader's error-correcting code frame of 56 bit Data BCH code can provide 10
-14the decoding of bit error rate exports.And then when bug check and the correcting circuit 256 bit Data district shorter to this length read, its data read, when carrying out error-correcting routine, can guarantee that these data more effectively can be examined and correct.Therefore, bug check and correcting circuit 256 can provide suitable error bit metamessage, in order to memory management circuitry 202 according to obtained error bit metamessage, optionally adjust the threshold value voltage of its log-likelihood ratio question blank or storage unit.
Only it should be noted, though the shorter bit Data district of the data length of the present embodiment is configured at the initial position of each physical page, the present invention is not limited to this.In other embodiments, the bit Data district that data length is shorter and leader's error-correcting code frame also configurable in any two length be 1.5KB bit Data district between.In addition, the bit Data district number of each physical page of the present invention and length are also not limited to person illustrated in the present embodiment.
After memory management circuitry 202 obtains suitable error bit metamessage, namely optionally adjust the threshold value voltage of its log-likelihood ratio question blank or storage unit.The threshold value voltage how adjusting its log-likelihood ratio question blank and storage unit will be described in more detail below with different exemplary embodiment and accompanying drawing.
Fig. 5 is the summary block scheme of the memorizer memory devices according to exemplary embodiment of the present invention.
Please refer to Fig. 3 and Fig. 5, memorizer memory devices 100 can use together with host computer system 1000, data can be write to memorizer memory devices 100 to make host computer system 1000 or read data from memorizer memory devices 100.
Memory Controller 104 comprises memory management circuitry 202, host interface 204, memory interface 206, storage element 252, electric power management circuit 254 and bug check and correcting circuit 256.Wherein the structure and fuction of Memory Controller 104 has described as above, in this not repeated description.
The data that memory module 106 writes in order to store host computer system 1000.In the present embodiment, memory module 106 is such as MLC flash memory module, and it comprises memory cell array 502, character line control circuit 504, data bit element line control circuit 506, column decoder (columndecoder) 508, data input/output (i/o) buffer 510 and control circuit 512.
Memory cell array 502 comprise in order to storage data multiple storage unit (not shown), connect many data bit line (not shown) of this little storage unit, many character lines and common source line (not shown).Storage unit is configured on the point of crossing of data bit element line and character line with array way.When receiving write instruction from Memory Controller 104 or reading data, control circuit 512 meeting control character line control circuit 504, data bit element line control circuit 506, column decoder 508, data input/output (i/o) buffer 510 writes data and reads data to memory array 502 or from memory array 502, wherein character line control circuit 504 is in order to control the character line voltage being imparted to character line, data bit element line control circuit 506 is in order to control data bit line, column decoder 508 according to the decoding column address in instruction to select corresponding data bit element line, and data input/output (i/o) buffer 510 is in order to temporal data.
As previously mentioned in the present embodiment, memory module 106 is MLC flash memory, and it uses multiple floating voltage to represent the data of multidigit metadata (bits).Specifically, each storage unit of memory cell array 502 has multiple storing state, and this little storing state reads voltage with multiple bit Data to distinguish.In the 3rd exemplary embodiment, control circuit 512 also can control character line control circuit 504, data bit element line control circuit 506, column decoder 508 with data input/output (i/o) buffer 510 to perform write and the reading of data.
Fig. 6 is the process flow diagram of the method for adjustment threshold value voltage according to exemplary embodiment of the present invention.
Please refer to Fig. 6, in step S602, memory management circuitry 202 writes the bit Data district of data to memory module 106.Then, in step s 604, memory management circuitry 202 reads data from the bit Data district of memory module 106.These data are the wherein a kind of storing states corresponding to memory module 106, and the voltage range of two storing states is distinguished by a threshold value voltage.
In the present embodiment, when memory management circuitry 202 detects that memory module 106 unrecoverable error occurs and mistakes, memory management circuitry 202 just can control bug check and correcting circuit 256 starts to perform the method adjusting threshold value voltage.Such as, bug check and correcting circuit 256 utilize error-correcting code frame execution error correction program to obtain wrong bit number.And memory management circuitry 202 can when occurred wrong bit number exceeds first preset value, there is unrecoverable error in determining storage device module 106.
In the present embodiment, memory management circuitry 202 can decide for carrying out the data of testing for the storing state of memory module 106, namely these data is write to memory module 106 and reads out and compare, use adjustment threshold value voltage.And in other embodiments, general data can also be write to adjust threshold value voltage.That is, write data, when data are write to memory module 106, can be recorded by memory management circuitry 202, afterwards when memory module 106 reads data, and can the comparison data read and the data write.
Afterwards, in step S606, memory management circuitry 202 compares each read data write data corresponding to it respectively and obtains error bit metamessage.In other words, memory management circuitry 202 performs a data processor according to read data, to obtain error bit metamessage.Such as, when memory management circuitry 202 writes data to memory module 106, write data can be recorded in advance.Afterwards, the data of the data read out from memory module 106 and its precedence record just can be compared by memory management circuitry 202, and obtain error bit metamessage.At this, error bit metamessage comprises mistake bit number and error bit metadata model (such as, can only store 1 bit Data with storage unit, the storing state of the data of reading becomes 1 from 0, or becomes 0 from 1).In another exemplary embodiment of the present invention, above-mentioned data processor also can be an error-correcting routine.Now, memory management circuitry 202 completes Data correction by error-correcting code, and then obtains error bit metamessage.
After calculating error bit metamessage, as shown in step S608, memory management circuitry 202, again according to error bit metamessage, calculates the bucking voltage of threshold value voltage.In step S610, memory management circuitry 202 adjusts threshold value voltage by bucking voltage.
What deserves to be explained is, physical page, when splitting each physical page, is divided into the bit Data district with different data lengths by the memory management circuitry 202 of the present embodiment.Particularly, the shorter bit Data district of data length is configured at the initial position of each physical page, and the error-correcting code frame wherein corresponding to this shorter bit Data district of data length has preferably wrong bit calibration capability.Therefore, bug check and correcting circuit 256 can provide suitable error bit metamessage, in order to memory management circuitry 202 according to obtained error bit metamessage, optionally adjust the threshold value voltage of its log-likelihood ratio question blank or storage unit.
The data of above-mentioned write comprise many bit Data.First storing state adjacent for voltage range and the second storing state, memory management circuitry 202 can be added up these bit Data and is the first storing state when writing and be the first wrong bit number of the second storing state when reading.Further, memory management circuitry 202 can be added up these bit Data and is the second storing state when writing and is the second wrong bit number of the first storing state when reading.At this, the voltage range of the first storing state is less than the voltage range of the second storing state, and memory management circuitry 202 calculation compensation voltage is according to following formula:
Wherein, x represents bucking voltage, and g represents constant, and error2 represents the second wrong bit number, and error1 represents the first wrong bit number.
And after calculating bucking voltage x, then threshold value voltage can be added bucking voltage and obtain the threshold value voltage after adjustment.
To store the memory module 106 of 2 bit Data in each storage unit, when the wrong bit number that wherein a physical page produces be greater than the first preset value or wrong bit number exceed the error correction capability of bug check and correcting circuit 256 time, memory management circuitry 202 first can judge that this physical page is quick physical page or physical page at a slow speed.When this physical page is quick physical page, memory management circuitry 202 can read wherein one the data of quick physical page, and the data that read of comparison and raw data, with the bit Data position that locates errors.Afterwards, then from error bit metadata location corresponding bit Data is read.Memory management circuitry 202 can according to the bit Data misjudgment bit Data pattern read.Such as, the bit Data of write is the bit Data that the first storing state reads out is the second storing state, or the bit Data of write is the second storing state, and the bit Data read out is the first storing state (voltage range of the first storing state and the second storing state is adjacent).Accordingly, it is the first wrong bit number that the first storing state is mistaken for the second storing state that memory management circuitry 202 can add up bit Data in quick physical page, and statistics bit Data is the second wrong bit number that the second storing state judges to the first storing state by accident.On the other hand, when this physical page be at a slow speed physical page time, memory management circuitry 202 reads out bit Data corresponding to physical page at a slow speed from the error bit metadata location of physical page at a slow speed.Further, memory management circuitry 202, according to the error bit metadata location of physical page at a slow speed, reads the bit Data that quick physical page is corresponding.By this, memory management circuitry 202 according to above-mentioned bit Data, can calculate the first wrong bit number and the second wrong bit number of physical page at a slow speed.
In the present embodiment, after calculating error bit metamessage, in order to the data after making calculating have higher confidence level, whether memory management circuitry 202 also can be greater than one second preset value, to perform the step of offset value calculation again when wrong bit number is greater than the second preset value by the wrong bit number in first misjudgment order information.
Wherein about adjustment threshold value voltage method further illustrate that enumeration is in Taiwan application case 099111612 relevant paragraph, it includes the part becoming announcement herein in because quoting.
In the present invention, memorizer memory devices, except according to error bit metamessage, outside the threshold value voltage of adjustment storage unit, also can select adjustment log-likelihood ratio question blank.
Fig. 7 is the summary block scheme of the memorizer memory devices according to exemplary embodiment of the present invention.Please refer to Fig. 7, the Memory Controller 104 ' of the present embodiment also comprises a log-likelihood ratio estimation circuit 702.Memory management circuitry 202 ' comprises a log-likelihood ratio question blank 704.
Log-likelihood ratio estimation circuit 702 coupled memory management circuit 202 ' and bug check and correcting circuit 256.Log-likelihood ratio estimation circuit 702 is the log-likelihood ratio Regulation mechanism realizing this exemplary embodiment.The Detailed Operation mode of this log-likelihood ratio Regulation mechanism will explain in following cooperation accompanying drawing again.In an exemplary embodiment, log-likelihood ratio estimation circuit 702 is such as become several steering order with hardware pattern implementation.In other exemplary embodiment, log-likelihood ratio estimation circuit 702 also can be the steering order that firmware pattern implementation becomes or the steering order become with procedure code pattern implementation.
Fig. 8 is the schematic diagram that storing state according to exemplary embodiment of the present invention and bit Data read voltage.In this exemplary embodiment, type nonvolatile module 106 is 8 rank storage unit NAND flash memories, as shown in Figure 8, floating voltage system in each storage unit reads voltage VA according to the first bit Data, second bit digital independent voltage VB, 3rd bit Data reads voltage VC, nibble digital independent voltage VD, 5th bit Data reads voltage VE, 6th bit Data reads voltage VF and the 7th bit Data reads voltage VG and divides into 8 kinds of storing states, " 111 " respectively, " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ".Each storing state comprises least significant bit (LSB) metadata (LeastSignificantBit, LSB), middle significance bit metadata (CenterSignificantBit, CSB), and these 3 bit Data of highest significant position metadata (MostSignificantBit, MSB).For example, the 1st bit Data that each storing state is counted from left side in this exemplary embodiment is LSB, and the 2nd bit Data counted from left side is CSB, and the count from left side the 3rd bit Data is MSB.Accordingly, each storage unit can store 3 bit Data, therefore the storage unit on same character line can form the storage area of 3 physical page (that is, lower physical page, middle physical page and upper physical page).That is, the LSB of each storage unit is corresponding lower physical page, the CSB of each storage unit is physical page in correspondence, and the MSB of each storage unit is corresponding upper physical page.In addition, several physical page can form a physical blocks, and physical blocks is the least unit performing running of erasing.That is, each physical blocks contain minimal amount in the lump by the storage unit of erasing.In this exemplary embodiment, the storing state order of these 8 kinds of storing states is sequentially " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 ", " 011 ".Should be noted that, storing state order may be different according to the design of Ge Jia type nonvolatile chip manufacturer, do not limited at this.
Fig. 9 is the various corresponding relation that the storing state storing mistake may occur in the exemplary embodiment shown in Fig. 8.In fig .9, the first storing state of data is read in the storing state representative being indicated in the right of " → ", and the storing state being indicated in the left of " → " is the second storing state reading data.
Please refer to Fig. 8 and Fig. 9, when the first storing state reading data is " 000 ", the 2nd possible storing state is " 010 ", " 001 ".When the first storing state reading data is " 001 ", the second possible storing state is " 101 ", " 000 ".And when the first storing state reading data is " 010 ", the second possible storing state is " 000 ", " 011 ", by that analogy.
Being denoted as " * " part in fig .9, reading data when being read to should the first storing state if represent, then storing mistake, to occur in the probability of this bit Data very little.Such as, when the first storing state reading data is " 100 ", if store mistake to occur in LSB, represent that the second storing state reading data should be " 000 ".But because this exemplary embodiment has supposed that storing mistake only can occur between the adjacent storing state of storing state order, and contrast the known storing state of Fig. 8 " 000 " and storing state " 100 " and non-conterminous, that event is when the first storing state of reading data is " 100 ", store mistake and occur in suitable low of the probability of LSB, do not have in this hypothesis the situation that the second storing state reading data is " 000 ", namely LSB is that the log-likelihood ratio of 0 is for negative infinitely great.
In an exemplary embodiment, be " 000 " when log-likelihood ratio estimation circuit 702 obtains the first storing state reading data for " 001 " and the second storing state, log-likelihood ratio estimation circuit 702 just can be added up in those data stored by storage unit of sum by mistake of statistics, obtain when data are written into and be storing state " 000 " but the storage mistake sum that to be storing state when being read be " 001 ", and calculate a log-likelihood ratio with above-mentioned formula (1).But, if the first storing state reading data is " 001 " and the second storing state is " 100 ", because first, second storing state is non-conterminous in the storing state order, therefore log-likelihood ratio estimation circuit 702 can read the value of bit Data according to read data one, is set as by log-likelihood ratio positive infinitely great or negative infinitely great.Corresponding relation shown in Fig. 9 can be used to calculate the log-likelihood ratio that the storage mistake reading data occurs in LSB, CSB or MSB.
Figure 10 is the process flow diagram of the method for adjustment log-likelihood ratio according to exemplary embodiment of the present invention.
After memorizer memory devices 100 receives the reading command that host computer system 1000 assigns, first as shown in step S1010, memory management circuitry 202 ' instruction memory module 106 in Memory Controller 104 ' uses bit Data to read voltage from storage unit, obtains reading data, and this reads corresponding first storing state of data.
Then, in step S1020, the bug check in Memory Controller 104 ' and correcting circuit 256 perform an error-correcting routine and read data second storing state corresponding when writing memory module 106 to reading data to obtain.
Next as shown in step S1030, log-likelihood ratio estimation circuit 702 in Memory Controller 104 ' in the storing state meeting error statistics sum, obtain write time be the second storing state and read time be the first storing state one store mistake sum.
In step S1040, log-likelihood ratio estimation circuit 702 is according to the storing state quantity of error statistics sum, storing state, and store mistake sum execution one logarithm operation, to produce the log-likelihood ratio reading data, wherein calculating this log-likelihood ratio is according to following formula:
Wherein LLR_c represents log-likelihood ratio, and N represents error statistics sum, S represents storing state quantity, and W represents storage mistake sum.
Afterwards, in step S1050, log-likelihood ratio estimation circuit 702 can directly utilize the log-likelihood ratio of estimation gained to upgrade the log-likelihood ratio question blank 704 in memory management circuitry 202 '.That is, utilize the log-likelihood ratio of this estimation gained to replace in log-likelihood ratio question blank 704 the current logarithmic likelihood ratio read corresponding to data.
Wherein further illustrate that enumeration is in Taiwan application case 099131626 relevant paragraph about what adjust the method for log-likelihood ratio, it includes the part becoming announcement herein in because quoting.
Figure 11 is the process flow diagram of the method for reading data according to exemplary embodiment of the present invention.
Referring to Fig. 2 and Figure 11, the method for reading data of the present embodiment is such as applicable to a type nonvolatile module, and it comprises the steps.First, in step S1100, each physical page of segmentation memory module 106 is multiple bit Data districts, and the bit Data section length of the physical page wherein after segmentation and quantity are as shown in Figure 4.Then, in step S1102, the bit Data district of data to these physical page is write.Afterwards, in step S1104, be certainly written in these bit Data districts of data and read data.Then, in step S1106, a data processor is performed to obtain an error bit metamessage according to read data.Wherein, this data processor comprises these data that comparison is read and these data write.Or this data processor also can be an error-correcting routine.Then, in step S1108, according to error bit metamessage, the threshold value voltage of adjustment log-likelihood ratio question blank or storage unit.
In addition, the method for reading data of embodiments of the invention can obtain enough teachings, suggestion and implementation by the describing of Fig. 1 to Figure 10 embodiment, and therefore repeats no more.
In sum, in exemplary embodiment of the present invention, corresponding to the error-correcting code frame that bit Data district data length is shorter, there is preferably wrong bit calibration capability.Therefore, when memorizer memory devices carries out error-correcting routine to read data, can guarantee that these data effectively can be examined and correct.And then memorizer memory devices according to obtained error bit metamessage, can optionally adjust the threshold value voltage of log-likelihood ratio question blank or storage unit.
Although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention, any person of an ordinary skill in the technical field, when doing a little change and retouching, and does not depart from the spirit and scope of the present invention.
Claims (21)
1. a method for reading data, for a type nonvolatile module, this type nonvolatile module has multiple physical blocks, and each those physical blocks has multiple physical page, and this method for reading data comprises:
Splitting each those physical page is multiple bit Data districts, and wherein in the middle of each those physical page, at least one bit Data district has different data lengths compared to other bit Data districts;
Write data to those bit Data districts, wherein the corresponding error-correcting code frame in each those bit Data district, and in the middle of those error-correcting code frames, the error-correcting code frame corresponding to this at least one bit Data district is have shorter data length;
This data are read from those bit Data districts;
A data processor is performed to obtain an error bit metamessage according to these read data; And
According to this error bit metamessage, adjust a log-likelihood ratio question blank or at least one threshold value voltage.
2. method for reading data according to claim 1, the step wherein splitting each those physical page comprises:
This at least one bit Data district is configured at the initial position of each those physical page,
The error-correcting code frame wherein corresponding to this at least one bit Data district has preferably wrong bit calibration capability.
3. method for reading data according to claim 1, the step wherein adjusting this threshold value voltage comprises:
The bucking voltage of this threshold value voltage is calculated according to this error bit metamessage; And
This at least one threshold value voltage is adjusted by this bucking voltage.
4. method for reading data according to claim 3, wherein perform this data processor according to these read data and comprise comparison these data read and these data write to obtain one first wrong bit number and one second wrong bit number with the step obtaining this error bit metamessage, wherein calculating this bucking voltage is according to following formula:
Wherein, x represents this bucking voltage, and g represents a constant, and error1 represents this first wrong bit number, and error2 represents this second wrong bit number.
5. method for reading data according to claim 1, wherein this type nonvolatile module has multiple storage unit and each those storage unit has multiple storing state, corresponding one first storing state of this data be read, wherein performs this data processor according to these read data and to comprise with the step obtaining this error bit metamessage and perform an error-correcting routine to obtain these data of reading one second storing state corresponding when writing to these read data.
6. method for reading data according to claim 5, the step wherein adjusting log-likelihood ratio question blank comprises:
Meet in those storing states of an error statistics sum read, obtain write time be this second storing state and read time be this first storing state one store mistake sum; And
According to a storing state quantity of this error statistics sum, those storing states, and this storage mistake sum performs a logarithm operation, and to produce a log-likelihood ratio of these data be read, wherein calculating this log-likelihood ratio is according to following formula:
Wherein LLR_c represents this log-likelihood ratio, and N represents this error statistics sum, S represents this storing state quantity, and W represents this storage mistake sum.
7. method for reading data according to claim 6, wherein this type nonvolatile module is configured at a memorizer memory devices, this memorizer memory devices comprises this log-likelihood ratio question blank, the current logarithmic likelihood ratio corresponding to these data that this log-likelihood ratio question blank record is read, the step wherein adjusting log-likelihood ratio question blank also comprises:
This log-likelihood ratio is utilized to replace this current log-likelihood ratio in this log-likelihood ratio question blank.
8. a Memory Controller, comprising:
One host system interface, couples a host computer system;
One memory interface, couples a type nonvolatile module, and this type nonvolatile module has multiple physical blocks, and each those physical blocks has multiple physical page;
One memory management circuitry, is coupled to this host system interface and this memory interface, and it is multiple bit Data districts that this memory management circuitry splits each those physical page; Write data to those bit Data districts; This data are read from those bit Data districts; A data processor is performed to obtain an error bit metamessage according to these read data; And according to this error bit metamessage, adjust at least one threshold value voltage; And
One log-likelihood ratio estimation circuit, couples this memory management circuitry, and this log-likelihood ratio estimation circuit adjusts a log-likelihood ratio question blank according to this error bit metamessage,
Wherein in the middle of each those physical page, at least one bit Data district has different data lengths compared to other bit Data districts, and the corresponding error-correcting code frame in each those bit Data district, in the middle of those error-correcting code frames, to should the error-correcting code frame at least one bit Data district be that there is shorter data length.
9. Memory Controller according to claim 8, wherein this shorter for data length at least one bit Data district is configured at the initial position of each this physical page by this memory management circuitry, and this error-correcting code frame wherein corresponding to this at least one bit Data district has preferably wrong bit calibration capability.
10. Memory Controller according to claim 8, wherein this memory management circuitry calculates the bucking voltage of this threshold value voltage according to this error bit metamessage, and adjusts this at least one threshold value voltage by this bucking voltage.
11. Memory Controllers according to claim 10, wherein this memory management circuitry perform this data processor be these data of reading of comparison with these data write to obtain one first wrong bit number and one second wrong bit number, wherein calculating this bucking voltage is according to following formula:
Wherein, x represents this bucking voltage, and g mono-represents constant, and error1 represents this first wrong bit number, and error2 represents this second wrong bit number.
12. Memory Controllers according to claim 8, wherein this type nonvolatile module has multiple storage unit and each those storage unit has multiple storing state, corresponding one first storing state of this data be read, wherein this memory management circuitry performs this data processor is perform an error-correcting routine to obtain these data of reading one second storing state corresponding when writing to these read data.
13. Memory Controllers according to claim 12, wherein this log-likelihood ratio estimation circuit meets in those storing states of an error statistics sum read, obtain write time be this second storing state and read time be this first storing state one store mistake sum, and a storing state quantity that is total according to these error statistics, those storing states, and this storage mistake sum performs a logarithm operation, to produce a log-likelihood ratio of these data be read, wherein calculating this log-likelihood ratio is according to following formula:
Wherein LLR_c represents this log-likelihood ratio, and N represents this error statistics sum, S represents this storing state quantity, and W represents this storage mistake sum.
14. Memory Controllers according to claim 13, wherein this memory management circuitry has this log-likelihood ratio question blank, the current logarithmic likelihood ratio corresponding to these data that this log-likelihood ratio question blank record is read, and this log-likelihood ratio estimation circuit utilizes this log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.
15. 1 kinds of memorizer memory devices, comprising:
A connector, couples a host computer system;
One type nonvolatile module, has multiple physical blocks, and each those physical blocks has multiple physical page; And
One Memory Controller, is coupled to this type nonvolatile module and this connector, and it is multiple bit Data districts that this Memory Controller splits each those physical page; Write data to those bit Data districts; This data are read from those bit Data districts; A data processor is performed according to these read data; And according to an error bit metamessage, adjust a log-likelihood ratio question blank or at least one threshold value voltage,
Wherein in the middle of each those physical page, at least one bit Data district has different data lengths compared to other bit Data districts, and the corresponding error-correcting code frame in each those bit Data district, in the middle of those error-correcting code frames, the error-correcting code frame corresponding to this at least one bit Data district is have shorter data length.
16. memorizer memory devices according to claim 15, wherein this at least one bit Data district is configured at the initial position of each those physical page by this Memory Controller, and wherein this error-correcting code frame in this at least one bit Data district has preferably wrong bit calibration capability.
17. memorizer memory devices according to claim 15, wherein this Memory Controller calculates the bucking voltage of this threshold value voltage according to this error bit metamessage, and adjusts this at least one threshold value voltage by this bucking voltage.
18. memorizer memory devices according to claim 17, wherein this Memory Controller perform this data processor be these data of reading of comparison with these data write to obtain one first wrong bit number and one second wrong bit number, wherein calculating this bucking voltage is according to following formula:
Wherein, x represents this bucking voltage, and g represents a constant, and error1 represents this first wrong bit number, and error2 represents this second wrong bit number.
19. memorizer memory devices according to claim 15, wherein this type nonvolatile module has multiple storage unit and each those storage unit has multiple storing state, corresponding one first storing state of this data be read, it is perform an error-correcting routine to obtain these data of reading one second storing state corresponding when writing to these read data that this Memory Controller performs this data processor.
20. memorizer memory devices according to claim 19, wherein this Memory Controller meets in those storing states of an error statistics sum read, obtain write time be this second storing state and read time be this first storing state one store mistake sum, and a storing state quantity that is total according to these error statistics, those storing states, and this storage mistake sum performs a logarithm operation, to produce a log-likelihood ratio of these data be read, wherein calculating this log-likelihood ratio is according to following formula:
Wherein LLR_c represents this log-likelihood ratio, and N represents this error statistics sum, S represents this storing state quantity, and W represents this storage mistake sum.
21. memorizer memory devices according to claim 20, wherein this Memory Controller has this log-likelihood ratio question blank, the current logarithmic likelihood ratio corresponding to these data that this log-likelihood ratio question blank record is read, and this Memory Controller utilizes this log-likelihood ratio to replace this current log-likelihood ratio in this log-likelihood ratio question blank.
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| US10783972B2 (en) * | 2018-08-02 | 2020-09-22 | SK Hynix Inc. | NAND flash memory with reconfigurable neighbor assisted LLR correction with downsampling and pipelining |
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