CN103219992A - Blind sampling clock data recovery circuit with filter shaping circuit - Google Patents
Blind sampling clock data recovery circuit with filter shaping circuit Download PDFInfo
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Abstract
The invention discloses a blind sampling clock data recovery circuit with a filter shaping circuit. The blind sampling clock data recovery circuit with the filter shaping circuit mainly solves an error code caused by distortion of a data stream in serial communication, and improves the accuracy of clock data recovery. The blind sampling clock data recovery circuit comprises a receiver (1), a data recovery circuit (2) and a phase-locked loop (3). The receiver (1) is composed of a parallel sampling module. The data recovery circuit (2) is composed of a synchronous adjustment circuit (21), the filter shaping circuit (22), a phase demodulation encoding circuit (23) and a control circuit (24), a data selection circuit (25). The phase-locked loop (3) is composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LP), a frequency divider (/M) and a multi-phase voltage controlled oscillator (VCO). The filter shaping circuit is additionally arranged so that a sampling data stream is effectively improved, the sampling data stream which is originally provided with burrs is smooth, the circuit can obtain high jitter tolerance, and the high noise inhibiting ability can be provided.
Description
Technical field
The present invention relates to the semiconductor integrated circuit design field, particularly relate to the clock data recovery circuit (CDR) for serial communication.
Background technology
Clock data recovery circuit (CDR) is as the important component part of receiving terminal, it is responsible for extracting synchronizing information from serial data at a high speed, and sampling recovers correct digital signal to serial signal to utilize this synchronizing information, and logarithm is now gone here and there and changes factually.Generally speaking, when serial data sends on transmission medium at transmitting terminal, the characteristic of data-signal is more satisfactory.And, at receiving terminal, the data-signal arrived by transmission medium has been superposeed by outside noise and interference.Receiving terminal, when from serial data, extracting data, must be selected best sampling judgement constantly, thereby guarantee the minimum error rate.For such situation, data recovery circuit must possess certain jitter toleration and suppress the ability of noise, interference.
Blind over-sampling data recovery circuit mainly is divided into receiver and two parts of data recovery circuit, restriction due to the local clock frequency, receiver generally adopts the space over-sampling, and its implementation has with multi-phase clock sampling frequently and two kinds of concrete methods of data delay chain sampling.
What the traditional data restore circuit adopted is mainly difference in logic, mainly contain two kinds: a kind of is statistical decision: the corresponding positions of two adjacent groups register is carried out XOR and is detected to complete edge, testing result grouping addition, apart from greatest measure, corresponding sampling clock clock farthest can be used as recovered clock so, by the data of this clock sampling, can be used as the recovery data; The second is the phase demodulation coding: then marked in the hopping edge in sampled data stream by phase demodulation, and then select suitable sampling clock as the optimum sampling recovery point.
This method of statistical decision requires input data transfer rate is the same with local sample frequency just can guarantee correctly to recover data, if frequency difference is arranged, recovery time of a specified duration will cause huge error code, the phase demodulation this mode of encoding allows both to have certain frequency departure, so the scope of application is wider; For statistical decision, need to consume certain data bit and carry out the phase place statistics and then could produce correct sampling phase, locking time is oversize; The words of phase demodulation coding circuit are compared to the method for statistical decision, and amount of calculation is relatively larger, and the cycle that data are processed is also relatively longer, the Digital Implementation relative complex; Also exist some problems for the phase demodulation coding circuit, the wherein unsmooth correct recovery that will directly affect data of sampled data stream, cause the great error rate (BER), when consecutive word is too much, also can produce larger impact.
Summary of the invention
goal of the invention:problem and shortage for above-mentioned existing existence, the purpose of this invention is to provide a kind of blind over-sampling clock data recovery circuit with filtering shaping circuit, at the synchronous adjusting module of the receiver back of the blind over-sampling clock data recovery circuit of tradition process, add this filtering shaping circuit.This filtering shaping circuit must with the phase demodulation coding module reasonable combination of synchronizeing adjusting module and rear class of prime, could realize good noiseproof feature, obtain very high jitter toleration.
technical scheme:a kind of blind over-sampling clock data recovery circuit with filtering shaping circuit of the present invention comprises the receiver by parallel over-sampling module composition; The data recovery circuit formed by synchronization adjustment circuit, filtering shaping circuit, phase demodulation coding circuit, control circuit, data selection circuit, the phase-locked loop formed by phase frequency detector, charge pump, loop filter, frequency divider, multiphase voltage controlled oscillator; Wherein the input of synchronization adjustment circuit directly is connected with receiver, output termination filtering shaping circuit, the output of filtering shaping circuit divides two-way, and a road connects the phase demodulation coding circuit, another road connects data selection circuit, and control circuit is connected with data selection circuit with the phase demodulation coding circuit respectively; In phase-locked loop, phase frequency detector, charge pump, loop filter, frequency divider are linked in sequence and form a loop, the output termination multiphase voltage controlled oscillator of loop filter, the output termination receiver of multiphase voltage controlled oscillator;
This filtering shaping circuit comprises 3 11 bit register arrays, 9 adder arrays, 9 data selection gate array and 19 output register, wherein, register array comprises i.e. the first register reg1, the second register reg2, the 3rd register reg3;
11 bit data PBit4, PBit5, PBit6, PBit7, PBit8, Bit1, Bit2, Bit3, Bit4, Bit5, the Bit6 obtained after synchronous the adjustment deposits respectively the relevant position of three registers in, PBit means the data in last sampled data stream, and Bit means the data in current sampled data stream.Is the adder of 93 input 2 outputs below three registers, PBit6 by the first register, the PBit4 of the PBit5 of the second register and the 3rd register is connected with the input of first adder, PBit7 by the first register, the PBit5 of the PBit6 of the second register and the 3rd register is connected with the input of second adder, PBit8 by the first register, the PBit6 of the PBit7 of the second register and the 3rd register is connected with the input of the 3rd adder, Bit1 by the first register, the PBit7 of the PBit8 of the second register and the 3rd register is connected with the input of the 4th adder, Bit2 by the first register, the PBit8 of the Bit1 of the second register and the 3rd register is connected with the input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, Bit3 by the first register, the Bit1 of the Bit2 of the second register and the 3rd register is connected with the input of the 6th adder, Bit4 by the first register, the Bit2 of the Bit3 of the second register and the 3rd register is connected with the input of the 7th adder, Bit5 by the first register, the Bit3 of the Bit4 of the second register and the 3rd register is connected with the input of the 8th adder, finally by the Bit6 of the first register, the Bit4 of the Bit5 of the second register and the 3rd register is connected with the input of the 9th adder, the data selection module of one 2 input 1 output of termination under each adder, output H1 by first adder, L1 is connected with the input of the first data selection module, output H2 by second adder, L2 is connected with the input of the second data selection module, output H3 by the 3rd adder, L3 is connected with the input of the 3rd data selection module, output H4 by the 4th adder, L4 is connected with the input of the 4th data selection module, output H5 by the slender acanthopanax musical instruments used in a Buddhist or Taoist mass, L5 is connected with the input of the 5th data selection module, output H6 by the 6th adder, L6 is connected with the input of the 6th data selection module, output H7 by the 7th adder, L7 is connected with the input of the 7th data selection module, output H8 by the 8th adder, L8 is connected with the input of the 8th data selection module, output H9 by the 9th adder, L9 is connected with the input of the 9th data selection module, finally, selecting module to have 9 outputs altogether 9 data is connected with output register bottom, so just formed this filtering shaping circuit.
The principle that realizes of the present invention: in order to eliminate the distortion data in sampled data stream, the realization of filtering shaping circuit is based on some characteristics of data flow, if produced a distortion sampled data, this sampled data must be all different with the front and back data so, just be based on this characteristic, just can realize the distorting shaping of sampled data, recover the level and smooth of data.For blind over-sampling clock data recovery circuit more than 4 times and 4 times, all be suitable for.
beneficial effect:the present invention by sampled data filter shape, make script become smooth smooth with the data flow of distortion sampled data, hopping edge is more accurately regular, coordinates so the phase demodulation coding circuit of back again, completes phase-detection and the data of sampled data stream are recovered.Adding of this invention, greatly improved the accuracy of the edge detection of circuit, sampled data stream smooth further improved the accuracy that data are recovered, and effectively reduces the error rate (BER) of blind over-sampling clock data recovery circuit, and system has higher noiseproof feature and jitter toleration.If sample frequency is 5Gbps, adopt 5 times of over-samplings, when scope that frequency is determined is 250M, the consecutive word tolerance has reached 32 bit, excellent performance so.
The accompanying drawing explanation
Fig. 1 is the filtering shaping circuit that is applied to blind over-sampling clock data recovery circuit of the present invention;
Fig. 2 is the structure of filtering shaping circuit.
Fig. 3 is the synchronous structure of adjusting of sampled data stream.
Fig. 4 is the comprehensive rear sequential analogous diagram that has added the blind over-sampling clock data recovery circuit of filtering shaping circuit.
Embodiment
For the technological means that further illustrates advantage of the present invention place and specifically take, following constipation closes diagram and describes the specific embodiment of the present invention and circuit structure in detail.
Fig. 1 illustrates formed blind over-sampling clock data recovery circuit, it comprises the receiver by parallel over-sampling module composition, the data recovery module formed by synchronous adjusting module, filtering shaping circuit, phase demodulation coding circuit, control circuit, data selection circuit, wherein synchronous adjusting module directly is connected with receiver, back connects this filtering shaping circuit, then divide two-way, lower road connects the phase demodulation coding circuit, right wing connects data selection circuit, finally pass through control circuit, then phase demodulation coding circuit and data selection circuit are coupled together.The phase-locked loop formed by phase frequency detector PFD, charge pump CP, loop filter LF, frequency divider/M and multiphase voltage controlled oscillator VCO, wherein by PFD, CP, LF ,/M is interconnected to constitute a loop, meet leggy VCO on LF, leggy VCO is connected with receiver again.
Fig. 2 shows the filtering shaping circuit that can be applicable to blind over-sampling clock data recovery circuit, this filtering shaping circuit mainly contains four parts and forms: 3 11 bit register arrays: the first register reg1, the second register reg2, the 3rd register reg3,9 adder arrays, 9 data are selected gate array, 19 output register.11 bit data PBit4, PBit5, PBit6, PBit7, PBit8, Bit1, Bit2, Bit3, Bit4, Bit5, the Bit6 wherein obtained after synchronous the adjustment deposits respectively the relevant position of three registers in, PBit means the data in last sampled data stream, and Bit means the data in current sampled data stream.Three register lower ends, are adders of 93 input 2 outputs, PBit6 by the first register, the PBit4 of the PBit5 of the second register and the 3rd register is connected with the input of first adder, PBit7 by the first register, the PBit5 of the PBit6 of the second register and the 3rd register is connected with the input of second adder, PBit8 by the first register, the PBit6 of the PBit7 of the second register and the 3rd register is connected with the input of the 3rd adder, Bit1 by the first register, the PBit7 of the PBit8 of the second register and the 3rd register is connected with the input of the 4th adder, Bit2 by the first register, the PBit8 of the Bit1 of the second register and the 3rd register is connected with the input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, Bit3 by the first register, the Bit1 of the Bit2 of the second register and the 3rd register is connected with the input of the 6th adder, Bit4 by the first register, the Bit2 of the Bit3 of the second register and the 3rd register is connected with the input of the 7th adder, Bit5 by the first register, the Bit3 of the Bit4 of the second register and the 3rd register is connected with the input of the 8th adder, finally by the Bit6 of the first register, the Bit4 of the Bit5 of the second register and the 3rd register is connected with the input of the 9th adder, the data selection module of one 2 input 1 output of termination under each adder, output H1 by first adder, L1 is connected with the input of the first data selection module, output H2 by second adder, L2 is connected with the input of the second data selection module, output H3 by the 3rd adder, L3 is connected with the input of the 3rd data selection module, output H4 by the 4th adder, L4 is connected with the input of the 4th data selection module, output H5 by the slender acanthopanax musical instruments used in a Buddhist or Taoist mass, L5 is connected with the input of the 5th data selection module, output H6 by the 6th adder, L6 is connected with the input of the 6th data selection module, output H7 by the 7th adder, L7 is connected with the input of the 7th data selection module, output H8 by the 8th adder, L8 is connected with the input of the 8th data selection module, output H9 by the 9th adder, L9 is connected with the input of the 9th data selection module, finally, selecting module to have 9 outputs altogether 9 data is connected with output register bottom, so just formed this filtering shaping circuit.
Fig. 1 illustrates the blind over-sampling clock data recovery circuit that has added Shaping Module and mainly is divided into receiver and two parts of data recovery circuit, for the sampling section in receiver, and 8 phase differences 45 will exporting by phase-locked loop
.clock input signal is carried out to 4 times of blind over-samplings, so with regard to two signals of sampling simultaneously, reduced the requirement to PLL output clock frequency, this over-sampling rate, both guaranteed receiving the jitter toleration of data-signal, required sampling clock number is unlikely to again a lot, has guaranteed circuit in the situation that PLL output clock number is less can use.After over-sampling, the data flow that sampling is obtained is sent into synchronous adjusting module, for whole filtering shaping circuit, if the words of 9 sampled data streams of shaping not only need these 9 of current shaping: PBit5, PBit6, PBit7, PBit8, Bit1, Bit2, Bit3, Bit4, Bit5 also need the PBit4 in last data stream, add the Bit6 in the current data code stream, when adjusting, only need latter 5 in current 8 sampled data streams are stayed as next shaping.After each the adjustment, output needs two excessive datas of 9 sampled datas of shaping and both sides in filtering shaping circuit.
Fig. 3 shows the structure of this filtering shaping circuit, above-mentioned 11 bit data are divided into to three groups, one group is carried out the data reach, after one group of data, move, three groups of data are stored respectively, then by 3 data additions on the data bit of required shaping, by the PBit6 by the first register, the PBit4 of the PBit5 of the second register and the 3rd register is connected with the input of first adder, PBit7 by the first register, the PBit5 of the PBit6 of the second register and the 3rd register is connected with the input of second adder, PBit8 by the first register, the PBit6 of the PBit7 of the second register and the 3rd register is connected with the input of the 3rd adder, Bit1 by the first register, the PBit7 of the PBit8 of the second register and the 3rd register is connected with the input of the 4th adder, Bit2 by the first register, the PBit8 of the Bit1 of the second register and the 3rd register is connected with the input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, Bit3 by the first register, the Bit1 of the Bit2 of the second register and the 3rd register is connected with the input of the 6th adder, Bit4 by the first register, the Bit2 of the Bit3 of the second register and the 3rd register is connected with the input of the 7th adder, Bit5 by the first register, the Bit3 of the Bit4 of the second register and the 3rd register is connected with the input of the 8th adder, finally by the Bit6 of the first register, the Bit4 of the Bit5 of the second register and the 3rd register is connected with the input of the 9th adder, obtain two 2 systems and count HxLx, if the data of current shaping are accidental data, be assumed to be 1, the left and right data are all 0 so, now HxLx is 01, Hx is the data 0 that the shaping data should be exported so, if current shaping data are 0, the left and right data are all 1 so, now HxLx is 10, the data 1 that Hx still should export for the shaping data so, so 2/3 following decision circuit is data and selects module, select correct data are outputed in 9 output registers, data in 9 output registers are as the output of shaping circuit.
Filter shape by this circuit to sampled data stream, eliminated distortion sampled data wherein, make whole sampled data stream become more smooth, add afterwards the phase demodulation coding circuit sampled data stream after shaping is carried out to the detection of hopping edge, and every sampled data is encoded under the operation of peripheral control circuit, while completing the resetting of sampled data stream, finally add data selection circuit, according to the gained codes selection, suitable sampling clock is as the optimum sampling recovery point and then recover valid data.
Fig. 4 shows the comprehensive post-simulation figure of the blind over-sampling clock data recovery circuit that has added filtering shaping circuit, blind over-sampling circuit like this is by the Verilog realization of programming, complete the comprehensive post-simulation of Modelsim and Quartus II, owing to adopting the FPGA checking, be limited to the PLL output clock number restriction of FPGA inside, therefore adopt 4 output clock clk0 of inner PLL, clk1, clk2, clk3, 90 ° of bilateral edge samplings of phase difference realize, export two dout1 as a result at the trailing edge of clk1 simultaneously, dout2, can see, final Output rusults and input signal (din) are in full accord, and eliminated the distorted signal in din, proved the correctness of this circuit.The data regeneration rate that this design has met the 100M fiber optic Ethernet has required.
Adding of this filtering shaping circuit, synchronous adjustment and phase demodulation coding module before and after coordinating again, make so blind over-sampling clock and data recovery there is the wider scope of application, for consecutive word, very high tolerance is arranged, locking that can be very fast also recovers data, also has very high noiseproof feature, can improve unsmooth in sampled data stream, the final error rate (BER) that greatly reduces the data recovery, the data that complete under burst mode are recovered.
It is only below example of the present invention, do not form any limitation of the invention, obviously, under thought of the present invention, any those skilled in the art, within not breaking away from technical scheme scope of the present invention, can utilize the technology contents of above-mentioned announcement suitably adjust or optimize circuit structure and metalogic thought, refer to according to technology of the present invention any simple modification, equivalents and the modification that above example is done, all belong to the scope of technical solution of the present invention.
Claims (2)
1. the blind over-sampling clock data recovery circuit with filtering shaping circuit, is characterized in that described blind over-sampling clock data recovery circuit comprises the receiver (1) by parallel over-sampling module composition; The data recovery circuit (2) formed by synchronization adjustment circuit (21), filtering shaping circuit (22), phase demodulation coding circuit (23), control circuit (24), data selection circuit (25); The phase-locked loop (3) formed by phase frequency detector (PFD), charge pump (CP), loop filter (LF), frequency divider (/M), multiphase voltage controlled oscillator (VCO); Wherein the input of synchronization adjustment circuit (21) directly is connected with receiver (1), output termination filtering shaping circuit (22), the output of filtering shaping circuit (22) divides two-way, one tunnel connects phase demodulation coding circuit (26), another road connects data selection circuit (27), and control circuit (24) is connected with data selection circuit with the phase demodulation coding circuit respectively; In phase-locked loop (3), phase frequency detector (PFD), charge pump (CP), loop filter (LF), frequency divider (/M) are linked in sequence and form a loop, the output termination multiphase voltage controlled oscillator (VCO) of loop filter (LF), the output termination receiver (1) of multiphase voltage controlled oscillator (VCO).
2. according to the blind over-sampling clock data recovery circuit with filtering shaping circuit claimed in claim 1, it is characterized in that: this filtering shaping circuit comprises 3 11 bit register arrays, 9 adder arrays, 9 data selection gate array and 19 output register, wherein, register array comprises i.e. the first register reg1, the second register reg2, the 3rd register reg3;
11 bit data PBit4, PBit5, PBit6, PBit7, PBit8, Bit1, Bit2, Bit3, Bit4, Bit5, the Bit6 obtained after synchronous the adjustment deposits respectively the relevant position of three registers in, PBit means the data in last sampled data stream, and Bit means the data in current sampled data stream;
Is the adder of 93 input 2 outputs below three registers, PBit6 by the first register, the PBit4 of the PBit5 of the second register and the 3rd register is connected with the input of first adder, PBit7 by the first register, the PBit5 of the PBit6 of the second register and the 3rd register is connected with the input of second adder, PBit8 by the first register, the PBit6 of the PBit7 of the second register and the 3rd register is connected with the input of the 3rd adder, Bit1 by the first register, the PBit7 of the PBit8 of the second register and the 3rd register is connected with the input of the 4th adder, Bit2 by the first register, the PBit8 of the Bit1 of the second register and the 3rd register is connected with the input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, Bit3 by the first register, the Bit1 of the Bit2 of the second register and the 3rd register is connected with the input of the 6th adder, Bit4 by the first register, the Bit2 of the Bit3 of the second register and the 3rd register is connected with the input of the 7th adder, Bit5 by the first register, the Bit3 of the Bit4 of the second register and the 3rd register is connected with the input of the 8th adder, finally by the Bit6 of the first register, the Bit4 of the Bit5 of the second register and the 3rd register is connected with the input of the 9th adder, the data selection module of one 2 input 1 output of termination under each adder, output H1 by first adder, L1 is connected with the input of the first data selection module, output H2 by second adder, L2 is connected with the input of the second data selection module, output H3 by the 3rd adder, L3 is connected with the input of the 3rd data selection module, output H4 by the 4th adder, L4 is connected with the input of the 4th data selection module, output H5 by the slender acanthopanax musical instruments used in a Buddhist or Taoist mass, L5 is connected with the input of the 5th data selection module, output H6 by the 6th adder, L6 is connected with the input of the 6th data selection module, output H7 by the 7th adder, L7 is connected with the input of the 7th data selection module, output H8 by the 8th adder, L8 is connected with the input of the 8th data selection module, output H9 by the 9th adder, L9 is connected with the input of the 9th data selection module, finally, selecting module to have 9 outputs altogether 9 data is connected with output register bottom, so just formed this filtering shaping circuit.
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| CN107943738A (en) * | 2017-11-28 | 2018-04-20 | 珠海全志科技股份有限公司 | Clock data recovery circuit and implementation method |
| US11296709B2 (en) | 2018-12-21 | 2022-04-05 | Huawei Technologies Co., Ltd. | Cross-clock-domain processing circuit |
| CN112840593B (en) * | 2018-12-21 | 2022-05-13 | 华为技术有限公司 | Clock domain crossing processing circuit |
| CN112840593A (en) * | 2018-12-21 | 2021-05-25 | 华为技术有限公司 | Cross-clock domain processing circuit |
| TWI690162B (en) * | 2019-08-30 | 2020-04-01 | 瑞昱半導體股份有限公司 | Clock data recovery apparatus and method |
| CN111541447A (en) * | 2020-05-26 | 2020-08-14 | 中国人民解放军国防科技大学 | Clock data recovery circuit for PAM4 receiver with waveform screening function and PAM4 receiver |
| CN111541447B (en) * | 2020-05-26 | 2023-06-30 | 中国人民解放军国防科技大学 | Clock data recovery circuit for PAM4 receiver and PAM4 receiver |
| CN112184934A (en) * | 2020-09-30 | 2021-01-05 | 广州市埃特斯通讯设备有限公司 | Method and system for decoding FM0 coded data of ETC |
| CN112184934B (en) * | 2020-09-30 | 2022-06-03 | 广州市埃特斯通讯设备有限公司 | Method and system for decoding FM0 coded data of ETC |
| CN114363734A (en) * | 2020-10-12 | 2022-04-15 | 华为技术有限公司 | Clock data recovery method, input/output device and optical line terminal |
| CN114363734B (en) * | 2020-10-12 | 2023-06-20 | 华为技术有限公司 | Clock data recovery method, input/output device and optical line terminal |
| CN113037667B (en) * | 2021-02-24 | 2022-03-15 | 电子科技大学 | Data signal recovery method based on FPGA |
| CN113037667A (en) * | 2021-02-24 | 2021-06-25 | 电子科技大学 | Data signal recovery method based on FPGA |
| CN113886300A (en) * | 2021-09-23 | 2022-01-04 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
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