CN102684653A - Digital synchronous pulse wireless low-jitter transmission method - Google Patents
Digital synchronous pulse wireless low-jitter transmission method Download PDFInfo
- Publication number
- CN102684653A CN102684653A CN2012101694519A CN201210169451A CN102684653A CN 102684653 A CN102684653 A CN 102684653A CN 2012101694519 A CN2012101694519 A CN 2012101694519A CN 201210169451 A CN201210169451 A CN 201210169451A CN 102684653 A CN102684653 A CN 102684653A
- Authority
- CN
- China
- Prior art keywords
- pulse
- reference clock
- signal
- clock
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to a digital synchronous pulse wireless low-jitter transmission method in the field of pulse wireless transmission communication, and the method is especially applicable to wireless low-jitter transmission of radar pulse. Pulse shaping is carried out at a transmitting terminal, a PLL (Phase Locked Loop) circuit is adopted for enabling a reference clock to be in phase synchronization with a pulse synchronous clock, and the synchronized reference clock is utilized for performing digital sampling, coding, modulation and other modulation steps on pulse; and a PLL circuit is adopted at a receiving terminal for enabling a reference clock to be in phase synchronization with the reference clock at the transmitting terminal, the synchronized reference clock is utilized for completing pulse demodulation, decoding, recovery and other demodulation steps, and a low-jitter pulse signal is finally output. The digital synchronous pulse wireless low-jitter transmission method can be used for well recovering the pulse at the transmitting terminal and has low requirements on the clocks in the system, and main circuit components are realized by adopting an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) so as to be low in design and debugging difficulty.
Description
Technical field
The present invention relates to a kind of digital synchronous pulse wireless low jitter transmission method in the pulse wireless transport communication field, be specially adapted to the wireless low jitter transmission of radar pulse.
Background technology
Pulse digit sampling wireless transmission method commonly used can be judged having or not of pulse signal accurately at receiving terminal, and the rising edge of the pulse signal that still receives, trailing edge are shaken bigger.Reduce along shake, just need to improve the sampling clock frequency, thereby improve the sample rate of paired pulses.If the requirement to along shake is low to moderate nanosecond, then required clock frequency is up to 1GHz even higher.Under current technical conditions, this is difficult to realize.
Summary of the invention
Technical problem to be solved by this invention is to avoid the weak point in the above-mentioned background and a kind of pulse digit wireless low jitter transmission method based on synchronised clock is provided.The synchronised clock that produces pulse signal is incorporated in the transmission system, utilizes synchronised clock that the reference clock of digital modulator is advanced horizontal lock, accomplish sampling, modulation and the transmission of pulse signals with the reference clock after locking mutually.The main circuit parts sampling FPGA or the ASIC of the inventive method realize, high conformity, and debugging difficulty is low, realizes the wireless transmission of pulse jitter less than 5ns easily.
The objective of the invention is to realize like this, it comprises step:
1) transmitted pulse gets into modulating unit, carries out shaping pulse, and the pulse distortion in the Wireline transmission is corrected;
2) synchronised clock gets into modulating unit, adopts phase-locked loop circuit (PLL) that the reference clock signal of modulating unit is advanced horizontal lock, makes reference clock and synchronous clock phase synchronous;
3) transmitted pulse of the reference clock after utilizing lock mutually after to shaping carries out digital sample, coding, modulation, and pulse information and clock information are contained in the digital modulation signals;
4) digital modulation signals is carried out D/A switch, convert modulated-analog signal into;
5) modulated-analog signal gets into radio frequency unit, and modulation signal is carried out up-conversion, power amplification, converts high-frequency signal into, gets into wireless channel through antenna;
6) antenna of radio frequency unit receives the high-frequency signal in the wireless channel, is modulated-analog signal through circuit conversion such as low noise amplification, down-conversion, AGC;
7) modulated-analog signal gets into demodulating unit, through mould/number conversion, converts digital modulation signals into;
8) utilize in the digital modulation signals clock information as a reference, through phase-locked loop circuit (PLL), make the reference clock Phase synchronization of the reference clock and the modulating unit of demodulating unit;
9) reference clock signal after utilizing synchronously carries out digital demodulation, decoding, pulse-recovery to digital modulation signals, in demodulating unit, recovers pulse signal;
10) pulse signal that recovers is finally exported the low jitter pulse signal through judgement;
The transmission of completion pulse wireless low jitter.
The present invention compares with background technology, has following advantage:
1, the pulse wireless transmission method of the present invention's proposition is compared with the pulse wireless transmission of the digital form of using always, has guaranteed the special applications of pulse edge low jitter in the pulse wireless transmission.The pulse wireless transmission method of digital form commonly used, emphasis transmission pulse level, when the edge shake was proposed requiring of nanosecond, the digital sample clock need be increased to more than the 1GHz.Such system clock is realized difficulty, and expense is very high, and high sample rate has increased the design difficulty of modulation.The pulse wireless transmission method that the present invention proposes, the synchronised clock of the generation pulse of introducing, the system clock of transmitter unit and receiving element are all synchronous with synchronous clock phase, sample and modulation with the system clock paired pulses synchronously.Adopt this method, less demanding to system clock, reduced the design difficulty of modulation.
2, the main circuit parts of the inventive method adopt FPGA or ASIC to realize, high conformity, and debugging difficulty is low, realizes the wireless transmission of pulse jitter less than 5ns easily.
Description of drawings
Fig. 1 is the electric functional-block diagram of the wired side signal of the present invention to wireless side inter-process embodiment.
Fig. 2 is the electric functional-block diagram of wireless side signal of the present invention to wired side inter-process embodiment.
1 is the shaping pulse module among Fig. 1, and 2 is phase-locked loop module, and 3 is impulse sampling, coding, modulation module, and 4 is the D/A switch module, and 5 is the radio frequency unit module.Wherein phase-locked loop module generally comprises parts such as phase discriminator, loop filter, VCXO; Impulse sampling, coding, modulation module generally are made up of FPGA or ASIC, and the radio frequency unit module generally comprises parts such as local oscillator, I/Q modulator, upconverter, power amplifier, antenna.
6 is the radio frequency unit module among Fig. 2, and 7 is mould/number conversion module, and 8 are pulse demodulation, decoding, recovery module, and 9 is phase-locked loop module, and 10 are the pulse judging module.Wherein the radio frequency unit module generally comprises parts such as antenna, low noise amplifier, low-converter, AGC, i/q demodulator, local oscillator; Pulse demodulation, recovery module generally are made up of FPGA or ASIC, and phase-locked loop module generally comprises parts such as phase discriminator, loop filter, VCXO.
Embodiment
Referring to figs. 1 through Fig. 2.Fig. 1 is the electric functional-block diagram of the wired side signal of the present invention to wireless side inter-process embodiment, and it comprises shaping pulse module 1, phase-locked loop module 2, impulse sampling, coding, modulation module 3, D/A switch module 4, radio frequency unit module 5; Wherein shaping pulse module 1, phase-locked loop module 2, impulse sampling, coding, modulation module 3, D/A switch module 4 constitutes modulating unit.1 pair of input pulse of shaping pulse module carries out shaping, and the pulse distortion in the circuit transmission is corrected; The reference clock signal of 2 pairs of modulating units of phase-locked loop module advances horizontal lock, makes the synchronous clock phase of reference clock and pulse signal synchronous; The transmitted pulse of reference clock after impulse sampling, coding, modulation module 3 utilizes lock mutually after to shaping carries out digital sample, coding, modulation, and pulse information and clock information are contained in the digital modulation signals; 4 pairs of digital modulation signals of D/A switch module carry out D/A switch, convert modulated-analog signal into; Modulated-analog signal is transformed to radiofrequency signal through radio frequency unit module 5 and gets into wireless transmission.
Fig. 2 is the electric functional-block diagram of wireless side signal of the present invention to wired side inter-process embodiment, and it comprises radio frequency unit module 6, mould/number conversion module 7, pulse demodulation, decoding, recovery module 8, phase-locked loop module 9, pulse judging module 10; Mould/number conversion module 7 wherein, pulse demodulation, decoding, recovery module 8, phase-locked loop module 9, pulse judging module 10 constitutes demodulating units.Radio frequency unit module 6 is transformed to modulated-analog signal with the radiofrequency signal of wireless transmission; Modulated-analog signal gets into mould/number conversion module 7, converts digital modulation signals into; Utilize in the digital modulation signals clock information as a reference, through phase-locked loop module 9, make the reference clock Phase synchronization of the reference clock and the modulating unit of demodulating unit; In pulse demodulation, decoding, recovery module 8, the reference clock signal after the utilization synchronously carries out digital demodulation, decoding, pulse-recovery to digital modulation signals; The pulse signal that recovers is finally exported the low jitter pulse signal through pulse judging module 10.
The signal transmission of technical scheme of the present invention is carried out according to the following steps:
1) transmitted pulse gets into modulating unit, carries out shaping pulse, and the pulse distortion in the Wireline transmission is corrected, and embodiment is accomplished by the shaping pulse module 1 among Fig. 1;
2) synchronised clock gets into modulating unit, adopts phase-locked loop circuit (PLL) that the reference clock signal of modulating unit is advanced horizontal lock, makes reference clock and synchronous clock phase synchronous, and embodiment is accomplished by the phase-locked loop module among Fig. 12;
3) transmitted pulse of the reference clock after utilizing lock mutually after to shaping carries out digital sample, coding, modulation, and pulse information and clock information are contained in the digital modulation signals, and embodiment is accomplished by the impulse sampling among Fig. 1, coding, modulation module 3;
4) digital modulation signals is carried out D/A switch, convert modulated-analog signal into, embodiment is accomplished by the D/A switch module 4 among Fig. 1;
5) modulated-analog signal gets into radio frequency unit, and modulation signal is carried out up-conversion, power amplification, converts high-frequency signal into, gets into wireless channel through antenna, and embodiment is accomplished by the radio frequency unit module 5 among Fig. 1;
6) antenna of radio frequency unit receives the high-frequency signal in the wireless channel, is modulated-analog signal through circuit conversion such as low noise amplification, down-conversion, AGC, and embodiment is accomplished by the radio frequency unit module 6 among Fig. 2;
7) modulated-analog signal gets into demodulating unit, through mould/number conversion, converts digital modulation signals into, and embodiment is accomplished by the mould among Fig. 2/number conversion module 7;
8) utilize in the digital modulation signals clock information as a reference, through phase-locked loop circuit (PLL), make the reference clock Phase synchronization of the reference clock and the modulating unit of demodulating unit, embodiment is accomplished by the phase-locked loop module among Fig. 29;
9) reference clock signal after utilizing synchronously carries out digital demodulation, decoding, pulse-recovery to digital modulation signals, in demodulating unit, recovers pulse signal, and embodiment is accomplished by the pulse demodulation among Fig. 2, decoding, recovery module 8;
10) pulse signal that recovers is finally exported the low jitter pulse signal through judgement, and embodiment is accomplished by the pulse judging module 10 among Fig. 2.
Claims (1)
1. digital synchronous pulse wireless low jitter transmission method is characterized in that comprising step:
1) transmitted pulse gets into modulating unit, carries out shaping pulse, and the pulse distortion in the Wireline transmission is corrected;
2) synchronised clock gets into modulating unit, adopts phase-locked loop circuit that the reference clock signal of modulating unit is advanced horizontal lock, makes reference clock and synchronous clock phase synchronous;
3) transmitted pulse of the reference clock after utilizing lock mutually after to shaping carries out digital sample, coding, modulation, and pulse information and clock information are contained in the digital modulation signals;
4) digital modulation signals is carried out D/A switch, convert modulated-analog signal into;
5) modulated-analog signal gets into radio frequency unit, and modulation signal is carried out up-conversion, power amplification, converts high-frequency signal into, gets into wireless channel through antenna;
6) antenna of radio frequency unit receives the high-frequency signal in the wireless channel, converts modulated-analog signal into through low noise amplification, down-conversion, agc circuit;
7) modulated-analog signal gets into demodulating unit, through mould/number conversion, converts digital modulation signals into;
8) utilize in the digital modulation signals clock information as a reference, through phase-locked loop circuit, make the reference clock Phase synchronization of the reference clock and the modulating unit of demodulating unit;
9) reference clock signal after utilizing synchronously carries out digital demodulation, decoding, pulse-recovery to digital modulation signals, in demodulating unit, recovers pulse signal;
10) pulse signal that recovers is finally exported the low jitter pulse signal through judgement;
The transmission of completion pulse wireless low jitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210169451.9A CN102684653B (en) | 2012-05-29 | 2012-05-29 | Digital synchronous pulse wireless low-jitter transmission method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210169451.9A CN102684653B (en) | 2012-05-29 | 2012-05-29 | Digital synchronous pulse wireless low-jitter transmission method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102684653A true CN102684653A (en) | 2012-09-19 |
| CN102684653B CN102684653B (en) | 2015-07-01 |
Family
ID=46816116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210169451.9A Expired - Fee Related CN102684653B (en) | 2012-05-29 | 2012-05-29 | Digital synchronous pulse wireless low-jitter transmission method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102684653B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN103905015A (en) * | 2014-04-15 | 2014-07-02 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method for high-precision digital asynchronous pulse |
| CN103986565A (en) * | 2014-06-06 | 2014-08-13 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method of clock signal |
| CN105049004A (en) * | 2015-07-02 | 2015-11-11 | 国家电网公司 | Tube-type nanosecond high voltage steep pulse source |
| CN105974375A (en) * | 2016-04-27 | 2016-09-28 | 山东省科学院自动化研究所 | Method of suppressing timing jitter in ultra-wideband through-wall radar |
| CN106940394A (en) * | 2017-04-24 | 2017-07-11 | 南京南瑞继保电气有限公司 | It is a kind of to realize the method that optical current mutual inductor is measured at a high speed |
| CN111800164A (en) * | 2020-07-02 | 2020-10-20 | 成都精位科技有限公司 | UWB decoding method, device, receiver and UWB positioning system |
| CN112737570A (en) * | 2020-12-15 | 2021-04-30 | 中国科学技术大学 | PAM4 signal clock data recovery method based on software phase-locked loop |
| CN117595865A (en) * | 2023-12-12 | 2024-02-23 | 深圳新港海岸科技有限公司 | Circuit for reducing clock signal jitter |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574725A (en) * | 2003-05-23 | 2005-02-02 | 三洋电机株式会社 | Radio transmission system |
| CN1897490A (en) * | 2005-01-20 | 2007-01-17 | Vixs系统公司 | System and method for multimedia delivery in a wireless environment |
| US20090196312A1 (en) * | 2008-02-02 | 2009-08-06 | Keio University | Integrated circuit |
| CN101594130A (en) * | 2009-07-02 | 2009-12-02 | 中国电子科技集团公司第五十四研究所 | A kind of pulse wireless low jitter transmission method based on slope frequency detection mode |
| CN201467124U (en) * | 2009-08-06 | 2010-05-12 | 中国电子科技集团公司第五十四研究所 | Multi-mode compatible channel machine |
| CN101836372A (en) * | 2007-08-15 | 2010-09-15 | 诺基亚公司 | Alternate mobile network cell synchronization |
-
2012
- 2012-05-29 CN CN201210169451.9A patent/CN102684653B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574725A (en) * | 2003-05-23 | 2005-02-02 | 三洋电机株式会社 | Radio transmission system |
| CN1897490A (en) * | 2005-01-20 | 2007-01-17 | Vixs系统公司 | System and method for multimedia delivery in a wireless environment |
| CN101836372A (en) * | 2007-08-15 | 2010-09-15 | 诺基亚公司 | Alternate mobile network cell synchronization |
| US20090196312A1 (en) * | 2008-02-02 | 2009-08-06 | Keio University | Integrated circuit |
| CN101594130A (en) * | 2009-07-02 | 2009-12-02 | 中国电子科技集团公司第五十四研究所 | A kind of pulse wireless low jitter transmission method based on slope frequency detection mode |
| CN201467124U (en) * | 2009-08-06 | 2010-05-12 | 中国电子科技集团公司第五十四研究所 | Multi-mode compatible channel machine |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN103219992B (en) * | 2013-01-31 | 2016-01-27 | 南京邮电大学 | A kind of blind over-sampling clock data recovery circuit with filtering shaping circuit |
| CN103905015B (en) * | 2014-04-15 | 2017-04-05 | 中国电子科技集团公司第五十四研究所 | A kind of wireless low jitter transmission method of high accuracy number asynchronous pulse |
| CN103905015A (en) * | 2014-04-15 | 2014-07-02 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method for high-precision digital asynchronous pulse |
| CN103986565A (en) * | 2014-06-06 | 2014-08-13 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method of clock signal |
| CN103986565B (en) * | 2014-06-06 | 2017-05-24 | 中国电子科技集团公司第五十四研究所 | Wireless low-jitter transmission method of clock signal |
| CN105049004A (en) * | 2015-07-02 | 2015-11-11 | 国家电网公司 | Tube-type nanosecond high voltage steep pulse source |
| CN105049004B (en) * | 2015-07-02 | 2018-03-30 | 国家电网公司 | A kind of tubular type nanosecond high pressure steep-sided pulse source |
| CN105974375A (en) * | 2016-04-27 | 2016-09-28 | 山东省科学院自动化研究所 | Method of suppressing timing jitter in ultra-wideband through-wall radar |
| CN105974375B (en) * | 2016-04-27 | 2019-01-18 | 山东省科学院自动化研究所 | A method of for inhibiting time jitter in ultra-broadband wall-through radar |
| CN106940394A (en) * | 2017-04-24 | 2017-07-11 | 南京南瑞继保电气有限公司 | It is a kind of to realize the method that optical current mutual inductor is measured at a high speed |
| CN111800164A (en) * | 2020-07-02 | 2020-10-20 | 成都精位科技有限公司 | UWB decoding method, device, receiver and UWB positioning system |
| CN112737570A (en) * | 2020-12-15 | 2021-04-30 | 中国科学技术大学 | PAM4 signal clock data recovery method based on software phase-locked loop |
| CN117595865A (en) * | 2023-12-12 | 2024-02-23 | 深圳新港海岸科技有限公司 | Circuit for reducing clock signal jitter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102684653B (en) | 2015-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102684653B (en) | Digital synchronous pulse wireless low-jitter transmission method | |
| CN102820872A (en) | Wireless low-jitter transmission method for digital asynchronous pulse | |
| TWI442739B (en) | A polar receiver using injection locking technique | |
| CN104753548B (en) | Multipath reception device and its signal acceptance method | |
| US9444500B2 (en) | Modulation circuit of digital transmitter, digital transmitter, and signal modulation method | |
| US8908804B2 (en) | Phase interpolator | |
| US11070224B1 (en) | Method and apparatus for implementing multirate SerDes systems | |
| CN106656168B (en) | Clock data recovery device and method | |
| CN104717036A (en) | Differential Manchester decoding circuit and system | |
| CN103986565B (en) | Wireless low-jitter transmission method of clock signal | |
| CN205179051U (en) | Visible light communication's fast signal restore circuit | |
| CN103905015B (en) | A kind of wireless low jitter transmission method of high accuracy number asynchronous pulse | |
| CN101594130B (en) | Slope frequency detection mode based pulse wireless low jitter transmission method | |
| CN106888027B (en) | Transmitter for a radio frequency interconnect RFI | |
| TWI473441B (en) | Receiver, signal demodulation module and demodulation method thereof | |
| CN204180063U (en) | A kind of receiving terminal for unmanned plane ground-to-air wideband communication system | |
| CN202841098U (en) | High-speed input/output interface and receiving circuit thereof | |
| CN103001901B (en) | Integrated circuit high-speed digital interface module based on modified difference pulse code modulation (MDPCM) | |
| CN104378130A (en) | Receiving terminal for unmanned aerial vehicle land-to-air wideband communication system | |
| CN103281073A (en) | Double phase-locked loop device for interphone | |
| CN107968647B (en) | Clock recovery method and system in frequency shift keying regulation system | |
| CN102025452B (en) | Miniature variable rate communication module based on system on chip (SOC) and radio frequency integrated circuit (RFIC), and communication method | |
| CN101702699B (en) | System and method for reducing LO phase errors | |
| CN205356305U (en) | Serial data clock digit phase locking device | |
| CN211063587U (en) | Carrier extraction circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150701 Termination date: 20180529 |