CN103716060A - Clock data recovery circuit - Google Patents
Clock data recovery circuit Download PDFInfo
- Publication number
- CN103716060A CN103716060A CN201410020957.2A CN201410020957A CN103716060A CN 103716060 A CN103716060 A CN 103716060A CN 201410020957 A CN201410020957 A CN 201410020957A CN 103716060 A CN103716060 A CN 103716060A
- Authority
- CN
- China
- Prior art keywords
- sampling
- data
- clock
- sampled
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a clock data recovery circuit which comprises a sampling module and a clock recovery module. The sampling module comprises a sampling control unit and a plurality of sampling units. The sampling units are used for sampling serial data to obtain sampling data. The sampling control unit is used for controlling the sampling units to sample the serial data in sequence, and after all the serial data are sampled by the sampling units, the sampling units are controlled to simultaneously send the sampling data to the clock recovery module. The clock recovery module is used for recovering a clock according to the received sampling data.
Description
Technical field
The present invention relates to a kind of clock data recovery circuit.
Background technology
At present, in serial communication system, clock data recovery circuit (CDR) plays a part crucial in receiver.Clock recovery module in clock data recovery circuit is often operated under high speed.In realization, for making clock data recovery circuit realize high transfer rate, after normally clock and data recovery module being placed on to the modular converter of going here and there and changing.As shown in Figure 1, it is for realizing the structural representation of the clock data recovery circuit of high transfer rate in prior art.Sampling module 110 is sent to modular converter 130 by the serial data of sampling, through modular converter 130, the serial data of high transfer rate is gone here and there and turned and afterwards, the transmission rate of data can decrease, so the parallel data after conversion is carried out to the also corresponding reduction of operating rate of the clock recovery module 120 of clock recovery, thereby avoid the realization difficulty of clock recovery module high workload speed.
But, because clock recovery module is to realize after modular converter, therefore the system delay of whole clock data recovery circuit is larger, lower to the degrees of tolerance of numerous unfavorable factors such as frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of the shake in the intrinsic noise of transmitting terminal, data and noise, transmission channel.
Summary of the invention
The object of the invention is when making clock data recovery circuit realize high transfer rate, reduce the system delay of above-mentioned clock data recovery circuit, improve the degrees of tolerance to the unfavorable factors such as frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of the shake in the intrinsic noise of transmitting terminal, data and noise, transmission channel.
The embodiment of the present invention provides a kind of clock data recovery circuit, and described clock data recovery circuit comprises: sampling module and clock recovery module;
Described sampling module comprises: controlling of sampling unit and a plurality of sampling unit;
Described a plurality of sampling unit, for serial data is sampled, obtains sampled data;
Described controlling of sampling unit is used for controlling described a plurality of sampling unit and successively serial data is sampled, after described a plurality of sampling units are all sampled to serial data, control described a plurality of sampling unit and described sampling data transmitting is delivered to described clock recovery module simultaneously;
The described sampled data recovered clock that described clock recovery module receives for basis.
Further, described clock data recovery circuit also comprises: modular converter; Described controlling of sampling unit also, for after all serial data being sampled when described a plurality of sampling unit samplings, is controlled described a plurality of sampling unit and described sampling data transmitting is delivered to described modular converter simultaneously; Described modular converter is for being converted to parallel data by the described sampled data receiving.
Further, the quantity of described a plurality of sampling units is less than the string of described modular converter and changes multiple.
Further, described clock data recovery circuit also comprises: pretreatment module; Described pretreatment module comprises: difference input coupling circuit and transmission line balanced unit; The serial data that described pretreatment module sends for receiving outside transmitting apparatus, by described difference input coupling circuit and transmission line balanced unit, the serial data receiving is carried out to preliminary treatment, to the pretreated serial data of described sampling module output process, so that described a plurality of sampling unit is sampled to the serial data of described pretreatment module output.
By utilizing clock data recovery circuit provided by the invention, a plurality of sampling units are sampled to serial data successively, after the plurality of sampling unit is all sampled to serial data, sampling data transmitting is delivered to clock recovery module, to avoid clock recovery module to be operated under two-forty simultaneously.Because clock recovery module is before serial-parallel conversion circuit, therefore this clock data recovery circuit is when realizing high transfer rate, can effectively reduce the system delay of clock data recovery circuit, improve the degrees of tolerance to the unfavorable factors such as frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of the shake of the intrinsic noise of transmitting terminal, data and noise, transmission channel.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of clock data recovery circuit of the prior art;
The structural representation of a kind of clock data recovery circuit that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the another kind of clock data recovery circuit that Fig. 3 provides for the embodiment of the present invention;
The structural representation of another clock data recovery circuit that Fig. 4 provides for the embodiment of the present invention.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making all other embodiment that obtain under creative work prerequisite, belong to the scope of protection of the invention.
The clock data recovery circuit that the Fig. 2 of take below provides as the example detailed description embodiment of the present invention.As shown in Figure 2, the structural representation of its a kind of clock data recovery circuit providing for the embodiment of the present invention.
This clock data recovery circuit comprises: sampling module 210, clock recovery module 220 and modular converter 230.
Sampling module 210 comprises: controlling of sampling unit 211 and a plurality of sampling unit 212.
The input of controlling of sampling unit 211 is connected with clock recovery module 220 outputs, and the output of controlling of sampling unit 211 is connected with the first input end of a plurality of sampling units 212 respectively.The output of a plurality of sampling units 212 is connected with modular converter 230 with clock recovery module 220 respectively.
Wherein, each sampling unit 212 in a plurality of sampling units 212 is identical.Each sampling unit 212, for serial data is sampled, obtains sampled data.
Sample to serial data successively for controlling a plurality of sampling units 212 in controlling of sampling unit 211, after a plurality of sampling units 212 are all sampled to serial data, control a plurality of sampling units 212 and sampling data transmitting is delivered to clock recovery module 220 and modular converter 230 simultaneously.
The sampled data recovered clock that clock recovery module 220 receives for basis.
Modular converter 230 is for being converted to parallel data by the sampled data receiving.
Preferably, the quantity of a plurality of sampling units 212 is less than the string of modular converter 230 and changes multiple, to guarantee that the operating rate of the clock recovery module 220 in the clock data recovery circuit shown in Fig. 2 is greater than the operating rate of the clock recovery module in the clock data recovery circuit shown in Fig. 1.
In a concrete example, the transmission rate of sampled data is 1.5GHz, if the string of the modular converter in the clock data recovery circuit shown in employing Fig. 1 and this clock data recovery circuit is also changed multiple into 10, clock recovery module will be operated in 150MHz so.If the number of the clock data recovery circuit shown in employing Fig. 2 and hypothesis sampling unit 212 is 3, the string of modular converter 230 is also changed multiple into 10, and clock recovery module will be operated in 500MHz so.This shows, when adopting identical string and changing the modular converter of multiple, the clock data recovery circuit that the embodiment of the present invention provides not only can avoid clock recovery module to be operated in the transmission rate of sampled data, and compared to the clock recovery module in the clock data recovery circuit shown in Fig. 1, its operating rate also increases.
In addition, as shown in Figure 3, the clock data recovery circuit that the embodiment of the present invention provides can also comprise: pretreatment module 240.
The output of pretreatment module 240 is connected with the second input of a plurality of sampling units 212 respectively.
The serial data that this pretreatment module 240 sends for receiving external equipment, the serial data receiving is carried out to preliminary treatment, to the pretreated serial data of sampling module 210 output process, so that the serial data of 212 pairs of pretreatment module outputs of a plurality of sampling unit is sampled.
Wherein, as shown in Figure 4, pretreatment module 240 comprises: difference input coupling circuit 241 and transmission cable balanced unit 242.By difference input coupling circuit 241 and 242 pairs of serial datas of transmission cable balanced unit, carry out preliminary treatment, to strengthen the physical characteristic consistency of serial data after the transmission of physical channel, be beneficial to reprocessing.
By utilizing clock data recovery circuit provided by the invention, a plurality of sampling units are sampled to serial data successively, after the plurality of sampling unit is all sampled to serial data, sampling data transmitting is delivered to clock recovery module, to avoid clock recovery module to be operated under the transmission rate of sampled data simultaneously.Because clock recovery module is before serial-parallel conversion circuit, therefore this clock data recovery circuit is when realizing high transfer rate, can effectively reduce the system delay of clock data recovery circuit, improve the degrees of tolerance to the unfavorable factors such as frequency difference of non-ideal factor, transmitting terminal and the receiving terminal of the shake of the intrinsic noise of transmitting terminal, data and noise, transmission channel.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range being not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (4)
1. a clock data recovery circuit, is characterized in that, described clock data recovery circuit comprises: sampling module and clock recovery module;
Described sampling module comprises: controlling of sampling unit and a plurality of sampling unit;
Described a plurality of sampling unit, for serial data is sampled, obtains sampled data;
Described controlling of sampling unit is used for controlling described a plurality of sampling unit and successively serial data is sampled, after described a plurality of sampling units are all sampled to serial data, control described a plurality of sampling unit and described sampling data transmitting is delivered to described clock recovery module simultaneously;
The described sampled data recovered clock that described clock recovery module receives for basis.
2. clock data recovery circuit according to claim 1, is characterized in that, described clock data recovery circuit also comprises: modular converter;
Described controlling of sampling unit also, for after all serial data being sampled when described a plurality of sampling unit samplings, is controlled described a plurality of sampling unit and described sampling data transmitting is delivered to described modular converter simultaneously;
Described modular converter is for being converted to parallel data by the described sampled data receiving.
3. clock data recovery circuit according to claim 2, is characterized in that, the quantity of described a plurality of sampling units is less than the string of described modular converter and changes multiple.
4. according to the arbitrary described clock data recovery circuit of claim 1-3, it is characterized in that, described clock data recovery circuit also comprises: pretreatment module;
Described pretreatment module comprises: difference input coupling circuit and transmission line balanced unit;
The serial data that described pretreatment module sends for receiving outside transmitting apparatus, by described difference input coupling circuit and transmission line balanced unit, the serial data receiving is carried out to preliminary treatment, to the pretreated serial data of described sampling module output process, so that described a plurality of sampling unit is sampled to the serial data of described pretreatment module output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020957.2A CN103716060B (en) | 2014-01-15 | 2014-01-15 | Clock data recovery circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410020957.2A CN103716060B (en) | 2014-01-15 | 2014-01-15 | Clock data recovery circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103716060A true CN103716060A (en) | 2014-04-09 |
| CN103716060B CN103716060B (en) | 2016-05-25 |
Family
ID=50408707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410020957.2A Active CN103716060B (en) | 2014-01-15 | 2014-01-15 | Clock data recovery circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103716060B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114337708A (en) * | 2021-12-31 | 2022-04-12 | 苏州兆芯半导体科技有限公司 | Data transmission circuit, method and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090196387A1 (en) * | 2008-02-01 | 2009-08-06 | Matsushita Electric Industrial Co., Ltd. | Instant-acquisition clock and data recovery systems and methods for serial communications links |
| WO2011004580A1 (en) * | 2009-07-06 | 2011-01-13 | パナソニック株式会社 | Clock data recovery circuit |
| CN103036670A (en) * | 2011-12-27 | 2013-04-10 | 龙迅半导体科技(合肥)有限公司 | Clock recovery circuit and parallel output circuit |
| CN103078667A (en) * | 2013-01-23 | 2013-05-01 | 杭州电子科技大学 | Low voltage differential signaling (LVDS) high-speed data transmission method based on cat-5 |
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN203708231U (en) * | 2014-01-15 | 2014-07-09 | 英特格灵芯片(天津)有限公司 | Clock data recovery circuit |
-
2014
- 2014-01-15 CN CN201410020957.2A patent/CN103716060B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090196387A1 (en) * | 2008-02-01 | 2009-08-06 | Matsushita Electric Industrial Co., Ltd. | Instant-acquisition clock and data recovery systems and methods for serial communications links |
| WO2011004580A1 (en) * | 2009-07-06 | 2011-01-13 | パナソニック株式会社 | Clock data recovery circuit |
| CN103036670A (en) * | 2011-12-27 | 2013-04-10 | 龙迅半导体科技(合肥)有限公司 | Clock recovery circuit and parallel output circuit |
| CN103078667A (en) * | 2013-01-23 | 2013-05-01 | 杭州电子科技大学 | Low voltage differential signaling (LVDS) high-speed data transmission method based on cat-5 |
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN203708231U (en) * | 2014-01-15 | 2014-07-09 | 英特格灵芯片(天津)有限公司 | Clock data recovery circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114337708A (en) * | 2021-12-31 | 2022-04-12 | 苏州兆芯半导体科技有限公司 | Data transmission circuit, method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103716060B (en) | 2016-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6433973B2 (en) | Multi-wire single-ended push-pull link with data symbol transition-based clocking | |
| CN104618086B (en) | A kind of single conductor cable data transmission system and method | |
| CN104184451A (en) | Reconfigurable circuit block and exemplary method for configuring the circuit block | |
| CN103944583B (en) | Processing method and device for parallelizing high-speed serial signals in SerDes | |
| TW202127842A (en) | Driver architecture for multiphase and amplitude encoding transmitters | |
| CN103401551B (en) | A kind of method of sampling of SerDes technology high speed serial signal and device | |
| CN203708231U (en) | Clock data recovery circuit | |
| KR20180065119A (en) | Receiver for data communication | |
| CN103716060A (en) | Clock data recovery circuit | |
| CN103037222A (en) | Compression transmission device and method of parallel digital video signal | |
| KR20010015027A (en) | Transmission system, receiver, transmitter and interface device for interfacing a parallel system with a transceiver of the data-strobe type | |
| CN204945791U (en) | A kind of single rotor wing unmanned aerial vehicle flight control system | |
| CN101577598A (en) | Multiple signal multiplexing and demultiplexing methods, devices and systems | |
| CN104717440A (en) | LED transmitting card cascade interface | |
| CN202652394U (en) | Data conversion device | |
| CN101604998A (en) | The method and apparatus of receiving and sampling light signals | |
| CN103686170A (en) | Short-distance multi-channel video transmission method and device | |
| CN104836754A (en) | Method and device for achieving backboard auto-negotiation function by means of high speed Serdes | |
| CN206237547U (en) | A kind of low-power short distance Video transmission system | |
| CN105610509B (en) | A kind of 160M optical transmission devices | |
| CN216979755U (en) | Camera Link relay equipment and system thereof | |
| Vyas et al. | Development of SoC for interfacing avionics units with ARINC 429 bus | |
| CN100533414C (en) | Control system and method of multipath input data | |
| CN202696738U (en) | Video output signal synchronous control device | |
| CN202190349U (en) | Audio and video monitoring system using power line for transmitting signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190709 Address after: 100176 Beijing Daxing District Beijing Economic and Technological Development Zone Ronghua Road No. 10 Building A 9-storey 915 Patentee after: Xin Chuangzhi (Beijing) Microelectronics Co., Ltd. Address before: Room 2701-1, Building 2, Teda Service Outsourcing Park, 19 Xinhuan West Road, Binhai New Development Zone, Tianjin, 300457 Patentee before: International Green Chip (Tianjin) Co.,Ltd. |
|
| TR01 | Transfer of patent right |