CN114363734B - Clock data recovery method, input/output device and optical line terminal - Google Patents
Clock data recovery method, input/output device and optical line terminal Download PDFInfo
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Abstract
A serial deserializer in the input/output device opens an interface for transmitting data sample signals and edge sample signals for an external control module, and the control module realizes phase discrimination to adjust the phase of the clock signals. The clock signal generator in the serial deserializer only needs to generate a local clock signal, and then the control module adjusts the phase of the local clock signal by transmitting the phase difference between the data sample signal and the edge sample signal so as to align the sampling clock signal and the data sample signal, thereby the serial deserializer is not required to have the capability of quick locking, and the implementation difficulty of the serial deserializer is reduced.
Description
Technical Field
The present disclosure relates to the field of optical communications technologies, and in particular, to a clock data recovery method, an input/output device, and an optical line terminal.
Background
A passive optical network (passive optical network, PON) system comprises an optical line terminal (optical line termination, OLT) mounted to a central control station and a plurality of optical network units (optical network unit, ONUs). When the OLT transmits data to the ONUs, a time division multiplexing (time division multiplexing, TDM) mode is adopted, that is, each ONU transmits data to the OLT on a time slice allocated by the OLT. Time slicing may be referred to as time slots or bursts (bursts). For the OLT, since different ONUs transmit data to the OLT through different time slices, and clock phases adopted by the different ONUs may be different, and the data transmitted by the ONUs to the OLT does not include a clock signal, a Serializer/Deserializer (SerDes) in the OLT is required for clock recovery.
The scheme adopted at present for realizing clock recovery is as follows: one is to perform clock recovery by means of oversampling; the other is provided with an arbitrated feedback equalizer (decision feedback equalizer, DFE) by a clock data recovery (clock data recovery) circuit included in the SerDes. The clock recovery time by means of oversampling is short, but when the data rate is high, the oversampling requires a rate multiple times higher than the data rate, resulting in incapacity. By adopting the DFE mode, the DFE needs to track data bits of a plurality of past symbol intervals (UI) to predict the sampling threshold of the current bit, and the clock recovery time is long.
Disclosure of Invention
The application provides a clock data recovery method, an input/output device and an optical line terminal, which are used for reducing recovery time.
In a first aspect, an embodiment of the present application provides an input/output device, which may be applied to, but not limited to, an optical line terminal OLT, and includes an edge sampling module, a data sampling module, a clock signal generator, and a control module; the edge sampling module is used for obtaining a first edge sample signal according to the sampling clock signal; the data sampling module is used for collecting a first data sample signal according to the sampling clock signal; the clock signal generator is used for generating a local clock signal and receiving a phase control signal from the control module, and carrying out phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal; the control module is used for detecting the phase difference between the first edge sample signal and the first data sample signal and generating a phase control signal according to the phase difference.
In the scheme, the phase discrimination is realized through the control module to adjust the phase of the clock signal, so that the alignment of the sampling clock signal and the data sample signal is achieved, the serial deserializer is not required to have the capability of quick locking, and the realization difficulty of the serial deserializer is reduced. In addition, the time of clock recovery required by the clock recovery circuit itself is reduced, and whether the CDR is operating normally is not required by detecting an unbinding lock (unbinding lock).
In one possible design, the edge sampling module, the data sampling module, and the clock signal generator are located inside the serial deserializer, and the control module is located outside the serial deserializer. In the above design, the clock recovery circuit inside the serial deserializer does not need to have a fast locking capability, and the clock signal generator only generates a local clock signal. The control module outside the serial de-serializer is used for controlling the phase of the local clock signal generated by the clock signal generator in the serial de-serializer, so that the hardware modification of the serial de-serializer is not needed, and the control logic in the serial de-serializer in the OLT is used for realizing the phase control, so that the method is simple and effective.
In one possible design, a clock signal generator includes a phase locked loop and a phase interpolator; a phase locked loop for generating a local clock signal; and the phase interpolator is used for receiving the phase control signal from the control module and carrying out phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal. In the above design, a simple and efficient clock signal generator is provided, which operates in a local clock mode through a phase locked loop, and then adjusts the phase through a phase difference device.
As an example, a phase locked loop may operate in a local clock mode to generate a local clock signal.
In one possible design, the first edge sample signal and the first data sample signal are carried on a time slice of the first optical network unit; and the control module is further used for storing the phase value of the sampling clock signal of the time slicing where the first optical network unit is located when the sampling clock signal of the time slicing where the first optical network unit is located currently meets the sampling requirement of the first data sample signal according to the phase difference of the first edge sample signal and the first data sample signal.
In one possible design, the control module is further configured to indicate, on a time slice of the first optical network unit, that the phase value of the sampling clock signal generated by the clock signal generator is the stored phase value.
By the design, when the optimal sampling phase of a time slicing is determined, the optimal sampling phase is included, and when the time slicing is reached later, the stored phase value is sampled, so that the clock recovery rate is improved.
In one possible design, an edge sampling module includes an edge sampler and a first series-to-parallel converter;
the edge sampler is used for carrying out edge sampling on the received service signal according to the sampling clock signal to obtain a second edge sample signal;
the first serial-to-parallel converter is used for carrying out serial-to-parallel conversion on the second edge sample signal to obtain a first edge sample signal.
In one possible design, the data sampling module includes a data sampler and a second series-to-parallel converter;
the data sampler is used for carrying out data sampling on the received service signal according to the sampling clock signal to obtain a second data sample signal;
and the second serial-to-parallel converter is used for carrying out serial-to-parallel conversion on the second data sample signal to obtain a first data sample signal.
In a second aspect, an embodiment of the present application provides a clock data recovery method, including: acquiring a first edge sample signal and a first data sample signal; a phase difference between the first edge sample signal and the first data sample signal is detected, a phase control signal is generated based on the phase difference, the phase control signal is used for controlling a phase of a sampling clock signal, and the sampling clock signal is used for sampling the first edge sample signal and the first data sample signal.
In one possible design, the first edge sample signal and the first data sample signal are carried on a time slice of the first optical network unit; the method further comprises the steps of: when the phase difference between the first edge sample signal and the first data sample signal meets the set phase difference value, the phase value of the sampling clock signal of the time slicing where the first optical network unit is located is stored.
In one possible design, the method further comprises: on time slicing of the first optical network unit, the phase value of the sampling clock signal is controlled to be the saved phase value.
In one possible design, obtaining the first edge sample signal includes: collecting a second edge sample signal according to the sampling clock signal, and carrying out serial-parallel conversion on the first edge sample signal to obtain a first edge sample signal; acquiring a first data sample signal, comprising: and acquiring a second data sample signal according to the sampling clock signal, and carrying out serial-parallel conversion on the first data sample signal to obtain the second data sample signal.
In a third aspect, an embodiment of the present application provides an optical line terminal OLT, which includes the input-output device of the first aspect or any one of the designs of the first aspect.
Drawings
Fig. 1 is a schematic diagram of an optical communication system architecture according to an embodiment of the present application;
fig. 2 is a schematic diagram of allocation of an uplink light-emitting timeslot of an optical network device in an embodiment of the present application;
fig. 3 is a schematic structural diagram of an input/output device 300 according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another input-output device 300 according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of yet another input/output device 300 according to an embodiment of the present application;
FIG. 6 is a flowchart of a clock data recovery method according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an apparatus 700 according to an embodiment of the present application.
Detailed Description
The embodiment of the application can be applied to an optical communication system, and the optical communication system can be a time division multiplexing (time division multiplexing, TDM) passive optical network (passive optical network, PON) system. The TDM PON system may be a gigabit-capable PON (GPON) system, an Ethernet Passive Optical Network (EPON) system, a 10G ethernet passive optical network (10 Gb/s ethernet passive optical network, 10G-EPON) system, a 10G-capable passive optical network (10 gigabit-capable passive optical network, XG-PON) system, or a 10G-capable symmetric passive optical network (10-gigabit-capable symmetric passive optical network, XGs-PON) system, or the like.
The optical communication system includes at least an OLT and a plurality of ONUs (or optical network terminals (optical network terminal, ONTs)), and the OLT communicates with the plurality of ONUs, respectively. The OLT and the ONU may be connected by an optical passive device such as an optical fiber or an optical splitter. Referring to fig. 1, the OLT communicates with n ONUs through a Splitter (Splitter). In fig. 1, n ONUs are ONU1, ONU2, … …, and ONUn, respectively. Split may also be referred to as an optical Splitter. Split may be a fiber optic junction device having multiple inputs and multiple outputs for coupling, branching, and distributing optical signals.
It should be understood that in the embodiments of the present application, the transmission direction of data or an optical signal carrying data from the OLT to the ONU/ONT is referred to as the downstream direction. The transmission direction of data or data-carrying optical signals from an ONU/ONT to an OLT is called upstream direction. The OLT transmits data or an optical signal to the ONU (downstream direction) may be a broadcast method, and the ONU transmits data or an optical signal to the OLT (upstream direction) may be a unicast method.
The transmission of data between the OLT and the ONUs employs time-division multiplexing techniques, such as time-division multiple access (time division multiple access, TDMA).
In the uplink transmission, as shown in fig. 2, each dynamic bandwidth allocation (dynamically bandwidth assignment, DBA) period (uplink transmission time) is divided into a plurality of time slots Ti (i=1, 2,3, … …, … …), and as shown in fig. 2, only one ONU is arranged to transmit an uplink signal to the OLT in a packet manner in each time slot, and each ONU sequentially transmits the uplink signal in the order specified by the OLT. It should be noted that an ONU may be allocated one or more time slots. Time slots may also be referred to as Unit Intervals (UIs), time slices, or the like.
For the OLT, the OLT includes a controller and a receiver. The controller may be implemented by a medium access control (media access control, MAC) chip. The MAC chip is used for realizing that the OLT completes the control of the physical layer and the link layer. The receiver is used for receiving the uplink signal from the ONU. Other components or devices, such as a transmitter, may also be included in the OLT, and the devices included in the OLT are not specifically limited in this application.
When the controller controls the receiver to receive the upstream signals from the plurality of ONUs, the upstream signals from different ONUs are received through different time slots, so to speak, mixed together for reception. While the clock phases of different ONUs may be different, the receiver is required to have the ability to lock (or clock recover) quickly for each slot. The scheme adopted at present for realizing clock recovery is as follows: one is by means of oversampling, such as by 4-8 times oversampling. The other is clock recovery capability through SerDes in the receiver. For example, the clock data recovery (clock data recovery, CDR) circuit included in SerDes is required to be provided with an arbitrated feedback equalizer (decision feedback equalizer, DFE). The clock recovery time by means of oversampling is short, but when the data rate is high, the oversampling requires a rate multiple times higher than the data rate, resulting in incapacity. By adopting the mode of the DFE, the DFE needs to track data bits of a plurality of symbol intervals in the past to predict the sampling threshold of the current bit, if the CDR does not work normally, the clock phase needs to be increased or decreased by 1/4UI, and then the data bits of a plurality of UIs are re-tracked to predict the sampling threshold of the current bit, so that the clock recovery time is longer.
Based on this, an input-output device 300 is provided in the embodiment of the present application. The input-output device 300 may be applied to an OLT. The functions of the input-output device may be implemented by a field programmable gate array (field programmable gate array, FPGA), an application specific integrated circuit (application specific integrated circuit, ASIC), or a central processing unit (central processing unit, CPU), or the like. It should be noted that, the FPGA, ASIC, CPU, or the like may be used only to implement the functions of the input-output device, and may also be used to implement other functions, such as a control function, which is not specifically limited in the embodiments of the present application.
The input/output device in the embodiment of the present application may be named as other names, such as clock data recovery device, and the naming manner is not specifically limited in the embodiment of the present application.
Referring to fig. 3, a schematic structure of an input/output device 300 is shown.
The input-output device 300 includes an edge sampling (edge sampling) module 301, a data sampling (data sampling) module 302, a clock signal generator 303, and a control module 304. The edge sampling module 301 is coupled to a clock signal generator 303 and a control module 304, respectively. The data sampling module 302 is coupled to a clock signal generator 303 and a control module 304, respectively. The control module 304 is coupled to the clock signal generator 303.
The edge sampling module 301 is configured to obtain a first edge sample signal according to a sampling clock signal. Wherein the first edge sample signals are parallel signals.
In a possible implementation, an edge sampling (edge sampling) module 301, a data sampling (data sampling) module 302, and a clock signal generator 303 in the input/output device may be located in a SerDes, and the control module 304 may be implemented by control logic of an FPGA or an ASIC.
In one example, the edge sampling module 301 may include an edge sampler 3011 and a first serial-to-parallel (parallel to serial, P2S) converter 3012, as shown in fig. 4. The edge sampler 3011 is configured to perform edge sampling on the received service signal according to the sampling clock signal to obtain a second edge sample signal. Further, the edge sampler 3011 transmits the second edge sample signal to the first P2S converter 3012, and the first P2S converter 3012 performs serial-parallel conversion on the second edge sample signal to obtain a first edge sample signal.
The data sampling module 302 is configured to sample the clock signal to acquire a first data sample signal. Wherein the first edge sample signals are parallel signals.
In another example, the data sampling module 302 may include a data sampler 3021 and a second P2S converter 3022, see fig. 4. The data sampler 3021 is configured to perform data sampling on the received service signal according to the sampling clock signal to obtain a second data sample signal. Further, the data sampler 3021 transmits the second data sample signal to the second P2S converter 3022, and the second P2S converter 3022 performs serial-parallel conversion on the second data sample signal to obtain the first data sample signal.
The clock signal generator 303 is configured to generate a local clock signal, and receive a phase control signal from the control module 304, and perform phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal.
In one possible example, the clock signal generator 303 may include a phase locked loop (phase locked loop, PLL) 3031 and a phase interpolator 3032. The PLL operates in a local clock mode, i.e., does not perform a frequency locking operation, for generating a local clock signal. The PLL used to generate the local clock signal may be replaced by other devices that are capable of operating in a local clock mode and generating the local clock signal. The phase interpolator 3032 is configured to receive the phase control signal from the control module 304, so as to perform phase adjustment on the local clock signal according to the phase control signal to obtain the sampling clock signal.
The control module 304 is configured to detect a phase difference between the first edge sample signal and the first data sample signal, and generate a phase control signal according to the phase difference.
As a possible implementation, the control module 304 may be implemented by a processing unit or a control unit. For example, the processing unit may include one or a processor, which may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated circuit (application specific integrated circuit, ASIC), or CPU, or other programmable logic device, discrete gate or transistor logic device, or the like, and/or other devices that provide the functionality described above. Illustratively, the control unit may include one or more of a media access control (media access control, MAC), a micro control unit (microcontroller unit, MCU), a digital signal processor (digital signal processor, DSP), or a microprocessor unit (micro processor unit, MPU) or the like for implementing control functions.
When the input-output device is applied to the controller, the control module may be implemented by a user logic unit in the controller.
The control module 304 has a phase discrimination function, and determines to adjust the phase of the local clock signal to obtain the sampling clock signal through the phase difference between the edge sample signal and the data sample signal, so that the edge sample signal and the data sample signal can be synchronous and keep a fixed phase relation, and the sampling clock signal can be aligned with the data sample signal.
As an example, taking the transition between binary symbols received by control module 304 as an example. The data sample signals at time (n-1) and time (n), identified as "Dn-1" and "Dn", may have a logical value of 0 or 1. Dn-1 and Dn are data sample signals collected by the data sampling module 302 according to the sampling clock signal. The time delay between Dn-1 and Dn is one Unit Interval (UI), and the data samples D n-1 and Dn are most easily detected in the center of the corresponding UI and most accurately detected in the center of the UI, and if detected at the edges of the UI, detection errors can occur. Between time (n-1) and time (n), the logical value of the data sample signal may remain unchanged, or may change from 0 to 1 or from 1 to 0. Between every two data sample signals, the control module 304 receives the edge sample signal E [ n-1] acquired according to the sampling clock signal sent by the edge sampling module 301, where the edge sample signal acquisition time is between D [ n-1] and D [ n ]. For example, if Dn-1 and Dn are at the skip edges and the edge sample signal is at the UI center, the phase of the sampling clock signal needs to be adjusted, i.e. the sampling phase of the edge sample signal is the optimal sampling phase of the data sample signal. If Dn-1 and Dn are in the UI center and the edge sample signal is at the skip edge, the receiving end can optimally detect the data samples D n-1 and Dn, and the sampling phases of D n-1 and Dn are the optimal sampling phases of the data sample signal.
In connection with the structure of the input-output device shown in fig. 4, fig. 5 shows a schematic diagram of signal flow transmission.
In the embodiment of the application, the PLL is operated in the local clock mode, and the phase discrimination is realized through the control module to adjust the phase of the clock signal, so that the alignment of the sampling clock signal and the data sample signal is achieved, the serial deserializer is not required to have the capability of quick locking, and the realization difficulty of the serial deserializer is reduced. In addition, the time of clock recovery required by the clock recovery circuit itself is reduced, and whether the CDR is operating normally is not required by detecting an unbinding lock (unbinding lock).
Because different time slices are distributed to different ONUs, clock phases adopted by the different ONUs may be different, and therefore, through the scheme provided by the embodiment of the application, the clock phases on the time slices adopted by the different ONUs are adjusted, and the time length of clock recovery is reduced for each time slice. As an example, for ONU1, the traffic signal sent by ONU1 is carried in time-slicing 1 allocated for ONU 1. After detecting the first edge sample signal and the first data sample signal of the traffic signal of ONU1, the control module 304 stores the phase value, such as the phase value AA, of the sampling clock signal currently corresponding to the time slice where the first optical network unit is located when determining, according to the phase difference between the first edge sample signal and the first data sample signal, that the sampling clock signal currently corresponding to the time slice where the first optical network unit is located meets the sampling requirement of the data sample signal. Also for ONU2, the traffic signal sent by ONU2 is carried on time-slicing 2 allocated for ONU 2. After detecting the first edge sample signal and the first data sample signal of the traffic signal of the ONU2, the control module 304 determines, according to the phase difference between the first edge sample signal and the first data sample signal, that the current sampling clock signal for the time slice 2 where the first optical network unit is located meets the sampling requirement of the data sample signal, and stores the phase value, such as the phase value BB, of the current sampling clock signal for the time slice where the first optical network unit is located. Based on this, the control module 304, upon determining that time slice 1 is reached, sends an indication to the phase interpolator 3032 indicating that the phase value of the local clock signal of the PLL is AA. For example, when it is determined that time slice 1 is reached, the control module 304 sends a phase control signal 1 to the phase interpolator 3032, controlling the phase value of the local clock signal of the PLL to AA. When time slicing 2 is reached, a phase control signal 2 is sent to phase interpolator 3032, controlling the phase value of the local clock signal of the PLL to be BB. Thus phase discrimination and lock time can be further reduced.
Based on the same inventive concept as the input-output device, the embodiments of the present application provide a clock data recovery method. See fig. 6.
S601, acquiring a first edge sample signal and a first data sample signal;
s602, detecting a phase difference between the first edge sample signal and the first data sample signal, and generating the phase control signal according to the phase difference, wherein the phase control signal is used for controlling the phase of the sampling clock signal, and the sampling clock signal is used for sampling the first edge sample signal and the first data sample signal.
In one possible implementation, the first edge sample signal and the first data sample signal are carried on a time slice of a first optical network unit;
the method further comprises the steps of:
when the phase difference between the first edge sample signal and the first data sample signal is determined to meet a set phase difference value, the phase value of the sampling clock signal of the time slicing where the first optical network unit is located is stored.
In one possible implementation, the phase value of the sampling clock signal is controlled to be the saved phase value on a time slicing of the first optical network unit.
In one possible implementation, acquiring the first edge sample signal includes:
collecting a second edge sample signal according to the sampling clock signal, and carrying out serial-parallel conversion on the first edge sample signal to obtain the first edge sample signal;
acquiring a first data sample signal, comprising:
and acquiring a second data sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first data sample signal to obtain a second data sample signal.
In some embodiments, the controller is configured to perform the method flow shown in FIG. 6. As an example, fig. 7 is a schematic structural diagram of another apparatus 700 provided in an embodiment of the present application, for implementing the method flow shown in fig. 6. The apparatus 700 comprises a communication interface 701, a processor 702 and a memory 703. The communication interface 701 is used to receive traffic data from an ONU. The memory 703 is used to store data. In one form, the processor 702 may include input-output devices to implement the embodiments described above. Alternatively, the memory 703 may store the input-output devices as instructions that are executed by the processor 702.
The processor 702 is any combination of hardware, middleware, firmware, or software. The processor 702 includes any combination of one or more CPU chips, cores, FPGAs, ASICs, or DSPs. The memory 703 includes any combination of disks, tape drives, or solid state drives. The apparatus 700 may use the memory 703 as an overflow data storage device to store programs that are executed by the apparatus 700 when such programs are selected and to store instructions and data that are read by the apparatus 700 during program execution. The memory 703 may be volatile or non-volatile and may be any combination of read-only memory (rom), random-access memory (ram), ternary content-addressable memory (ternary content-addressable memory), or static RAM (static RAM).
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (11)
1. The input/output device is characterized by comprising an edge sampling module, a data sampling module, a clock signal generator and a control module; wherein, the liquid crystal display device comprises a liquid crystal display device,
the edge sampling module is used for obtaining a first edge sample signal according to a sampling clock signal;
the data sampling module is used for collecting a first data sample signal according to the sampling clock signal;
the clock signal generator is used for generating a local clock signal, receiving a phase control signal from the control module, and carrying out phase adjustment on the local clock signal according to the phase control signal to obtain the sampling clock signal;
the control module is used for detecting the phase difference between the first edge sample signal and the first data sample signal and generating the phase control signal according to the phase difference;
the input/output device comprises a serial deserializer, the edge sampling module, the data sampling module and the clock signal generator are positioned inside the serial deserializer, and the control module is positioned outside the serial deserializer.
2. The apparatus of claim 1, wherein the clock signal generator comprises a phase locked loop and a phase interpolator;
the phase-locked loop is used for generating the local clock signal;
the phase interpolator is configured to receive a phase control signal from the control module, and perform phase adjustment on the local clock signal according to the phase control signal to obtain the sampling clock signal.
3. The apparatus of any of claims 1-2, wherein the first edge sample signal and the first data sample signal are carried on a time slice of a first optical network unit;
the control module is further configured to determine, according to the phase difference between the first edge sample signal and the first data sample signal, when the sampling clock signal currently aiming at the time slicing where the first optical network unit is located meets the sampling requirement for the first data sample signal, save the phase value of the sampling clock signal currently aiming at the time slicing where the first optical network unit is located.
4. The apparatus of claim 3, wherein the control module is further configured to indicate, on the time slicing of the first optical network unit, that the phase value of the sampling clock signal generated by the clock signal generator is the saved phase value.
5. The apparatus of any of claims 1,2, 4, wherein the edge sampling module comprises an edge sampler and a first series-to-parallel converter;
the edge sampler is used for carrying out edge sampling on the received service signal according to the sampling clock signal to obtain a second edge sample signal;
the first serial-to-parallel converter is configured to perform serial-to-parallel conversion on the second edge sample signal to obtain a first edge sample signal.
6. The apparatus of any of claims 1,2, 4, wherein the data sampling module comprises a data sampler and a second series-to-parallel converter;
the data sampler is used for carrying out data sampling on the received service signal according to the sampling clock signal to obtain a second data sample signal;
the second serial-to-parallel converter is configured to perform serial-to-parallel conversion on the second data sample signal to obtain a first data sample signal.
7. A clock data recovery method, applied to a control module, comprising:
obtaining a first edge sample signal and a first data sample signal from a serializer;
detecting a phase difference between the first edge sample signal and the first data sample signal, and generating a phase control signal according to the phase difference, wherein the phase control signal is used for controlling a phase of a sampling clock signal adopted by the serial deserializer, and the sampling clock signal is used for sampling the first edge sample signal and the first data sample signal by the serial deserializer.
8. The method of claim 7, wherein the first edge sample signal and the first data sample signal are carried on a time slice of a first optical network unit;
the method further comprises the steps of:
and when the sampling clock signal of the time slicing where the first optical network unit is located currently meets the sampling requirement of the first data sample signal according to the phase difference of the first edge sample signal and the first data sample signal, saving the phase value of the sampling clock signal of the time slicing where the first optical network unit is located currently.
9. The method as recited in claim 8, further comprising:
and controlling the phase value of the sampling clock signal to be the stored phase value on the time slicing of the first optical network unit.
10. The method according to any of claims 7-9, wherein obtaining a first edge sample signal comprises:
collecting a second edge sample signal according to the sampling clock signal, and carrying out serial-parallel conversion on the first edge sample signal to obtain the first edge sample signal;
acquiring a first data sample signal, comprising:
and acquiring a second data sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first data sample signal to obtain a second data sample signal.
11. An optical line termination OLT comprising an input-output device according to any of claims 1-6.
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