CN108322214A - A kind of clock and data recovery circuit of no reference clock input - Google Patents
A kind of clock and data recovery circuit of no reference clock input Download PDFInfo
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- CN108322214A CN108322214A CN201810036978.1A CN201810036978A CN108322214A CN 108322214 A CN108322214 A CN 108322214A CN 201810036978 A CN201810036978 A CN 201810036978A CN 108322214 A CN108322214 A CN 108322214A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Abstract
The present invention relates to a kind of clock and data recovery circuits of no reference clock input, which includes high-speed sampler, binary system phase discriminator, counter, comparator, pseudobinary searching algorithm, digital filter, voltage adjuster, current steering DAC and Low phase noise broadband VCO.This clock and data restoring circuit use double ring architecture, carry out fast frequency locking by coarse adjustment frequency-locked loop first, ensure that sample clock frequency is approximately equal to the rate of input data.After the completion of frequency-locked loop is adjusted, circuit enters accurate adjustment locking phase and adjusts loop realization PGC demodulation, ensures sampling clock along the centre position for being in data, accurately to recover clock and data information.This control mode can realize wide speed range work, and be not required to external reference clock, have stronger shake tolerance and quick locking ability.
Description
Technical field
The present invention relates to a kind of clock data recovery circuit of no reference clock input, especially one kind passing through pseudobinary
The clock data recovery circuit of searching algorithm and digital FILTER TO CONTROL, belongs to high-speed interface circuit design field.
Background technology
Clock data recovery circuit is the key modules for realizing high-speed serial communication.It recovers clock from serial data
Signal finds the optimum sampling point of data by the adjusting of circuit, by recovering data when resetting to data, eliminates number
According to the shake introduced in transmission process, performance has vital influence to entire high speed serial transmission system.When existing
Clock inputs CDR structures, needs to be pre-configured with message transmission rate, limits the flexibility of products application.
Existing PLL structures input CDR structures without reference clock, as shown in Figure 5 a.It is inputted by frequency discriminator FD630
Data frequency and VCO640 frequencies of oscillation compare, and after the completion of waiting for Frequency Locking, phase adjusted is carried out by phase discriminator PD610.
When circuit initialization or phase loop losing lock, the control signal that FD630 is generated passes through charge pump CP650 and loop filter
LF660 makes the concussion frequency of VCO640 be adjusted towards input data rate direction, when frequency difference falls into the energy of phase tracking loop
When within the scope of power, the frequency of oscillation that PD610 adjusts VCO640 is consistent with input data frequency.
Using Fig. 5 a design schemes, there are problems that two, first, Frequency tracking loop and phase tracking loop may be mutually
Interference influences circuit locking；Second is that when being consecutive identical pattern due to input data, intersymbol interference may cause FD630 can not
It is normally carried out adjusting.To overcome problem above, when design, will ensure that frequency-locked loop bandwidth will be much smaller than phase-locked loop bandwidth, thus
Cause circuit locking time longer.
For optimization system locking time, the design scheme of Fig. 5 b, frequency-locked loop bandwidth and phase-locked loop bandwidth may be used
Can be separately adjustable, but two sets of independent charge pump CP650, filter LF660 will increase a large amount of chip areas, to production
Cost requirement is higher.
Invention content
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of applied to high-speed interface circuit without reference
The clock data recovery circuit of clock input utilizes counter and pseudobinary searching algorithm accelerating circuit in coarse adjustment frequency locking process
Frequency is adjusted, and overcomes circuit loss of lock；In accurate adjustment phase locking process traditional analog filter is substituted using digital filter
Reduce chip area, increases circuit robustness.It works in wide speed range for guarantee circuit, devises Low phase noise broadband VCO,
To meet the application requirement of distinct interface agreement.
The object of the invention is achieved by following technical solution：
A kind of clock and data recovery circuit inputted without reference clock applied to high-speed interface circuit is provided, including thick
Adjust frequency locking module and accurate adjustment phase module；
Data DATA of the coarse adjustment frequency locking module to the input using voltage controlled oscillator VCO output clock as clock acquisition
It is counted respectively with the data DATA of input, compares the size of count value, if it is less, the output of voltage controlled oscillator VCO is turned up
The frequency of clock reduces the frequency of the output clock of voltage controlled oscillator VCO, until voltage controlled oscillator VCO is defeated if identical
The frequency change for going out clock is less than given threshold, the frequency of locking output clock；
The accurate adjustment phase module is using four phase clocks of voltage controlled oscillator VCO output as clock signal, acquisition input
Data DATA, phase relation differentiation is carried out to the data of acquisition, adjusts the phase of the output clock of voltage controlled oscillator VCO.
Preferably, the coarse adjustment frequency locking module includes the first high-speed sampler, buffer, the first counter circuit, second
Counter circuit, comparator, pseudobinary search algorithm module, voltage adjuster, current steering DAC and voltage controlled oscillator VCO；
One of four phase clocks of the clock end connection voltage controlled oscillator VCO output of first high-speed sampler, acquire input
Data DATA；
Buffer is to the data DATA of input into row buffering；
First counter circuit counts the data DATA in buffer；
Data after second counter circuit samples high-speed sampler count；
Comparator compares the count value size of the first counter circuit and the second counter circuit, when more than when, export DN
Effectively；When equal to when, output UP it is effective；
Pseudobinary search algorithm module includes adder, the first register, the second register and a shift register；
The value of shift register moves to right one after being added for the value of the first register and the second register, output to current steering DAC；Work as DN
When effective, the value of shift register is assigned to the second register；When UP is effective, the value of shift register is assigned to the first register；
When difference≤1 of the value of the first register and the second register, the value of shift register is no longer updated；
Value of the current steering DAC based on shift register adjusts output voltage VCTRLSize；
Voltage adjuster is to voltage VCTRLV is exported after carrying out steady pressure treatmentDDVCOTo voltage controlled oscillator VCO；
Voltage controlled oscillator VCO is based on input voltage VDDVCOSize adjustment frequency of oscillation and export four phase clocks phase.
Preferably, the accurate adjustment phase module includes the second high-speed sampler, digital filtering module and binary system phase discriminator；
Second high-speed sampler includes four samplers, and the four of voltage controlled oscillator VCO output are respectively adopted in four samplers
Phase clock acquires the data DATA of input, and the data of four samplers samples are sent to binary system mirror as clock signal
Phase device；
Binary system phase discriminator judges four phase clock phases with the phase relation of data DATA for advanced or lag；
Digital filtering module carries out cumulative filtering to the phase relation that binary system phase discriminator exports, and generates filtering signal extremely
Current steering DAC；
Filtering signal of the current steering DAC also based on digital filter output adjusts output voltage VCTRLSize.
Preferably, voltage controlled oscillator VCO phase is divided into n adjustment section, when phase relation is advanced, digital filtering
Module output valve control voltage controlled oscillator VCO adjusts a section backward；When phase relation is lag, digital filtering module
Output valve control voltage controlled oscillator VCO adjusts forward a section.
Preferably, the sampling rate of the first high-speed sampler and the second high-speed sampler is more than 10Gbps.
Preferably, the first high-speed sampler includes sense amplifier and RS latch, after the data DATA amplifications of input
It is latched；
Second high-speed sampler includes the identical sampler of four structures, includes each that sense amplifier and RS are latched
Device, to being latched after the data DATA amplifications of input.
Preferably, current steering DAC includes thermometer coding decoder, multiple current sources and switch arrays；It is posted based on displacement
The value of storage controls the output of preceding 6 current sources by switch arrays；The filtering signal of digital filter output is compiled through thermometer
2 after being controlled by switch arrays after code decoder decoding4The output of a current source.
Preferably, digital filtering module includes that voting machine and wave digital lowpass filter are in series.
Preferably, when the difference of the value of the first register and the second register≤1, the second high-speed sampler is started to work.
Preferably, the initial value of the first register is " 100000 ", and the initial value of the second register is minimum value.
The present invention has the following advantages that compared with prior art：
(1) present invention is by pseudobinary searching algorithm, accelerating circuit locking, and avoids existing two phase-locked loop structure
Loss of lock improves the reliability of circuit；
(2) present invention substitutes analog filter by digital filter, saves chip area, reduces the complexity of design
Degree；
(3) present invention controls VCO frequencies of oscillation using current steering DAC, and the smaller phase noise of output frequency is widened
Circuit work frequency range.
(4) the Key Circuit module in the present invention, such as counter, comparator, filter are all digital circuit, can be adopted
It is realized with the mode of logic synthesis, improves the robustness of circuit.
(5) present invention judges that the frequency of oscillation of VCO is by comparing the count value to the data after input data and sampling
It is no consistent with input data frequency, without using frequency discriminator, charge pump and analog filter, save chip area.
Description of the drawings
The clock and data recovery circuit structure diagram that Fig. 1 inputs for no reference clock；
Fig. 2 is 10 digit counters output schematic diagram of input when being random number；
Fig. 3 is pseudobinary searching algorithm operating diagram；
Fig. 4 is this structural schematic diagram of digital filter；
Fig. 5 a are the first example of clock and data recovery circuit structure diagram without reference clock input based on PLL structures,
Fig. 5 b are the second example of clock and data recovery circuit structure diagram without reference clock input based on PLL structures；
Fig. 6 is 10 current steering DAC circuit structure diagrams；
Fig. 7 is Low phase noise broadband VCO and voltage adjuster structure chart.
Specific implementation mode
The specific implementation mode of the present invention is described in detail below in conjunction with the accompanying drawings.
The present invention provides a kind of clock and data recovery circuit inputted without reference clock applied to high-speed interface circuit,
In conjunction with Fig. 1, the circuit includes high-speed sampler 150, high-speed sampler 210, buffer 110, binary system phase discriminator 220, counter
120,160, comparator 130, digital filter 230, current steering DAC 190, power manager 180, Low phase noise broadband are counted
VCO170 and pseudobinary search algorithm module 140.
It includes two parts of sense amplifier and RS latch that high-speed sampler 150 is identical with 210 structures, and sampling rate is big
In 10Gbps, the ends Clk connect the output of VCO, and when Clk is low, sampling unit is in reset state, while RS latch is in
Hold mode, output maintain laststate constant；When Clk is high, sampling unit is in running order, sensitive amplifier circuit warp
Over-sampling, regeneration and judgement three phases, the output signal with certain pulsewidth is zoomed by the differential signal of input, rear class
RS latch circuits identify the pulse width signal, and it is quickly latched, and one full swing differential signal of final output realizes sampling
Function.The data DATA of the acquisition input of high-speed sampler 150, is sampled according to the frequency of oscillation of VCO.
Buffer 110 is to the data DATA of input into row buffering.
Counter circuit is cascaded by ten triggers, for calculating the rising edge of input data and after over-sampling
The rising edge number of data；Counter circuit 120 counts data DATA, and counter circuit 160 is to high-speed sampler 150
Data after sampling are counted.Referring to Fig. 2, counting output is carried out to the data of input.
Comparator circuit 130 is used for comparing two size of data of counter 120 and counter 160, and exports UP and DN
Signal gives pseudobinary search algorithm module 140；When the counting of counter 160 counted less than counter 120, illustrate VCO
Frequency of oscillation is excessively slow, and output state is that DN is effective at this time；When the counting of counter 120 is equal to the counting of counter 160, explanation
VCO frequencies of oscillation are more than or equal to message transmission rate, and output state is that UP is effective at this time；
In conjunction with Fig. 3, there are one 450, three registers 410/420/440 of adder for pseudobinary search algorithm module 140
It is formed with a shift register 430.According to the control signal of input UP and DN, control switch CUPDAnd CDNDOn off state,
And then the value of output register C is constantly adjusted by adder and shift register, as U-D≤1, sign bit Init460 becomes
When being high, pseudobinary search algorithm module will be closed.Register U410 is defaulted as " 100000 ", and register D420 is defaulted as most
Small value " 0 " (0 represents binary number 000000), when DN is effective, switch CUPDIt closes, the value of register C is that (U+D)/2 is assigned to
Register D so that the value of register C increases.The value of output register C is to current steering DAC 190.
In conjunction with Fig. 6, current steering DAC 190 uses 10 current steer segmental structures, including thermometer coding decoder, electricity
Stream source and switch arrays, biasing circuit.Current steering DAC 190 is by digital control position DCO [9：0] V is converted toCTRL, and pass through voltage
Adjuster 180 generates the V of pure stabilizationDDVCO, and then by adjusting conducting resistance reach control VCO170 frequency of oscillation mesh
, wherein DCO [9:0] high six are KVCO gain control bits in, receive the value of output register C, control current supply switch pipe
760 break-make realizes the KVCO wide range of frequencies tuning of multi gear position；Low four are phase controlling position, receive digital filter output
Value, thermometer-code is translated by thermometer coding decoder, the break-make of control current supply switch pipe 770.
The V that Low phase noise broadband VCO170 receiving voltages adjuster 180 exportsDDVCO, by control delay cell 820 and voltage-controlled
Delay cell 830 forms, the V that voltage adjuster 180 exportsDDVCOThe size control frequency of oscillation of delay cell 820 and voltage-controlled
Delay cell 830 exports the phase of four phase clocks.
High-speed sampler 210 includes four samplers, and exporting four road orthogonal clocks by VCO170 carries out input data
Sampling.Four road orthogonal clocks are respectively adopted as clock in four samplers, are sampled to data DATA, then in each sampling
Period, two sampling units are used for sampling the serial data of input, other two sampling unit is used for sampling input serial data
Date conversion edge, obtain two groups of data and two groups of date conversion edges, output selects to adopt to binary system phase discriminator 220
It is exported as DATAOUT after one group of recovery waveform in the serial data of collection, while exporting the corresponding clock of this group of serial data
Signal.
Binary system phase discriminator 220 is used to judge the phase relation of input clock and data.It is realized to defeated by four d type flip flops
Enter data cache, between each sampling period is using date conversion edge and date conversion edge two side data
Relationship obtains the relationship between the sampling clock phase and the date conversion edge of every group of date conversion edge, and is converted into number
Word phase discrimination signal is exported to digital filter 230；The sampling clock phase of every group of date conversion edge and the data conversion
Relationship between edge includes advanced, lag or same phase, exists with mutually only theoretical, practical is indeterminate state.
In conjunction with Fig. 4, digital filtering module 230 is in series by voting machine 510 and wave digital lowpass filter 520.Each
A sampling period is filtered two groups of digital phase detection signals of input, generates and adjusts relationship comprising sampling clock phase
Four filtering signal (Din [3:0]), VCO170 output phase adjustings are carried out by controlling low four of current steering DAC 190；VCO
Phase be divided into 64 adjustment sections the phase of VCO is adjusted into a section backward when to be advanced, when for lag when, will
The phase of VCO adjusts forward a section.
The clock and data recovery circuit of no reference clock input is made of coarse adjustment frequency-locked loop and accurate adjustment phase-locked loop, slightly
It is exactly the rate of the frequency of oscillation and input data that adjust Low phase noise broadband VCO170 to adjust the major function that frequency-locked loop is completed
It is almost the same.After Frequency Locking, circuit enters phase locking process, and finally recovers clock and data-signal.
In circuit initialization procedure or when accurate adjustment phase-locked loop losing lock, clock and data recovery circuit enters frequency locking mould
Formula.When circuit initializes, register U410 is defaulted as " 100000 ", and register D420 is defaulted as minimum value " 0 ", and (0 represents two
System number 000000).Caused by data dithering is larger when accurate adjustment phase-locked loop losing lock, the value and register of register U410
The value of D420 is determined by the current state of register.
Because of T=U+D, the shifted register of the value of adder T450 430 moves to right one, so shift register 430 is deposited
The value of storage is (U+D)/2.High six (D [9 that shift register 430 passes through control current steering DAC 190:4]) come in wider rate
The frequency of oscillation of adjustment Low phase noise broadband VCO170 in range, and export four road quadrature clock signals.High-speed sampler 150 is logical
It crosses Low phase noise broadband VCO170 output quadrature clock signals and resampling is carried out to input data, give digit counter 120/
Data rising edge number after 160 statistic samplings.After 1024 sampling periods, digital comparator 130 is by comparing meter
Device 120 and 160 size of counter are counted to characterize the magnitude relationship of VCO frequencies of oscillation and input data rate, if counter 120
Value be more than value then UP=1, the DN=0 of counter 160, illustrate that VCO output frequencies are less than data rate；Otherwise illustrate that VCO is defeated
Go out frequency and is more than data rate.
As UP=1, switch Cupd is effective, indicates that the value of shift register 430 is less than desired value, then register U410
Value is substituted with the value of shift register 430, and otherwise the value of register D420 is substituted with the value of shift register 430.Update
Shift register 430 afterwards controls the frequency of oscillation of VCO170 again through current steering DAC 190, repeats above procedure, until
The value of register C440 reaches best, and the value of register U410 and the value of register D420 are almost the same at this time, i.e. U-D≤1, symbol
Number position Init460 becomes high, indicates that coarse adjustment frequency locking is completed, and close pseudobinary search module 140, circuit enters accurate adjustment locking phase
Pattern.
After clock and data recovery circuit enters accurate adjustment facies model, high-speed sampler 210 exports four tunnels by VCO170
Orthogonal clock samples input data.In each sampling period, two sampling units are used for sampling the serial number of input
According to other two sampling unit is used for sampling the date conversion edge of input serial data, obtains two groups of data and two groups of data
Switching edge, and last group of data that two groups of date conversion edges and a upper sampling period sample are exported to binary system
Phase discriminator 220.Binary system phase discriminator 220 is realized by four d type flip flops to the three samples of input data, then passes through at " 3 points
Sampling " principle judge phase transition along with the phase relation of sampling clock (leading, lag, identical), each phase discriminator 220 produces
Raw two phase demodulation information, four phase discriminators 220 in parallel just will produce eight phase demodulation information.To reduce rear class digital circuit
Operating rate, each two period are accumulative primary by voting machine to phase demodulation information result.In the phase of two sampling period internal clocks
Position can be summarized as 5 kinds of situations for by sampled data, i.e. two cycle clocks all TA data, a cycle when
In clock TA data and another cycle clock data do not overturn, in two cycle clocks data do not overturn, a cycle when
Data are not overturn in clock and another cycle clock falls behind data and two cycle clocks and falls behind data.Four groups of numbers are obtained altogether
According to；Phase demodulation decision signal is obtained finally by phase decision circuit.
Voting machine module 510 sums eight phase demodulation information in two periods by adder, determines continuous two
Phase is advanced or lag in a period.Wave digital lowpass filter 520 is realized using digital accumulator in analog filter
The integrating function of capacitance will filter out voting machine output phase and change too fast point, maintains output to the 4 of 190 module of current steering DAC
Big saltus step does not occur in circuit stability for position phase adjusted information, to make entire loop-locking.
10 current steering DACs 190 use segmental structure, high six Din [9 from the aspect of comprehensive performance and area two:4]
Structure, low four Din [3 are weighed using binary digit:0] thermometer decoder structure is used.Current steer type DAC190 speed is fast, switch
Parasitic parameter influence is small, and chip area is small, and input digital code often increases 1LSB, and just there are one corresponding switch conductions, defeated in this way
Go out and input always directly proportional, ensure that the monotonicity of DAC.Binary digit weighs structure input data Din [9:4] by pseudobinary
Searching algorithm 140 controls, and as KVCO Linear Controls position, multi gear position KVCO can be arranged to realize that wide range of frequencies is adjusted.Temperature
Meter decoding structure input data D [3:0] it is controlled by the output of digital filter 230, is KVCO integration controls position, to output phase
It is adjusted.
In conjunction with Fig. 7, Low phase noise broadband VCO170 is made of delay cell 820 and voltage-controlled delay unit 830, frequency tune
Section controls delay cell 820 by voltage adjuster 180 and realizes.It can guarantee by the voltage adjuster 180 of high PSRR
VCO170 exports four phase quadrature clock signals of high-performance low phase noise.
The above, best specific implementation mode only of the invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the known technology of professional and technical personnel in the field.
Claims (10)
1. a kind of clock and data recovery circuit of no reference clock input, which is characterized in that including coarse adjustment frequency locking module and essence
Adjust phase module；
Data of the coarse adjustment frequency locking module to the input using voltage controlled oscillator VCO (170) output clock as clock acquisition
DATA and the data DATA of input are counted respectively, compare the size of count value, if it is less, voltage controlled oscillator VCO is turned up
The frequency for exporting clock reduces the frequency of the output clock of voltage controlled oscillator VCO, until voltage controlled oscillator VCO if identical
Output clock frequency change be less than given threshold, locking output clock frequency；
The accurate adjustment phase module is using four phase clocks of voltage controlled oscillator VCO (170) output as clock signal, acquisition input
Data DATA, phase relation differentiation is carried out to the data of acquisition, adjusts the phase of the output clock of voltage controlled oscillator VCO.
2. the clock and data recovery circuit of no reference clock input according to claim 1, it is characterised in that：It is described thick
It includes the first high-speed sampler (150), buffer (110), the first counter circuit (120), the second counter to adjust frequency locking module
Circuit (160), comparator (130), pseudobinary search algorithm module (140), voltage adjuster (180), current steering DAC
(190) and voltage controlled oscillator VCO (170)；
One of four phase clocks that the clock end connection voltage controlled oscillator VCO (170) of first high-speed sampler (150) exports, acquisition
The data DATA of input；
Buffer (110) is to the data DATA of input into row buffering；
First counter circuit (120) counts the data DATA in buffer (110)；
Data after second counter circuit (160) samples high-speed sampler (150) count；
Comparator (130) compares the count value size of the first counter circuit (120) and the second counter circuit (160), when big
Yu Shi, output DN are effective；When equal to when, output UP it is effective；
Pseudobinary search algorithm module (140) includes adder (450), the first register (410), the second register (420)
With a shift register (430)；The value of shift register (430) is the first register (410) and the second register (420)
Value moves to right one after being added, output to current steering DAC (190)；When DN is effective, the value of shift register (430) is assigned to second
Register (420)；When UP is effective, the value of shift register (430) is assigned to the first register (410)；When the first register
(410) and difference≤1 of the value of the second register (420) value of shift register (430), is no longer updated；
The value that current steering DAC (190) is based on shift register (430) adjusts output voltage VCTRLSize；
Voltage adjuster (180) is to voltage VCTRLV is exported after carrying out steady pressure treatmentDDVCOTo voltage controlled oscillator VCO (170)；
Voltage controlled oscillator VCO (170) is based on input voltage VDDVCOSize adjustment frequency of oscillation and export four phase clocks phase.
3. the clock and data recovery circuit of no reference clock input according to claim 2, it is characterised in that：The essence
It includes the second high-speed sampler (210), digital filtering module (230) and binary system phase discriminator (220) to adjust phase module
Second high-speed sampler (210) includes four samplers, and it is defeated that voltage controlled oscillator VCO (170) is respectively adopted in four samplers
Four phase clocks gone out acquire the data DATA of input, and the data of four samplers samples are sent to two as clock signal
System phase discriminator (220)；
Binary system phase discriminator (220) judges four phase clock phases with the phase relation of data DATA for advanced or lag；
The phase relation that digital filtering module (230) exports binary system phase discriminator (220) carries out cumulative filtering, and generates filtering
Signal is to current steering DAC (190)；
The filtering signal that current steering DAC (190) is also based on digital filter (230) output adjusts output voltage VCTRLSize.
4. the clock and data recovery circuit of no reference clock input according to claim 3, it is characterised in that：It is voltage-controlled to shake
It swings device VCO (170) phase and is divided into n adjustment section, when phase relation is advanced, digital filtering module (230) output valve
It controls voltage controlled oscillator VCO (170) and adjusts a section backward；When phase relation is lag, digital filtering module (230)
Output valve controls voltage controlled oscillator VCO (170) and adjusts a section forward.
5. the clock and data recovery circuit of no reference clock input according to claim 2 or 3, it is characterised in that：The
The sampling rate of one high-speed sampler (150) and the second high-speed sampler (210) is more than 10Gbps.
6. the clock and data recovery circuit of no reference clock input according to claim 3 or 4, it is characterised in that：The
One high-speed sampler (150) includes sense amplifier and RS latch, to being latched after the data DATA amplifications of input；
Second high-speed sampler (210) includes the identical sampler of four structures, includes each that sense amplifier and RS are latched
Device, to being latched after the data DATA amplifications of input.
7. the clock and data recovery circuit of no reference clock input according to claim 3 or 4, it is characterised in that：Electricity
It includes thermometer coding decoder, multiple current sources and switch arrays to flow rudder DAC (190)；Value based on shift register (430)
The output of preceding 6 current sources is controlled by switch arrays；The filtering signal of digital filter (230) output is translated through thermometer coding
2 after being controlled by switch arrays after code device decoding4The output of a current source.
8. the clock and data recovery circuit of no reference clock input according to claim 3 or 4, it is characterised in that：Number
Word filter module (230) includes that voting machine (510) and wave digital lowpass filter (520) are in series.
9. the clock and data recovery circuit of no reference clock input according to claim 3 or 4, it is characterised in that：When
When the difference of the value of the first register (410) and the second register (420)≤1, the second high-speed sampler (210) is started to work.
10. the clock and data recovery circuit of no reference clock input according to claim 3 or 4, it is characterised in that：The
The initial value of one register (410) is " 100000 ", and the initial value of the second register (420) is minimum value.
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| CN201810036978.1A CN108322214A (en) | 2018-01-15 | 2018-01-15 | A kind of clock and data recovery circuit of no reference clock input |
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| CN109787615A (en) * | 2018-12-29 | 2019-05-21 | 光梓信息科技（上海）有限公司 | Frequency discriminator, PAM4 data clock frequency locking means, restoration methods and circuit |
| CN111049540A (en) * | 2018-10-11 | 2020-04-21 | 三星显示有限公司 | Transition detector and clock data recovery unit including the same |
| CN111211883A (en) * | 2018-11-22 | 2020-05-29 | 三星电子株式会社 | Electronic circuit configured to adjust sampling timing for recovering data |
| CN113141181A (en) * | 2020-01-17 | 2021-07-20 | 中国电子科技集团公司第二十四研究所 | Digital control circuit and clock data recovery circuit of clock data recovery circuit |
| CN113507286A (en) * | 2021-06-16 | 2021-10-15 | 深圳市傲科光电子有限公司 | Method, apparatus and computer readable storage medium for determining clock signal |
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| CN109120393A (en) * | 2018-09-27 | 2019-01-01 | 深圳市傲科光电子有限公司 | A kind of low power consuming clock data recovery circuit and receiver |
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| CN111049540B (en) * | 2018-10-11 | 2022-07-05 | 三星显示有限公司 | Transition detector and clock data recovery unit including the same |
| CN111211883A (en) * | 2018-11-22 | 2020-05-29 | 三星电子株式会社 | Electronic circuit configured to adjust sampling timing for recovering data |
| CN109787615B (en) * | 2018-12-29 | 2023-04-14 | 光梓信息科技（上海）有限公司 | Frequency discriminator, PAM4 clock data frequency locking method, recovery method and circuit |
| CN109787615A (en) * | 2018-12-29 | 2019-05-21 | 光梓信息科技（上海）有限公司 | Frequency discriminator, PAM4 data clock frequency locking means, restoration methods and circuit |
| CN113141181A (en) * | 2020-01-17 | 2021-07-20 | 中国电子科技集团公司第二十四研究所 | Digital control circuit and clock data recovery circuit of clock data recovery circuit |
| CN113141181B (en) * | 2020-01-17 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Digital control circuit and clock data recovery circuit of clock data recovery circuit |
| CN113507286A (en) * | 2021-06-16 | 2021-10-15 | 深圳市傲科光电子有限公司 | Method, apparatus and computer readable storage medium for determining clock signal |
| CN113886300A (en) * | 2021-09-23 | 2022-01-04 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
| CN113886300B (en) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
| CN115102545A (en) * | 2022-08-25 | 2022-09-23 | 苏州联讯仪器有限公司 | Data clock recovery system and method |
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