CN114142852B - High-speed burst mode clock data recovery circuit suitable for PAM4 signal - Google Patents
High-speed burst mode clock data recovery circuit suitable for PAM4 signal Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
Abstract
The invention discloses a high-speed burst mode clock data recovery circuit suitable for a PAM4 signal, which comprises: the device comprises a sampling decision circuit, a phase discrimination circuit, a majority voting circuit, an oversampling logic unit, a digital phase control module, a digital loop filter, a quadrature clock generation circuit and a phase synthesis module; and the over-sampling logic unit controls the switching of the loop locking mode between the over-sampling mode and the phase discrimination locking mode, performs over-sampling on the PAM4 data signal quantization result and outputs a control signal. The invention adds an over-sampling locking loop, quickly samples the initial coding sequence, determines approximate clock phase, and realizes low-jitter receiving by matching with a locking mechanism with a binary phase discriminator locking loop and a smaller bandwidth. According to the invention, the sampler originally used for edge sampling and the partial sampler decoded by PAM4 are multiplexed by the sampling unit in the oversampling mode, no additional sampling circuit is needed, and the loop is quickly locked while the system power consumption is reduced.
Description
Technical Field
The invention belongs to the field of optical communication and integrated circuits, and particularly relates to a high-speed burst mode clock data recovery circuit suitable for a PAM4 signal.
Background
Clock and Data Recovery (CDR) circuits play a crucial role in serial communication systems. In a high-speed serial communication system, only serial data is transmitted on a channel, and a clock signal is not transmitted, and a data receiving end receives a data signal and performs clock recovery. The clock data recovery circuit is used for extracting a clock from a data signal according to a reference clock, and then the recovered clock is used for retiming received data to obtain a data receiving result which meets the specification.
The data rate is improved by using the PAM4 signal, and the receiver simultaneously phase-discriminates the three decoded data signals, so that the phase-discrimination density is improved. As shown in FIG. 1, PAM4 CDR in the prior art is mostly composed of Bang phase detector (BBPD for short) and digital loop filter, such as the architecture published by Changzhi Yu et al in the Journal of IEEE Journal of Solid-State Circuits in 2020. However, in order to reduce the jitter of the recovered clock signal, the loop bandwidth generally needs to be set small to meet the communication standard requirements, which makes it necessary for a long time to elapse for the system to be stable. However, in the burst-mode PAM4 CDR, a fast loop tracking response needs to be achieved.
Under a non-Return-to-Zero (None-Return-to-Zero) NRZ data format, a commonly used method for realizing burst mode reception is a Gated-VCO, and an input signal is injected into an oscillator through a logic gate to realize fast locking. Another common method is the Time-to-Digital Converter, which converts the phase error into a Digital signal and performs fast phase locking. Both methods require digital operations using logic gates and are therefore only suitable for NRZ format. One way to achieve a fast loop tracking response is to use an oversampling mode. However, for PAM4 data recovery in high-speed burst mode, a high-speed, higher resolution ADC unit is required, which increases the complexity of circuit design and increases circuit power consumption.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a high-speed burst mode clock data recovery circuit and a receiver suitable for a PAM4 signal, and aims to solve the problem that complexity and power consumption are greatly increased due to the fact that an ADC circuit is introduced under an oversampling mode in the prior art.
The invention provides a high-speed burst mode clock data recovery circuit suitable for a PAM4 signal, which comprises: the phase detection circuit comprises a sampling decision circuit, a phase discrimination circuit, a majority voting circuit, an oversampling logic unit, a digital phase control module, a digital loop filter, a quadrature clock generation circuit and a phase synthesis module; a first input end of the sampling decision circuit is used for receiving PAM4 data signals input from the outside, and a second input end of the sampling decision circuit is connected to an output end of the phase synthesis module and is used for carrying out digital quantization on input levels according to a set reference voltage and outputting a quantization result; the input end of the phase discrimination circuit is connected to the output end of the sampling decision circuit and is used for receiving the quantized data signal and the clock signal output by the phase synthesis module and generating a leading voltage signal and a lagging voltage signal of the clock relative to the data signal according to the phase relation between the quantized data signal and the clock signal; the input end of the majority voting circuit is connected to the output end of the phase detection circuit and is used for outputting a unique leading voltage signal and a unique lagging voltage signal of a clock relative to a data signal after output data of the phase detection circuit are combined; the input end of the oversampling logic unit is connected to the output end of the sampling decision circuit, and the oversampling logic unit is used for controlling the switching of the loop locking mode between the oversampling mode and the phase discrimination locking mode, oversampling the PAM4 data signal quantization result and outputting a control signal; a first input end of the digital phase control module is connected to an output end of the majority voting circuit, and a second input end of the digital phase control module is connected to an output end of the oversampling logic unit and used for outputting a digital logic signal according to a phase discrimination result output by the majority voter and the control signal; the input end of the digital loop filter is connected to the output end of the digital phase control module and is used for performing low-pass filtering processing on the digital logic signal; the orthogonal clock generating circuit is used for receiving an externally input reference clock signal, filtering an external clock and generating two orthogonal clock signals; a first input end of the phase synthesis module is connected to an output end of the digital loop filter, and a second input end of the phase synthesis module is connected to an output end of the quadrature clock generation circuit, and is configured to shift phases of two paths of quadrature clocks according to the digital logic signal, and send the phase-shifted clock signal to the sampling decision circuit and the phase discriminator.
Further, the sampling decision circuit includes: the sampler comprises a first sampler A, a second sampler B, a third sampler C, a fourth sampler D, a first D trigger DFF _ A, a second D trigger DFF _ B, a third D trigger DFF _ C, a fourth D trigger DFF _ D and four groups of two-stage inverters; the first input end of the first sampler A, the first input end of the second sampler B, the first input end of the third sampler C and the first input end of the fourth sampler D are all used for connecting external input signals, the second input end of the first sampler A is connected with a first reference voltage REF1, the second input end of the second sampler B is connected with a second reference voltage REF2, the second input end of the third sampler C is connected with a third reference voltage REF3, and the second input end of the fourth sampler D is connected with the second reference voltage REF2; a first input terminal of the first D flip-flop DFF _ a is connected to an output terminal of the first sampler a, a first input terminal of the second D flip-flop DFF _ B is connected to an output terminal of the second sampler B, a first input terminal of the third D flip-flop DFF _ C is connected to an output terminal of the third sampler C, and a first input terminal of the fourth D flip-flop DFF _ D is connected to an output terminal of the fourth sampler D; a second input terminal of the first D flip-flop DFF _ a, a second input terminal of the second D flip-flop DFF _ B, and a second input terminal of the third D flip-flop DFF _ C are all used for connecting a data sampling clock, and an output terminal of the fourth D flip-flop DFF _ D is used for connecting an edge sampling clock; the input end of the first group of two-stage inverters is connected to the output end of the first D flip-flop DFF _ A, and the output end of the first group of two-stage inverters is used for outputting data A; the input end of the second group of two-stage inverters is connected to the output end of the second D flip-flop DFF _ B, and the output end of the second group of two-stage inverters is used for outputting data B; the input end of the third group of two-stage inverters is connected to the output end of the third D flip-flop DFF _ C, and the output end of the third group of two-stage inverters is used for outputting data C; the input end of the fourth group of two-stage inverters is connected to the output end of the fourth D flip-flop DFF _ D, and the output end of the fourth group of two-stage inverters is used for outputting an edge a; wherein the first reference voltage REF1 is smaller than the second reference voltage REF2, and the second reference voltage REF2 is smaller than the third reference voltage REF3.
Further, the phase detection circuit includes: a Bang phase discriminator; the Bang phase discriminator comprises an exclusive-or gate A and an exclusive-or gate B; the first input end of the exclusive-OR gate A is connected to the output end of the fourth group of two-stage inverters, the second input end of the exclusive-OR gate A is connected to the output end of the second group of two-stage inverters, and the exclusive-OR gate A outputs a clock lead signal which is used for adjusting the clock phase and realizing phase locking; and the first input end of the exclusive-OR gate B is connected to the output end of the second group of two-stage inverters, the second input end of the exclusive-OR gate B is connected with data of an upper sampling point, and the exclusive-OR gate B outputs a clock lag signal for adjusting the clock phase and realizing phase locking.
Still further, the oversampling logic unit includes: the over-sampling control logic module is used for realizing phase locking logic in an over-sampling mode and judging whether the phase locking module is in a close locking state according to a phase result: if the digital phase control module is in a close locking state, the oversampling control logic module gives the value of the internal register to the digital phase control module.
Further, the oversampling control logic module includes: NOT gate, OR gate, NOR gate, AND gate and register; the input end of the NOT gate is connected with a third sampling signal Sample [2], the output end of the NOT gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with a second sampling signal Sample [1], the output end of the OR gate is connected with the first input end of the AND gate, the second input end of the AND gate is connected with a first sampling signal Sample [0], and the output end of the AND gate is connected with the first input end of the register and used for outputting a phase advance signal; the first input end of the NOR gate is connected with the second sampling signal Sample [1], the second input end of the NOR gate is connected with the first sampling signal Sample [0], the output end of the NOR gate is connected with the second input end of the register and used for outputting a phase lag signal, and the register is used for outputting a phase control signal according to the phase lag signal and the phase lead signal.
Further, the phase synthesis module includes: four groups of phase interpolation units; the two groups of phase interpolation units are used for generating clocks with four phases of 0 degree, 90 degrees, 180 degrees and 270 degrees as data sampling clocks which are respectively supplied to each sampling channel; the other two groups of phase interpolation units are used for generating clocks with four phases of 45 degrees, 135 degrees, 225 degrees and 315 degrees as edge sampling clocks.
The invention also provides an oversampling logic control method based on the high-speed burst mode clock data recovery circuit, which comprises the following steps:
(1) Judging whether the three input phase decision signals are 110, if so, controlling the CDR to enter a BBPD locking mode; if not, entering the step (2);
(2) Judging whether the three input phase judgment signals are 111, 011 or 001, if so, controlling to reduce the sampling phase and lagging the clock; if not, entering the step (3);
(3) And (3) judging whether the three input phase decision signals are 100 or 000, if so, controlling to increase the sampling phase, otherwise, not needing phase operation and returning to the step (1).
The invention also provides a PAM4 receiver, the PAM4 receiver comprising: the device comprises a clock data recovery circuit, a PAM4 decoding circuit and an analog combiner; the clock data recovery circuit is used for recovering data from an input signal by extracting a correct sampling phase; the PAM4 decoding circuit is used for decoding the data A, the data B and the data C output from the sampler into NRZ coded binary codes MSB1 and LSB1; the analog combiner is used for combining MSB1, MSB2, MSB3 and MSB4 of 4 sampling channels with 1/4 rate into a series MSB; and the LSB1, LSB2, LSB3 and LSB4 of the 4 sampling channels are fused into one LSB in series connection; the clock data recovery circuit is characterized by being the high-speed burst mode clock data recovery circuit.
In the existing BBPD loop locking scheme, razavi et al have demonstrated a direct correlation between the loop bandwidth and the locking time. If a faster lock time is required, then a greater loop bandwidth is required. However, the CDR loop bandwidth is generally required to be not too large in communication standards, so that it is difficult to achieve fast locking by the conventional BBPD loop locking scheme. Compared with the prior art, the technical scheme provided by the invention introduces the oversampling locking mode on the basis of the BBPD loop locking mode by multiplexing the data sampling unit and changing the phase of edge sampling, avoids the compromise between the loop bandwidth and the phase locking time in the conventional BBPD loop locking scheme, and can realize rapid phase locking in a Preamble stage (Preamble). Meanwhile, after the over-sampling fast loop locking, the BBPD locking mode can be switched, so that the CDR circuit can keep the advantage of low bandwidth in the prior art.
Drawings
Fig. 1 is a diagram of a PAM4 CDR system of the prior art.
Fig. 2 is a diagram of a PAM4 CDR system in burst mode in an example of the invention.
Fig. 3 is a specific circuit configuration diagram of a sampling decision circuit and a phase detector in an example of the present invention.
Fig. 4 is a detailed circuit configuration diagram of a digital phase control module in an example of the present invention.
Fig. 5 is a specific circuit configuration diagram of a digital loop filter in an example of the present invention.
Fig. 6 is a specific circuit configuration diagram of the quadrature clock generating circuit in the example of the present invention.
Fig. 7 is a schematic diagram of the low power consumption fast oversampling principle in an embodiment of the present invention.
Fig. 8 is a conventional result of three sample data in the case of loop lock.
Fig. 9 is a result of three sampling data in the case where the sampling signal leads the data.
Fig. 10 is a result of three sample data in the case where two sample signals lead data.
Fig. 11 is a result of three sampled data in the case where two sampled signals lag data.
Fig. 12 is a logic block diagram of an oversampling logic unit.
Fig. 13 is a specific circuit configuration diagram of the oversampling logic unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Based on the CDR formed by a Bang phase discriminator and a digital loop filter adopted in the prior art, the invention introduces an oversampling logic unit, realizes equivalent oversampling by 3 times without introducing a new sampling channel by changing the phase of edge sampling and a multiplexing data sampling unit, and introduces a BBPD locking mode and an oversampling locking mode to ensure that PAM4 CDR in a burst mode can be quickly locked and improve the jitter characteristic of a recovered clock.
As shown in fig. 2, the basic architecture of the high-speed burst mode clock data recovery circuit suitable for the PAM4 signal provided by the present invention is as follows: the device comprises a sampling decision circuit 1, a phase discrimination circuit 2, a majority voting circuit 3, a digital phase control module 5, a digital loop filter 6, a quadrature clock generation circuit 7 and a phase synthesis module 8. To achieve fast lock, the present invention introduces a second set of fast lock loops comprising: an oversampling logic unit 4;
the sampling decision circuit 1 is used for receiving an externally input PAM4 data signal and a clock signal output by the phase synthesis module, setting reference voltages to be 0.25A,0.5A and 0.75A according to the maximum swing amplitude A of the signal, carrying out digital quantization on an input level, and sending a quantization result to the phase discriminator;
the phase discrimination circuit 2 is used for receiving the quantized data signal and the clock signal output by the phase synthesis module, generating a leading voltage signal and a lagging voltage signal of the clock relative to the data signal according to the phase relation between the quantized data signal and the clock signal, and sending the clock data phase error voltage signal to the majority voting circuit;
the majority voting circuit 3 is used for receiving the output of the phase discriminator, merging the output data of the phase discriminator, outputting a unique leading voltage signal and a unique lagging voltage signal of the clock relative to the data signal, and sending a phase error result to the digital phase control module;
the over-sampling logic unit 4 is used for controlling the switching of the loop locking mode between an over-sampling mode, namely a fast locking mode and a phase discriminator locking mode, performing over-sampling on an input PAM4 data quantization result and outputting a control signal to the digital phase control module;
the digital phase control module 5 is used for receiving the phase discrimination result output by the majority voter and receiving the control signal sent by the oversampling logic unit, and outputting the control logic signal to the phase synthesis module or the digital loop filter according to the different loop modes (the oversampling loop mode or the BBPD loop mode);
the digital loop filter 6 is used for receiving the digital logic signal sent by the digital phase control module, performing low-pass filtering processing on the digital logic signal and sending output to the phase synthesis module;
the orthogonal clock generating circuit 7 is used for receiving an externally input reference clock signal, filtering an external clock, generating two orthogonal clock signals and sending the generated two I/Q clock signals to the phase synthesis module;
and the phase synthesis module 8 is configured to receive the logic control signal transmitted by the digital phase control module after being filtered by the digital loop filter and the two orthogonal clocks, shift the phases of the two clocks through the control logic, and send the phase-shifted clock signal to the sampling decision circuit.
The high-speed burst mode clock data recovery circuit provided by the invention has the advantages that the oversampling locking mode is introduced on the basis of the BBPD loop locking mode by multiplexing the data sampling unit and changing the phase of edge sampling, the loop locking speed is increased, and meanwhile, lower power consumption can be realized at the same locking speed.
In the embodiment of the present invention, as shown in fig. 3, the sampling decision circuit 1 includes: four samplers, four D flip-flops DFFs and four groups of two-stage inverters; the sampler is used for comparing an input level with a reference level and outputting a comparison result.
The sampler A, the sampler B and the sampler C in the four samplers are used for PAM-4 signal sampling, and the sampler D is used for edge sampling. The input ends of the four samplers are connected with input signals, and if the input signals are at the highest level (for example, 600 mV), the threshold levels of the samplers A, B, C and D are respectively 0.25A,0.5A,0.75A and 0.5A; the outputs of the four samplers are connected to the D flip-flops, denoted as DFF _ a, DFF _ B, DFF _ C, and DFF _ D, respectively. The sampling clocks of DFF _ a, DFF _ B, and DFF _ C are all connected to the data sampling clock, and the sampling clock of DFF _ D is connected to the edge sampling clock. The outputs of the four D triggers are connected with two cascaded inverters, the outputs of the four groups of inverters are respectively called data A, data B, data C and edge A, wherein the data A, the data B and the data C are respectively sampling results of input signals at the time t, and the edge A is a sampling result of the input signals at the time 1.125 t.
In the embodiment of the present invention, as shown in fig. 3, the phase detection circuit 2 includes: a Bang phase discriminator; the Bang phase discriminator consists of two high-speed exclusive-or gates. The first input end of the exclusive-OR gate A is connected to the output end of the fourth group of two-stage inverters, the second input end of the exclusive-OR gate A is connected to the output end of the second group of two-stage inverters, and the output of the exclusive-OR gate A is a clock lead signal. The first input end of the exclusive-OR gate B is connected to the output end of the second group of two-stage inverters, the second input end of the exclusive-OR gate B is connected with data of a previous sampling point, and the output of the exclusive-OR gate B is a clock lag signal. The clock lead or lag information generated by the exclusive-or gate can be used for adjusting the phase of the system clock and realizing phase locking.
In the embodiment of the invention, the input of the oversampling logic unit 4 is connected after the sampling decision circuit 1, and the output is connected with the digital phase control module 5, so that an oversampling locking loop except for a BBPD locking loop is introduced, and a data sampling unit, an edge sampling unit and a phase synthesis module of the BBPD locking loop are multiplexed in an oversampling mode.
When the CDR is initially started, the CDR is preset in an oversampling mode, and at this time, only the sampling decision circuit 1, the oversampling logic unit 4, the digital phase control module 5, and the phase synthesis module 8 are in a working state in a loop of the CDR, and the phase discrimination circuit 2, the majority voting circuit 3, and the digital loop filter 6 are all in a closed state; when the oversampling logic unit 4 determines that the system is close to being locked, the oversampling logic unit 4 closes the module, and starts the phase discrimination circuit 2, the majority voting circuit 3, and the digital loop filter 6 to form a second phase locked loop. The locked loop has the characteristic of small loop bandwidth, and can bring better jitter performance.
In the embodiment of the present invention, as shown in fig. 4, the digital phase control module 5 includes: the clock frequency division module is realized as a D trigger with input and output short circuits, the clock input is a CDR master clock, and the output signal is connected with the register group. The register group is synchronous trigger logic and receives the clock lag or clock lead information of the phase discriminator, and meanwhile, the register group can receive the value of the oversampling register.
In the embodiment of the present invention, as shown in fig. 5, the digital loop filter 6 includes: differential path gain G prop Integral path gain G int Integrator 1/(1-Z) -1 ) Integral path delay Z -Nint And an accumulator Σ; wherein, the input digital signal is connected with the differential path gain and the integral path gain simultaneously; the output of the integral path gain is connected with the input of the integrator; the output of the integrator is connected with the delay of an integral path; the output of the differential path gain and the output of the integral path delay are connected to the input of an accumulator, the output of which is the output digital signal of the digital loop filter.
In the embodiment of the present invention, as shown in fig. 6, the quadrature clock generating circuit 7 includes: the filter network consists of a capacitor C and a resistor R; the input clock signal is a differential signal and is marked as in + and in-; the output clock signal is an orthogonal differential signal and is marked as I +, Q +, I-, and Q-; the A end of the resistor R1 is connected with in +, and the B end is connected with I +; the upper pole plate of the capacitor C1 is connected with in +, and the lower pole plate is connected with Q +; the A end of the resistor R2 is connected with the ground, and the B end of the resistor R2 is connected with the Q +; the upper polar plate of the capacitor C2 is connected with the ground, and the lower polar plate is connected with the I < - >; the A end of the resistor R3 is connected with in-, and the B end is connected with I-; the upper pole plate of the capacitor C3 is connected with the in-, and the lower pole plate is connected with the Q-; the A end of the resistor R4 is connected with the ground, and the B end is connected with the Q < - >; the upper plate of the capacitor C4 is connected with the ground, and the lower plate is connected with the I +.
In the embodiment of the present invention, the phase synthesis module 8 includes four sets of phase interpolation units; the four groups of phase interpolation units are mutually independent and are controlled by different digital control signals. Two groups of the four groups of phase interpolation units are responsible for sampling clock phase generation, and because the output of each group of phase interpolation units is a differential signal, clocks with four phases of 0 degree, 90 degrees, 180 degrees and 270 degrees can be generated as data sampling clocks which are respectively supplied to each sampling channel. Similarly, the other two sets of phase interpolation units will generate four phases of 45 degrees, 135 degrees, 225 degrees, 315 degrees clocks as the edge sampling clocks.
In the embodiment of the present invention, when in the burst mode, the oversampling logic unit 4 and the control logic control loop are in the oversampling mode, and fig. 7 shows a schematic diagram of the low-power consumption fast oversampling principle adopted in the present invention, in the example of the present invention, according to the IEEE specification, in the 28Gbuad PAM-4 burst mode, the Preamble is to alternate 0 and 1 with the NRZ format with the same height as PAM4 data. Thus at 28Gbps, the signal can be equivalent to a 14GHz clock. In the 28Gbaud 4 time-interleaved sample channel CDR, the sampling master clock is 7GHz. If we divide the phase of the 7GHz clock by 12, this is equivalent to 6 times oversampling the input data. Carefully observing the sampling result of each phase, since the input data is regular alternating 01, the data obtained by 6 times oversampling also has certain regularity. If we group the data in groups of three, we can find that the result of every three samples of data will be repeated continuously. Therefore, oversampling can be simplified, using only 3 sampling phases, achieving an equivalent 3 times oversampling.
According to the PAM4 CDR in the burst mode, under the condition that no additional sampling circuit is added, the rapid oversampling function is realized only by multiplexing of the sampling circuit, and compared with the traditional method, the method has the advantages that: avoiding the generation of a plurality of equidistant phases and reducing the complexity of the circuit. According to data analysis, only 3 phases are used, namely 3 times of equivalent oversampling is realized, and in a traditional mode, 6 phases are needed and lower power consumption can be realized at the same locking speed.
In the present example, the lead-lag relationship of the clock data is determined based on the data analysis, and fig. 8 is a loop-locked case, in which the result of every third sampling data is 110 and is repeated; fig. 9 is a case where the sampling signal leads the data, in which case the result is 111 every three sampling data and is repeated; fig. 10 shows the case of two kinds of sampling signal leading data, in which case the result is 011 or 001 every third sampling data and is repeated continuously; fig. 11 shows the case where two sampled signals lag data, in which case the result is 100 or 000 for every third sample and repeats. Thus, by simplifying the oversampling, only 3 sampling phases are used, achieving an equivalent 3-fold oversampling.
Fig. 12 is a logic block diagram of the oversampling logic unit 4. When the CDR circuit is in a reset state, the oversampling logic unit 4 will control the CDR to be in an oversampling mode, if the three phase decision signals input at this time are 110, it is indicated that the CDR is in a state close to locking, and the oversampling logic unit 4 will control the CDR to enter a BBPD locking mode; when the three input decision signals are 111/011/001, the phase advance is illustrated, and the clock is lagged; when the data is 100 or 000, phase lag is illustrated, at which point the sampling phase will be increased. The system will continue to repeat this process until it locks (decision signal 110).
Fig. 13 is a circuit block diagram of an embodiment of the oversampling logic unit 4, and the three sampled decision signals are set to Sample [2], sample [1] and Sample [0], respectively. To achieve high speed, all the circuitry of the oversampling logic unit 4 needs to operate at a very high frequency. Therefore, in order to reduce the delay introduced by the logic unit, the logic for judging the lead and the lag is optimized, only 4 logic gates are needed to realize the judgment, and only 3 logic gates are needed under the longest path. The register control is a comprehensive 8-bit register group. When the phase lead signal is high (VDD), the register control will decrease the value of the 8-bit register bank; when the phase lag signal is high (VDD), the register control will increase the value of the 8-bit register bank.
By adopting the oversampling logic, compromise between loop bandwidth and loop locking time in the conventional BBPD phase detection mode is avoided, so that the reduction of the whole loop phase locking time does not depend on the improvement of the loop bandwidth. Based on this, the CDR chip example adopting the mode of the invention can realize the phase locking within 7ns while maintaining the loop bandwidth of 5 MHz.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A high speed burst mode clock data recovery circuit adapted for use with a PAM4 signal, comprising: the phase detection circuit comprises a sampling decision circuit (1), a phase discrimination circuit (2), a majority voting circuit (3), an oversampling logic unit (4), a digital phase control module (5), a digital loop filter (6), a quadrature clock generation circuit (7) and a phase synthesis module (8);
a first input end of the sampling decision circuit (1) is used for receiving an externally input PAM4 data signal, and a second input end of the sampling decision circuit (1) is connected to an output end of the phase synthesis module (8) and used for carrying out digital quantization on an input level according to a set reference voltage and outputting a quantization result;
the input end of the phase demodulation circuit (2) is connected to the output end of the sampling decision circuit (1) and is used for receiving the quantized data signal and the clock signal output by the phase synthesis module and generating a leading voltage signal and a lagging voltage signal of the clock relative to the data signal according to the phase relation between the quantized data signal and the clock signal;
the input end of the majority voting circuit (3) is connected to the output end of the phase detection circuit (2) and is used for outputting a unique leading voltage signal and a unique lagging voltage signal of a clock relative to a data signal after output data of the phase detection circuit are combined;
the input end of the over-sampling logic unit (4) is connected to the output end of the sampling decision circuit (1) and is used for controlling the switching of a loop locking mode between an over-sampling mode and a phase discrimination locking mode, over-sampling the PAM4 data signal quantization result and outputting a control signal;
a first input end of the digital phase control module (5) is connected to an output end of the majority voting circuit (3), and a second input end of the digital phase control module is connected to an output end of the oversampling logic unit (4) and used for outputting a digital logic signal according to a phase discrimination result output by the majority voter and the control signal;
the input end of the digital loop filter (6) is connected to the output end of the digital phase control module (5) and is used for performing low-pass filtering processing on the digital logic signal;
the orthogonal clock generating circuit (7) is used for receiving an externally input reference clock signal, filtering an external clock and generating two orthogonal clock signals;
a first input end of the phase synthesis module (8) is connected to an output end of the digital loop filter (6), and a second input end of the phase synthesis module (8) is connected to an output end of the quadrature clock generation circuit (7), and is configured to shift phases of two quadrature clocks according to the digital logic signal, and send a clock signal after the phase shift to the sampling decision circuit and the phase discriminator;
when the phase discrimination circuit is initially started, the phase discrimination circuit is preset to be in an oversampling mode, only a sampling decision circuit (1), an oversampling logic unit (4), a digital phase control module (5) and a phase synthesis module (8) in a loop are in a working state, and a phase discrimination circuit (2), a majority voting circuit (3) and a digital loop filter (6) are in a closed state; when the sampling logic unit (4) judges that the system is close to locking, the sampling logic unit (4) closes the module and starts the phase discrimination circuit (2), the majority voting circuit (3) and the digital loop filter (6) so as to switch to a phase discrimination locking mode.
2. A high speed burst mode clock data recovery circuit as claimed in claim 1, characterized in that the sampling decision circuit (1) comprises: a first sampler A, a second sampler B, a third sampler C, a fourth sampler D, a first D flip-flop DFF _ A, a second D flip-flop DFF _ B, a third D flip-flop DFF _ C, a fourth D flip-flop DFF _ D and four groups of two-stage inverters;
the first input end of the first sampler A, the first input end of the second sampler B, the first input end of the third sampler C and the first input end of the fourth sampler D are all used for connecting external input signals, the second input end of the first sampler A is connected with a first reference voltage REF1, the second input end of the second sampler B is connected with a second reference voltage REF2, the second input end of the third sampler C is connected with a third reference voltage REF3, and the second input end of the fourth sampler D is connected with the second reference voltage REF2;
a first input terminal of the first D flip-flop DFF _ a is connected to an output terminal of the first sampler a, a first input terminal of the second D flip-flop DFF _ B is connected to an output terminal of the second sampler B, a first input terminal of the third D flip-flop DFF _ C is connected to an output terminal of the third sampler C, and a first input terminal of the fourth D flip-flop DFF _ D is connected to an output terminal of the fourth sampler D; a second input terminal of the first D flip-flop DFF _ a, a second input terminal of the second D flip-flop DFF _ B, and a second input terminal of the third D flip-flop DFF _ C are all used for connecting a data sampling clock, and an output terminal of the fourth D flip-flop DFF _ D is used for connecting an edge sampling clock;
the input end of the first group of two-stage inverters is connected to the output end of the first D flip-flop DFF _ A, and the output end of the first group of two-stage inverters is used for outputting data A; the input end of the second group of two-stage inverters is connected to the output end of the second D flip-flop DFF _ B, and the output end of the second group of two-stage inverters is used for outputting data B; the input end of the third group of two-stage inverters is connected to the output end of the third D flip-flop DFF _ C, and the output end of the third group of two-stage inverters is used for outputting data C; the input end of the fourth group of two-stage inverters is connected to the output end of the fourth D flip-flop DFF _ D, and the output end of the fourth group of two-stage inverters is used for outputting an edge a;
wherein the first reference voltage REF1 is smaller than the second reference voltage REF2, and the second reference voltage REF2 is smaller than the third reference voltage REF3.
3. A high speed burst mode clock data recovery circuit as claimed in claim 2, characterized in that the phase detection circuit (2) comprises: a Bang phase discriminator; the Bang phase discriminator comprises an exclusive-or gate A and an exclusive-or gate B;
the first input end of the exclusive-or gate A is connected to the output end of the fourth group of two-stage inverters, the second input end of the exclusive-or gate A is connected to the output end of the second group of two-stage inverters, and the exclusive-or gate A outputs a clock leading signal for adjusting the clock phase and realizing phase locking;
and the first input end of the exclusive-OR gate B is connected to the output end of the second group of two-stage inverters, the second input end of the exclusive-OR gate B is connected with data of a previous sampling point, and the exclusive-OR gate B outputs a clock lagging signal for adjusting the clock phase and realizing phase locking.
4. A high speed burst mode clock data recovery circuit as claimed in claim 1, characterized in that the oversampling logic unit (4) comprises: the over-sampling control logic module is used for realizing phase locking logic in an over-sampling mode and judging whether the phase locking module is in a close locking state according to a phase result: if the digital phase control module is in a close locking state, the oversampling control logic module gives the value of the internal register to the digital phase control module.
5. The high speed burst mode clock data recovery circuit of claim 4 wherein the oversampling control logic module comprises: NOT gate, OR gate, NOR gate, AND gate and register;
the input end of the NOT gate is connected with a third sampling signal Sample [2], the output end of the NOT gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with a second sampling signal Sample [1], the output end of the OR gate is connected with the first input end of the AND gate, the second input end of the AND gate is connected with a first sampling signal Sample [0], and the output end of the AND gate is connected with the first input end of the register and used for outputting a phase advance signal; the first input end of the NOR gate is connected with the second sampling signal Sample [1], the second input end of the NOR gate is connected with the first sampling signal Sample [0], the output end of the NOR gate is connected with the second input end of the register and used for outputting a phase lag signal, and the register is used for outputting a phase control signal according to the phase lag signal and the phase lead signal.
6. A high speed burst mode clock data recovery circuit according to any of claims 1 to 5, characterized in that the phase synthesis block (8) comprises: four groups of phase interpolation units;
the two groups of phase interpolation units are used for generating clocks with four phases of 0 degree, 90 degrees, 180 degrees and 270 degrees as data sampling clocks which are respectively supplied to each sampling channel;
the other two groups of phase interpolation units are used for generating clocks with four phases of 45 degrees, 135 degrees, 225 degrees and 315 degrees as edge sampling clocks.
7. An oversampling logic control method based on the high speed burst mode clock data recovery circuit according to any one of claims 1 to 6, comprising the steps of:
(1) Judging whether the three input phase decision signals are 110, if so, controlling the CDR to enter a BBPD locking mode; if not, entering the step (2);
(2) Judging whether the three input phase judgment signals are 111, 011 or 001, if so, controlling to reduce the sampling phase and delaying the clock; if not, entering the step (3);
(3) And (4) judging whether the input three phase judgment signals are 100 or 000, if so, controlling to increase the sampling phase, otherwise, not needing phase operation and returning to the step (1).
8. A PAM4 receiver, the PAM4 receiver comprising: the device comprises a clock data recovery circuit, a PAM4 decoding circuit and an analog combiner;
the clock data recovery circuit is used for recovering data from an input signal by extracting a correct sampling phase; the PAM4 decoding circuit is used for decoding the data A, the data B and the data C output from the sampler into NRZ coded binary codes MSB1 and LSB1; the analog combiner is used for combining MSB1, MSB2, MSB3 and MSB4 of 4 sampling channels with 1/4 rate into a series MSB; and the LSB1, LSB2, LSB3 and LSB4 of the 4 sampling channels are fused into one LSB in series connection; the clock data recovery circuit is the high-speed burst mode clock data recovery circuit according to any one of claims 1 to 6.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301358A (en) * | 2015-05-28 | 2017-01-04 | 瑞昱半导体股份有限公司 | The time pulse return apparatus of quick lock in and its method |
| WO2017141258A1 (en) * | 2016-02-18 | 2017-08-24 | Shiv Nadar University | Method for achieving higher jitter tolerance in a cdr circuit and the cdr circuit thereof |
| CN109787615A (en) * | 2018-12-29 | 2019-05-21 | 光梓信息科技（上海）有限公司 | Frequency discriminator, PAM4 data clock frequency locking means, restoration methods and circuit |
| CN113644909A (en) * | 2021-08-20 | 2021-11-12 | 天津大学 | Clock and data recovery circuit for PAM4 receiver |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7292662B2 (en) * | 2003-03-26 | 2007-11-06 | Infineon Technologies Ag | Feed forward clock and data recovery unit |
| US7436920B2 (en) * | 2004-06-17 | 2008-10-14 | Matisse Networks | Burst mode receiver based on charge pump PLL with idle-time loop stabilizer |
| US8243869B2 (en) * | 2006-11-28 | 2012-08-14 | Broadlight Ltd. | Burst mode clock and data recovery circuit and method |
| US8379711B2 (en) * | 2009-06-30 | 2013-02-19 | Lsi Corporation | Methods and apparatus for decision-feedback equalization with oversampled phase detector |
| US9479366B2 (en) * | 2015-01-28 | 2016-10-25 | Texas Instruments Incorporated | IIR DFE updating gain and time constants using LMS equations |
| US20180302264A1 (en) * | 2017-04-17 | 2018-10-18 | Intel Corporation | Hybrid clock data recovery circuitry for pulse amplitude modulation schemes |
-
2021
- 2021-11-24 CN CN202111406737.XA patent/CN114142852B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301358A (en) * | 2015-05-28 | 2017-01-04 | 瑞昱半导体股份有限公司 | The time pulse return apparatus of quick lock in and its method |
| WO2017141258A1 (en) * | 2016-02-18 | 2017-08-24 | Shiv Nadar University | Method for achieving higher jitter tolerance in a cdr circuit and the cdr circuit thereof |
| CN109787615A (en) * | 2018-12-29 | 2019-05-21 | 光梓信息科技（上海）有限公司 | Frequency discriminator, PAM4 data clock frequency locking means, restoration methods and circuit |
| CN113644909A (en) * | 2021-08-20 | 2021-11-12 | 天津大学 | Clock and data recovery circuit for PAM4 receiver |
Non-Patent Citations (3)
| Title |
|---|
| A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital;Changzhi Yu;《 IEEE Journal of Solid-State Circuits》;20200709;第2831 – 2841页 * |
| The Design Techniques for High-Speed PAM4 Clock and Data Recovery;Qiwen Liao;《 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)》;20190506;第142-143页 * |
| 面向5G通信的高速PAM4信号时钟与数据恢复技术;廖启文;《中兴通讯技术》;20180801;第21-26页 * |
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