KR100975083B1 - Serial transmitter and communication method used by the serial transceiver - Google Patents

Abstract

The present invention relates to a high-speed transmission and reception apparatus that does not use an external clock signal and a communication method thereof. To this end, a clock recovery unit including a built-in curse code generator, a frequency detector, and a linear phase detector is applied to a receiver, thereby providing clock information to data. While using the embedded clock method to apply the circuit, there is an excellent effect of eliminating the skew problem between the reference clock and the data and the jitter problem of the reconstructed clock that occur during data transmission.

Curse Code, Receive, Serial Communication, Synchronization, Phase Sync, Linear Phase Detector, Frequency Detector

Description

Serial transceiver and its communication method {SERIAL TRANSMITTER AND COMMUNICATION METHOD USED BY THE SERIAL TRANSCEIVER}

The present invention relates to a serial transmission and reception apparatus, and more particularly, to a high speed transmission and reception apparatus and a communication method thereof using no external clock signal.

The rapid proliferation and development of various communication methods has increased the user demand for multimedia, and thus, researches are being actively conducted to transmit more data more stably at a higher speed and to minimize the hardware configuration required for such transmission. have.

In general, in order to increase the data transmission speed, it is necessary to maximize the function by selecting one of the parallel transmission method that increases the number of channels and transmits multiple data at the same time and the serial transmission method that transmits the data at high speed through one channel. It is common. In this case, in the case of the parallel transmission scheme, data skew, which means a time difference between data transmitted through different channels, may exist between several transport channels, and as the number of channels increases, hardware cost increases. The transmission method has been widely used as a standard for high-speed transceivers, and research is being conducted to construct such high-speed serial communications in parallel. In such serial data transmission and reception, there is a problem that data uncertainty increases due to noise and bandwidth of a channel because data is very high in and out. To reduce this uncertainty in data transmission, the receiver must recover the clock to have as little jitter as possible to sample the input data, and optimize the phase relationship between the recovered clock and the input data so that the bit error rate is minimal. It must be maintained. Therefore, in the high speed serial communication, the clock recovery circuit that receives the clock and data from the transmitter and rearranges the clock signal to an optimal state for sampling the input data may be very important.

In general, a high speed data transceiver is configured to transmit a reference clock signal together to provide a synchronization reference for high speed data transmission and reception in order to transmit data from a transmitter to a receiver. However, this method can cause the receiver to recover data due to the skew problem between the data and the reference clock when transmitting over a long distance of several meters. In addition, in order to change the transmission speed of the conventional transceiver, it is troublesome to change the reference clock signal of the receiver to match the transmission speed or to change the digital code to adjust the operation speed of the receiver.

US Patent No. 6,680,970 "Statistical methods and systems for data rate detection for multi-speed embedded clock serial receivers" addresses this problem. For this purpose, a method using a method of detecting edges of the data is proposed, but in this case, the speed is limited because the jitter of the recovered clock signal is larger than that of the linear phase detector due to the limitation of the detection of the edge of the data. And the likelihood of error increases.

Alternatively, U.S. Patent No. 5,838,749 entitled "Method and apparatus for extracting an embedded clock from a digital data signal" includes a clock recovery circuit to solve the above problem. Although a method of mounting a clock supplier is used, problems such as an increase in area, cost, and power consumption are caused by the additional mounting of the clock supply.

An object of the embodiments of the present invention is to apply an embedded clock scheme for applying clock information to data by applying a clock recovery unit including a built-in curse code generator, a frequency detector, and a linear phase detector to a receiver when transferring data from a transmitter to a receiver. The present invention provides a serial transceiver and a communication method thereof, which can eliminate a skew problem between a reference clock and data and a jitter problem of a restore clock while data is being transmitted.

Another object of the embodiments of the present invention is to eliminate the skew problem between the data and the reference clock by not transmitting the reference clock together in data transmission, and to reduce the hardware cost by minimizing the number of transmission channels. It is to provide a serial transceiver and a communication method thereof.

Another object of the embodiments of the present invention is to adjust the speed without a separate external operation without transmitting the reference clock when transmitting data, and to reduce the jitter of the clock signal restored by applying the linear phase detection method. It is to provide a serial transceiver and a communication method thereof.

Another object of the embodiments of the present invention is to provide a serial transmission / reception apparatus and a communication method for recovering a clock signal without additional circuitry such as a separate clock supply to a receiver.

Another object of the embodiments of the present invention is to divide a voltage controlled oscillator output at a data rate and compare it with delayed data so as to apply a frequency detector that adjusts an operating frequency of the voltage controlled oscillator to a clock recovery unit to generate an accurate lock signal. It is to provide a serial transceiver and a communication method thereof.

Still another object of the embodiments of the present invention is to apply a linear phase detector for detecting a case having a rising edge of serial data and adjusting a charge pump with a pulse according to a phase difference between a clock signal and a serial data signal. And a communication method thereof.

In order to achieve the above object, the serial transmission and reception apparatus according to an embodiment of the present invention receives the parallel data to be transmitted and encodes the transmission data including the DC balance information and the internal phase operating based on an externally provided clock A transmitter including serial transmission means for serially transmitting data encoded according to a fixed clock communication clock; A clock recovery unit having a frequency detector and a linear phase detector for receiving encoded data from the transmitter and sequentially synchronizing the internal voltage controlled oscillator output with the received encoded data; and a plurality of stages output by the clock recovery unit A parallel bit that converts the received serial data into parallel data using a clock of the first memory; and a start bit detector for detecting a start bit by comparing some data of the output of the parallel device through a logic circuit, and an output of the parallel device. The receiver comprises a decoder for decoding and outputting.

Meanwhile, the transmitter receives a plurality of parallel data signals and divides the parallel data signals into two or more units, inserts information for DC balance at the divided positions, and starts information at the beginning and the end of the entire data, respectively. And encoding means for inserting termination information.

The clock recovery unit of the receiver may include a voltage controlled oscillator of a plurality of stages whose frequency range is determined by a cursor code; A built-in coarse code (Coarse Code) generation unit for providing the voltage-controlled oscillator with a curse code for controlling the voltage-controlled oscillator by inputting the output of the voltage-controlled oscillator and the received serial data; A frequency detector for outputting a signal for adjusting an applied voltage of the voltage controlled oscillator so that frequency synchronization is achieved by inputting the voltage controlled oscillator output in the frequency range determined by the output of the curse code generator and the received serial data; A linear phase detector for outputting a signal for adjusting an applied voltage of the voltage controlled oscillator for phase synchronization by inputting the voltage controlled oscillator output and the received serial data when the frequency detector is synchronized with the frequency detector; And a charge pump configured to selectively receive an output of the frequency detector and an output of the linear phase detector to adjust an applied voltage of the voltage controlled oscillator.

The clock recoverer generates a sampler for sampling the received serial data by using an output of the voltage controlled oscillator, and generates a enable signal for determining whether the curse code generator is operated according to the output of the sampler. The apparatus may further include a start circuit unit provided to the generation unit.

A serial transmission apparatus according to another embodiment of the present invention is a serial transmission apparatus connected to a serial reception apparatus and transmitting parallel data as serial data. The serial transmission apparatus receives a parallel data to be transmitted and includes a DC balance information and start and end information. An encoding unit for encoding data; A serial device for providing synchronization signals in a serial communication manner using an output clock of an internal phase locked loop according to an externally provided clock as a communication clock; And serial transmission means for serial transmission of data encoded according to the communication clock.

The serial receiver according to another embodiment of the present invention is connected to a transmitter for encoding parallel data and transmitting the serial data, and after receiving the serial data, recovers the clock included in the serial data and converts the serial data into parallel data. A serial receiver for converting and decoding to output a received clock and decoded parallel data, the serial receiver comprising: a frequency detector and a linear phase receiving serial data from the transmitter and synchronizing sequentially using an internal voltage controlled oscillator output and the received serial data A clock recovery unit having a detector; A parallel unit for converting the received serial data into parallel data using a clock of a plurality of stages output by the clock recovery unit; A start bit detector for detecting a start bit by comparing some data of the output of the parallel device through a logic circuit; And a receiver including a decoder for decoding and outputting the output of the parallelizer.

A serial receiver according to another embodiment of the present invention includes a clock recovery unit including a frequency detector to recover a clock, wherein the frequency detector is configured to receive some signals of the voltage controlled oscillator outputs of the plurality of stages. A divider which dispenses at a speed of; A serial data delay delaying the serial data delaying the output of the voltage controlled oscillator by the delay time of the frequency divider; At least one sync detection unit comparing one of the output of the delayer and one of the outputs of the divider to detect synchronization and providing the result as a synchronization signal; When a frequency difference occurs using a periodic pulse signal by one of the outputs of the divider and the output of the delayer, a frequency drop signal is output, and a frequency is generated by the synchronization signal of the synchronization detector and the output of the delayer. It comprises a frequency control unit for blocking the frequency falling signal during synchronization.

A serial receiver according to still another embodiment of the present invention includes a clock recovery unit including a linear phase detector to recover a clock, wherein the linear phase detector includes an initial stage and a final stage among the voltage controlled oscillator outputs of the multiple stages. A delay unit for delaying an output signal and the received data, respectively; A rising edge detector for sampling the serial received data according to the first stage and last stage output signals to detect rising edges of the serial data; The delayed voltage control on the basis of the rising edge of the delayed serial data by receiving the received data delayed by the delay unit and the rising edge detector output and the first stage and the final stage output of the voltage controlled oscillator delayed by the delay unit as inputs. And a phase detector for outputting a pulse between the final stage output of the oscillator and the rising edge of the initial stage output as a signal for adjusting the voltage of the voltage controlled oscillator, respectively.

In the serial transmission / reception apparatus according to another embodiment of the present invention, when the transmitter and the receiver are connected through a serial channel, the transmitter divides the actual data into a plurality of uniform sizes to include DC balance information for each divided region, and the entire data. Transmitting a serial transmission over the serial channel by encoding start and end information into actual transmission data having redundant information; The receiver generates a clock signal corresponding to the data rate by using a frequency detection method on the actual transmission data received through the serial channel, and restores a clock by adjusting a phase of a synchronized clock through a linear phase detection method. And a receiving step of acquiring data from the actual transmission data, decoding and outputting the original data from which the excess information is removed.

The serial transmission / reception apparatus according to an embodiment of the present invention and a communication method thereof employ an embedded clock scheme for applying clock information to data by applying a clock recovery unit including a built-in curse code generator, a frequency detector, and a linear phase detector to a receiver. It also has the added benefit of eliminating skew problems between the reference clock and data and jitter in the recovery clock that occur during data transfer.

The serial transmission / reception apparatus and its communication method according to an embodiment of the present invention eliminate the skew problem between the data and the reference clock by not transmitting the reference clock together when transmitting data, and also minimize the number of transmission channels. This can reduce the overall cost.

The serial transmission / reception apparatus and its communication method according to an embodiment of the present invention can adjust the speed without a separate external operation in a serial communication using a single channel, and greatly reduce jitter of a recovered clock signal by applying a linear phase detection method. There is an effect to increase the maximum communication speed and stability.

The serial transmission / reception apparatus and its communication method according to an embodiment of the present invention use an embedded clock method, and do not require an initial synchronization process between the transceivers, so that the procedure is simple, the transmitter configuration is simple, and the clock recovery reliability of the receiver is high and the cost is low. In addition, there is an effect that can simplify the connection configuration of the transceiver.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating a transceiver structure according to an embodiment of the present invention, and includes a transmitter 100 for receiving a parallel signal and transmitting the signal as a serial signal and a receiver 200 for receiving the serial signal. In the illustrated embodiment, the parallel data to be transmitted is described using 24 bits as an example, which is the case used for the control signal interface for controlling the liquid crystal display means.

The transmitter 100 receives 24 bits of parallel data and a reference clock signal and generates parallel data to be a serial signal according to a predetermined protocol through the encoder 20 of FIG. 1. In the above example, after dividing the 24-bit data by 12 bits, the encoder 20 is configured to insert a DC balanced signal of 2 bits into the division area, and to insert a start bit and a stop bit for notifying the start and end of the entire data, respectively. I use it. Or, if necessary, a signal of a specific pattern can be generated.

The encoded parallel signal may have a form as shown in FIG. 2 when converted into a serial signal, in which a start bit and a stop bit each consisting of 1 bit are present, and the parallel data to be transmitted is a block having a uniform size. After dividing the data into two blocks of 12 bits each, a pair of DC balanced signals DC _A and DC _B is further inserted into the corresponding division. That is, in the illustrated example, the converted 28-bit signal is a code inserted to apply frequency information to the data, to indicate the beginning of the data and to indicate the end of the data and the Start bit, which always indicates a value of 1. It always has a Stop bit that represents a value of 0, and a DC-balancing bit in the middle of the actual 24 bits. Since the start bit and the stop bit always have values of 1 and 0, when the first bit output and the last bit output of the receiving end are always output as 1 and 0, the reception unit 200 determines that the restoration operation is completed. The DC _A and DC _B bits act as a DC balance to minimize the distortion of the data over long distances.

The data generated by the encoder 20 is serial transmission data encoded through the conversion unit 70 that converts a logic signal such as a serializer 60 and a CMOS into a low voltage differential signaling (LVDS) signal. It is transmitted through the serial communication channel. First, when power is applied to the transceivers 100 and 200, the converter 70 inside the transmitter outputs only a zero signal until the phase locked loop of the transmitter 100 is synchronized to the reference clock. Do it. At this time, the receiver 200 starts an internal initialization operation and maintains the entire receiver circuit in the reset state. When the phase locked loop inside the transmitter 100 is synchronized with an external reference clock, the transmitter 100 begins to transmit data through an encoding process, and the receiver 200 generates and transmits a clock signal corresponding to the transmitted data rate. Adjust the phase of the clock so that the data can be sampled at the optimal position.

The receiver 200 is converted through a signal converter 210 for converting a VLDS signal (serial data) received through a serial channel back into a logic level signal, thereby converting a clock recovery unit 230 and a data retimer for clock recovery. After a signal is acquired in units of data blocks divided according to the clock restored through 220, the signals are parallelized through the parallelizer 250. Thereafter, a fine lock is detected by the surplus bits through the start bit detector 270, and a parallel bit originally transmitted through the output buffer 280 is obtained by obtaining a 24-bit signal that is a real signal through the decoder 260. Data in the form of signals OUT <0> to OUT <23>, a receive clock Rx clock, and a lock signal DE are output.

3 shows a block diagram of a clock recovery unit 230 according to an embodiment of the present invention.

Using the characteristics of jitter inversely proportional to the speed of the signal, for example, if the transmitter transmits a signal by applying 28 bits of data information to a clock signal of 5 to 65 MHz, the receiver receives 14 bits per clock signal of 10 to 130 MHz. Designing to extract data information reduces jitter in the receiver's internal clock. That is, the jitter reduction operation is performed in the receiver by extracting the data according to the size of the data blocks separated during encoding.

The operation of the illustrated circuit is largely divided into three phases: a coarse voltage generation operation, a phase locked loop synchronization operation, and a data alignment operation. The curse voltage generation operation is related to the low jitter characteristics of the wideband transceiver, and the phase locked loop inside the receiver controls the entire frequency range instead of controlling a wide frequency range (e.g. 10 to 130 MHz) with a single fine adjustment voltage. Voltage control by dividing into a plurality of frequency ranges (e.g. three) and controlling only a frequency band corresponding to a curse voltage of a predetermined bit (2 bits when the range is three or less) with the fine adjustment voltage The effect of minimizing the oscillator 232 gain is obtained. If the gain of the voltage-controlled oscillator 232 is large, the frequency change is large even with a small adjustment voltage change, and thus, there is a disadvantage in that it is very sensitive to external noise and degrades the jitter characteristic. For this reason, a control method of selecting an operating frequency band by a curse voltage has been used in the past, but a separate external control signal was necessary because a method of directly applying a curse voltage according to the frequency range was directly applied from the outside. . However, in the present exemplary embodiment, the curse code generator 231 generates a curse voltage corresponding to an operation speed in the receiver 200 so that an external control signal is not required.

The curse voltage operation by the curse code generator 231 is performed as follows. When power is initially applied to the initial transceiver, the first operation of synchronizing the phase locked loop inside the transmitter to the reference clock signal is performed. The serial channel output of the transmitter 100 is fixed to 0 until the phase locked loop is synchronized. do. Accordingly, the receiver 200 receives an input of 0 until the transmitter 100 performs normal operation.

At this time, the serializer 60 inside the transmitter 100 samples the serial data signal with a clock signal generated while the phase locked loop inside the transmitter vibrates. Since the serial data signal is fixed to 0, the sampled 14 bits are sampled. Are also fixed to zero. When the phase-locked loop inside the transmitter 100 finishes the synchronous operation, the encoded data signal, as described above, becomes an output of the transmitter, that is, serial data, and is transmitted to the receiver 200. When the serial data has a non-zero value, the sampler 245 included in the receiver 200 has at least one output of the 14-bit output as one.

FIG. 4 shows the configuration of the initiating circuit unit 241 included in the clock recovery unit 230. The circuit is composed of a simple circuit 310 such as a NOR gate, a NAND gate, an inverter, and all 14-bit parallel outputs are zero. And when the at least one is 1, the receiver 200 may determine that the transmitter 100 has finished providing an internal signal after completing the internal synchronization operation. When the discriminating circuit 310 composed of the NOR gate, the NAND gate, and the inverter inside the start circuit unit 241 determines that the output of the parallelizer has at least one 1, The stage D-flip-flop circuit 320 generates the long pulse signal of 80 cycles through the clock signal divided by eight. The pulse signal becomes a coarse enable signal, which is the final output of the start circuit, to reset the entire receiver 200 and to start the curse voltage generation operation. Here, the circuit and scheme for generating the long period of 80 cycles is to obtain a predetermined delay required for the initial synchronization of the receiver 200, the specific configuration or delay time may be configured differently.

The curse code generation operation is performed by the curse code generation unit 231 of FIG. 5. A coarse enable signal is coupled to MOS1 to allow Vctrl to be connected to VDD or GND (GND in the case shown) while the curse enable signal has a value of 1 to enable the voltage controlled oscillator 232 to present curs. Set the device to oscillate at the maximum speed that the code can oscillate. Since all circuits of the receiver 200 have completed the reset operation by the operation of the start circuit 241, the first curse code has a state of 00, and the voltage controlled oscillator 232 at this time is in accordance with the current curse code. Oscillating at the highest frequency that can be represented in the lowest frequency range. The curse code generator 231 receives a clock signal of a voltage controlled oscillator 232 oscillating at a maximum frequency in a curse code and a serial data signal applied in the form of a reference clock signal, and includes a delay stage including an inverter and To the D-flip flop stage 443. The D-flip-flop stage connected to the delay stage samples the input clock signal at the rising edge of the delayed clock signal so that the delayed clock signal has a phase ahead of the falling edge of the input clock signal and has a phase behind the falling edge. By outputting a value of 0, the output value changes from 1 to 0 in the part where the falling edge of the input clock signal and the rising edge of the delayed clock have a similar phase. This finds out how many falling edges the clock signal has in phase with the signal passing through it. An identifier (1-0 detector) 444 is a block in which the circuits of FIG. 6 are arranged in series and outputs a signal of 1 at a portion where the input signal changes from 1 to 0, so that the clock signal falls. A signal of 1 is generated at the stage corresponding to the position of the corner. If the identifier 444 outputs a signal of 1 at the Nth stage through the above operation, it can be seen that the period of the input signal has a value similar to 2N. By comparing the value output, it is easy to detect which signal is faster. If it is determined that the serial data signal is faster than the clock signal of the voltage controlled oscillator 232 through this operation, the curse code is increased by one through the logic units 445 and 441 composed of simple digital logic, and as the curse code increases. The clock signal of the voltage controlled oscillator 232 oscillating in the high range is compared with the serial data signal to increase the curse code by one, or to maintain the current value.

After 80 cycles of the reference clock signal, the enable signal is changed to a value of zero. When the curse enable signal becomes 0, MOS1, which previously connected Vctrl to GND for the curse code generation operation, is turned off, and the generated curse code remains. In this case, the entire clock recovery circuit has a form of a frequency fixed loop including a voltage controlled oscillator 232, a frequency detector 233, a charge pump 236, and a loop filter (resistor and capacitor configuration). The frequency locked loop synchronization operation is to synchronize the output clock of the voltage controlled oscillator 232 with serial data applied through the frequency locked loop. The frequency detector 233 shown in FIG. 7 serves to drop the frequency of the voltage controlled oscillator 232 oscillating at the highest frequency in the current frequency range by the curse code generation operation to a range suitable for the data rate. In the embodiment, since the voltage controlled oscillator oscillates at twice the data rate, the clock signal VCO <0> / 2 divided by two is compared with the serial data signal delayed by the delay time of two dividers as shown in FIG. 7. D flip-flops FF1 and FF2 configured in the frequency comparator 530 generate one signal at the rising edge of VCO <0> / 2 and the delayed serial data signal, respectively, and FF1 is reset when both flip-flop signals are one. , FF2 is reset at every falling edge of the serial data delayed by the operation of the FF2 reset unit. Since one cycle of VCO <0> / 2 contains 28 bits of data, the delayed serial data signal will have more rising edges than VCO <0> / 2. In this case, if 1 is generated at all rising edges of the delayed serial data, it is difficult to accurately extract the frequency. Therefore, FF1 receives VDD signal as the flip-flop data, so that 1 is taken at every rising edge of VCO <0> / 2. FF2 receives VCO <0> / 2 as flip-flop data, and FF2 receives delayed serial data after the rising edge of VCO <0> / 2 (the interval where VCO <0> / 2 is 1). By generating 1 only at the rising edge, the phase difference with the rising edge of the delayed serial data first occurring after the rising edge of VCO <0> / 2 is detected. Since the frequency (Freq_diff) indicating the difference in frequency has a value of 1 at the rising edge of VCO <0> / 2 and then changes to the value of 0 as FF1 is reset at the rising edge of the delayed serial data that occurs immediately after. It has a pulse width equal to the phase difference between VCO <0> / 2 and the delayed serial data. The signal is transferred to the charge pump (CP) 236 until the signal PD_Enable indicating frequency synchronization occurs. It acts to lower. If the time delay between the rising edge of VCO <0> / 2 and the rising edge of the delayed serial data signal is continuously within a predetermined range (lock range specified by the synchronization detector), the synchronization detector generates a lock signal Freq_lock.

The synchronization detector 540 shown in FIG. 8 receives the output data of the serial data and the voltage controlled oscillator 232 during the frequency locked loop synchronization operation so that the phase difference between the two signals is smaller than the delay time of the buffer cell at the D-flip-flop input terminal. When it is determined that the two signals are synchronized, the lock0 signal is output as 1. The counter connected to the lock0 signal outputs the final output (lock <n>) to 1 only when the lock signal is outputted as 1 for 8 or more cycles (in this embodiment) in preparation for the malfunction of the synchronization detector 540. .

Since the delayed serial data consists of arbitrary signals except start / stop bits and DC _A / DC _B bits, the rising edge of delayed serial data that occurs immediately after VCO <0> / 2 is the rising edge of the start bit. Until the edge is reached, the lock condition of the synchronization detector 540 cannot be satisfied. If the lock detector 540 does not generate a lock signal, the frequency detector 233 generates a signal Freq_DN for continuously adjusting the frequency down, so that the final lock state is increased by VCO <0> / 2. It is time for the rising edge of the edge and the delayed serial data start bit to be within the lock range. As described above, the sync detector 1 serves to detect a time delay between VCO <0> / 2 and the rising edge of the delayed serial data start bit, and the sync detector 2 is DC _A which is VCO <7> b / 2 and the 14th bit. It serves to detect the time delay between falling edges of bits.

If the speed of the serial data and the frequency of the clock are synchronized, and the phase between VCO <0> / 2 and the rising edge of the start bit is synchronized, the falling edge of VCOb <7> / 2 and the DC _A bit is also synchronized in the data structure of the embodiment. Since two synchronization detectors are used for more accurate synchronization detection, the number of synchronization detectors may vary depending on the design method. Here, when both of the synchronization detectors generate the lock signal, the PD_Enable signal is generated. The Freq_DN signal is kept at 0 as one input of the NAND gate outputting Freq_DN becomes 0.

When the synchronization signal PD_Enable of the frequency detector 233 outputs 1, the receiver 200 stops the frequency locked loop synchronization operation and changes the output of the multi-phase selector 234 to form a new loop. The new loop consists of a voltage controlled oscillator 232, a linear phase detector (Linear PD) 239, a charge pump (CP) 236, and serial data aligned with the voltage controlled oscillator 232 clock generated through the loop. The signal is coupled to the parallelizer 250.

The newly configured loop is a loop that is responsible for the data alignment operation so that the rising edge of the clock of the voltage controlled oscillator 232 is aligned at the center of each bit of the actual data signal. Conventional high-speed transceivers typically use a bang-bang phase detector to construct a clock recovery circuit, which has a relatively large jitter in the clock signal being recovered, which can increase the bit error rate (BER). In this embodiment, the linear phase detector 239 is designed to exhibit relatively small jitter and low bit error rate.

The voltage controlled oscillator 232 uses 14 stages, that is, a voltage controlled oscillator having 14 different phases, thereby providing an oscillating output for a 14 bit data block (12 bits of data and 2 bits of redundant data). have. If the input signal is divided into data blocks of different sizes, different stages are required.

9 and 10 show an example circuit diagram of the linear phase detector 239 and an operation waveform of the circuit. The linear phase detector 239 includes a serial data rising edge detector 510, which receives two multi-phase clock signals VCO <13> and VCO <0> and a serial data signal and serializes each clock signal. When the sampled output signal (sam <13>, sam <0>) has values of 0 and 1 in turn, that is, when the serial data signal has a rising edge, the phase difference between the clock signal and the serial data signal Accordingly, the pulse signal corresponding to the phase difference is output. However, the operation of the serial data rising edge detector 510 for determining whether the rising edge of the serial data is present should be terminated before the PD_DN and PD_UP signals are generated. VCO <0 generated by one data bit behind VCO <13>. Sam <0>, which is the result of sampling serial data with the> signal, is generated after PD_DN is generated by VCO <13>. In order to solve this problem, three input signals VCO <13>, VCO <0>, and a delay cell 521 having a delay of more than one data bit are connected to serial data, and the detection of PD_DN and PD_UP signals is performed. The delayed signals CK1D, CK2D, and DD signals are used. For example, in the case of using the 13th and 0th multi-phase clock signals among the 14 multi-phases, the serial data signal sampled by the 13th clock signal and the serial data signal sampled by the 0th clock signal are 0 and 0, respectively. If 1, that is, if the serial data signal has a rising edge between the 13th clock and the 0th clock signal as shown in Fig. 10, the linear phase detector 239 is delayed with the rising edge of the delayed 13th clock signal CK1D. The phase difference between the rising edge of the serial data DD is represented by the PD_DN signal, and the phase difference between the rising edge of the DD and the rising edge of the delayed zeroth clock signal CK2D is represented by the PD_UP signal. Since the PD_DN and PD_UP signals appear as pulses proportional to the phase difference between the multi-phase clock signal and the serial data signal, when the PD_DN signal appears as a wider pulse than the PD_UP signal, the signal to the charge pump 236 is slowed down. And vice versa to charge pump 236 to make the multiple clock signal faster. If the PD_DN signal and the PD_UP signal have the same width, the zeroth clock is located at the center of the serial data. In this case, the charge pump 236 keeps the output current constant.

Since the PD_DN and PD_UP signals are input signals to the charge pump, if there is a phase difference between the two signals, a current error may occur in the charge pump to generate a fixed phase error. The delay, that is, the half of the phase difference between the multi-phase clock signals is designed to be output in a delayed state to minimize the fixed phase error.

After finishing the data alignment by the linear phase detector 239, the first and last outputs of the parallelizer 250 are always fixed to 1 and 0, meaning start and stop bits. The start bit detector 270, which is a circuit that detects that the first and last outputs are output as 1 and 0 by simple logic, determines that the DE lock signal, which is the final lock signal, is set to 1 when the start and stop bits are fixed to 1 and 0. It is fixed to provide a permission signal indicating that the output of the parallelizer 250 may be used. Finally, the receiver 200 outputs a clock signal synchronized with an actual 24 bit output and a data rate excluding the start bit, stop bit, DCA, and DCB among the 28 bit output signals of the parallelizer 250.

1 is a block diagram showing the configuration of a high-speed transceiver that does not use a reference clock.

2 is a diagram illustrating a signal transmission form of a high speed transceiver.

3 is a block diagram showing a configuration of a clock recovery circuit.

4 is a block diagram showing the configuration of a start circuit portion;

5 is a block diagram showing the configuration of a curse voltage generator.

6 is a block diagram showing the configuration of a 1-0 detector included in a curse voltage generator.

7 is a block diagram showing the configuration of a frequency detector circuit.

8 is a block diagram showing a configuration of a synchronization detector applied to a frequency detector circuit.

9 is a block diagram showing the configuration of a linear phase detector circuit.

10 is a diagram illustrating a case where a phase difference is detected by a linear phase detector.

** Description of symbols for the main parts of the drawing **

10: input buffer 20: encoder

60: serializer 70: converter

100: transmitter 200: receiver

210: signal converter 220: data retimer

230: clock recovery unit 250: parallel

260: decoder 270: start bit detection unit

280: output buffer

Claims (14)

A transmitter including serial transmission means for receiving parallel data to be transmitted and encoding the data into transmission data including DC balance information, and serially transmitting data encoded according to a communication clock of an internal phase locked loop operating based on an externally provided clock. Wow; A clock recovery unit having a frequency detector and a linear phase detector for receiving encoded data from the transmitter and sequentially synchronizing the internal voltage controlled oscillator output with the received encoded data; and a plurality of stages output by the clock recovery unit A parallel bit that converts the received serial data into parallel data using a clock of the first memory; and a start bit detector for detecting a start bit by comparing some data of the output of the parallel device through a logic circuit, and an output of the parallel device. And a receiving unit including a decoder for decoding and outputting the serial transmitting and receiving device. The apparatus of claim 1, wherein the transmitter receives a plurality of parallel data signals, divides the parallel data signals into two or more units, inserts information for DC balance at the divided positions, and starts and ends the entire data. And encoding means for inserting start information and end information, respectively. The clock recovery unit of claim 1, wherein the clock recovery unit A multistage voltage controlled oscillator whose frequency range is determined by a curse code; A built-in coarse code (Coarse Code) generation unit for providing the voltage-controlled oscillator with a curse code for controlling the voltage-controlled oscillator by inputting the output of the voltage-controlled oscillator and the received serial data; A frequency detector for outputting a signal for adjusting an applied voltage of the voltage controlled oscillator so that frequency synchronization is achieved by inputting the voltage controlled oscillator output in the frequency range determined by the output of the curse code generator and the received serial data; A linear phase detector for outputting a signal for adjusting an applied voltage of the voltage controlled oscillator for phase synchronization by inputting the voltage controlled oscillator output and the received serial data when the frequency detector is synchronized with the frequency detector; And a charge pump selectively receiving the output of the frequency detector and the output of the linear phase detector to adjust an applied voltage of the voltage controlled oscillator. The method of claim 3, wherein the clock recovery unit A sampler for sampling the received serial data using the output of the voltage controlled oscillator; And a starting circuit unit configured to generate a curse enable signal that determines whether the curse code generator is operated according to an output of the sampler, and to provide the curse enable signal to the curse code generator. 5. The method of claim 4, further comprising a switch for selectively connecting an applied voltage provided by the charge pump to the voltage controlled oscillator with a maximum voltage or a minimum voltage to operate the voltage controlled oscillator at a maximum frequency. And a signal is also used as a control signal for operating the switch. 4. The multi-stage voltage controlled oscillator of claim 3, wherein the bit size of the data block divided by the DC balance information and the half size and start or stop of the DC balance information among serial signals provided for one external clock. And a stage having the same size as the sum of the bits. A serial transmission device connected to a serial reception device and transmitting parallel data as serial data, An encoding unit which receives parallel data to be transmitted and encodes the same into transmission data including DC balance information and start and end information; A serial device for providing synchronization signals in a serial communication manner using an output clock of an internal phase locked loop according to an externally provided clock as a communication clock; And serial transmission means for serially transmitting data encoded according to the communication clock. Connected to a transmitter that encodes parallel data and transmits it as serial data, receives the serial data, restores the clock included in the serial data, converts and decodes the serial data into parallel data, and outputs the received clock and decoded parallel data. In the serial receiving device, A clock recovery unit including a frequency detector and a linear phase detector for receiving serial data from the transmitter and synchronizing sequentially using an internal voltage controlled oscillator output and the received serial data; A parallel unit for converting the received serial data into parallel data using a clock of a plurality of stages output by the clock recovery unit; A start bit detector for detecting a start bit by comparing some data of the output of the parallel device through a logic circuit; And a receiver comprising a decoder for decoding and outputting the output of the parallelizer. The method of claim 8, wherein the clock recovery unit A multistage voltage controlled oscillator whose frequency range is determined by a curse code; A built-in curse code generator for providing the voltage controlled oscillator with a curse code for controlling the voltage controlled oscillator by inputting the output of the voltage controlled oscillator and the received serial data; A frequency detector for outputting a signal for adjusting an applied voltage of the voltage controlled oscillator so that frequency synchronization is achieved by inputting the voltage controlled oscillator output in the frequency range determined by the output of the curse code generator and the received serial data; A linear phase detector for outputting a signal for adjusting an applied voltage of the voltage controlled oscillator for phase synchronization by inputting the voltage controlled oscillator output and the received serial data when the frequency detector is synchronized with the frequency detector; And a charge pump selectively receiving the output of the frequency detector and the output of the linear phase detector to adjust an applied voltage of the voltage controlled oscillator. Connected to a transmitter that encodes parallel data and transmits it as serial data, receives the serial data, restores the clock included in the serial data, converts and decodes the serial data into parallel data, and outputs the received clock and decoded parallel data. To a serial receiver device The serial receiver includes a clock recovery unit including a frequency detector for recovering a clock, wherein the frequency detector A divider for dividing a part of a plurality of stages of voltage controlled oscillator outputs at a rate of the received data; A serial data delay delaying the serial data delaying the output of the voltage controlled oscillator by the delay time of the frequency divider; At least one sync detection unit comparing one of the output of the delayer and one of the outputs of the divider to detect synchronization and providing the result as a synchronization signal; When a frequency difference occurs using a periodic pulse signal by one of the outputs of the divider and the output of the delayer, a frequency drop signal is output, and a frequency is generated by the synchronization signal of the synchronization detector and the output of the delayer. And a frequency adjuster to block the frequency down signal during synchronization. Connected to a transmitter that encodes parallel data and transmits it as serial data, receives the serial data, restores the clock included in the serial data, converts and decodes the serial data into parallel data, and outputs the received clock and decoded parallel data. To a serial receiver device The serial receiver includes a clock recovery unit including a linear phase detector to recover a clock, and the linear phase detector A delay unit for delaying the first and last stage output signals and the received data among the voltage controlled oscillator outputs of the multiple stages, respectively; A rising edge detector for sampling the serial received data according to the first stage and last stage output signals to detect rising edges of the serial data; The delayed voltage control on the basis of the rising edge of the delayed serial data by receiving the received data delayed by the delay unit and the rising edge detector output and the first stage and the final stage output of the voltage controlled oscillator delayed by the delay unit as inputs. And a phase detector for outputting a pulse between the final stage output of the oscillator and the rising edge of the initial stage output as a signal for adjusting the voltage of the voltage controlled oscillator, respectively. When the transmitter and the receiver are connected through a serial channel, the transmitter divides the actual data into a plurality of uniform sizes to include the DC balance information for each division region, and includes the start and end information in the entire data to include the actual information having the surplus information. Transmitting the serial data over the serial channel by encoding the transmission data; The receiver generates a clock signal corresponding to the data rate by using a frequency detection method on the actual transmission data received through the serial channel, and restores a clock by adjusting a phase of a synchronized clock through a linear phase detection method. And a receiving step of acquiring data from the actual transmission data, decoding and outputting the original data from which the surplus information is removed, and outputting the original data. The method of claim 12, wherein the receiving step The actual transmission data is sampled by using the built-in voltage controlled oscillator output of the multiple stages, and the operating frequency band of the voltage controlled oscillator of the multiple stages is input by inputting the sampled signal, the actual transmission data and the voltage controlled oscillator output. A frequency band determination step of generating a cursor code for determining; The voltage controlled oscillator frequency of the multiple stages is detected until the output of the voltage controlled oscillator operating at the maximum speed of the selected frequency band and the actual transmission data are synchronized by detecting the frequency difference. A frequency synchronization step of adjusting downward; After the frequency synchronizing step, a phase synchronizing step of adjusting a control voltage of the voltage controlled oscillator of the multiple stages so as to synchronize the linear phase of the voltage controlled oscillator output of the multiple stages and the actual transmission data. Communication method of serial transceiver. The method of claim 13, wherein the receiving step A data output for outputting a data enable signal in parallel with the clock signal synchronized by the phase synchronization step, and outputting a data enable signal indicating that an output signal is available by detecting a start bit included in the synchronized signal; Communication method of a serial transceiver device comprising the step.

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