WO2005099164A1

WO2005099164A1 - Clock recovery in an oversampled serial communications system

Info

Publication number: WO2005099164A1
Application number: PCT/RU2005/000167
Authority: WO
Inventors: Igor Anatolievich Abrosimov; Alexander Roger Deas; David Coyne
Original assignee: Igor Anatolievich Abrosimov
Priority date: 2004-04-01
Filing date: 2005-04-01
Publication date: 2005-10-20

Abstract

The present invention relates to the recovery of a clock from the parallel data bits in an over-sampling receiver and a method using the same. A high-speed receiver according to the invention comprises a sampling system which provides a set of samples of the received signal; provided with a multiphase clock generator; and a dual phase detector PLL configured with a clock recovery phase detector, a phase and frequency detector and a lock detector; wherein the frequency lock detector determines when lock is achieved, and once achieved, switches the phase detector to the clock recovery phase detector which extracts the frequency of the data from the over-sampled data to generate signals to achieve the clock recovery.

Description

CLOCK RECOVERY IN AN OVER SAMPLED SERIAL COMMUNICATIONS SYSTEM

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a Continuation-in-Part of US 10/038,868 filed on 08 January 2002 claiming priority from US Provisional application 60/317,216 filed 06 September 2001 , and also claims priority from US Provisional application 60/558,154 filed on 01 April 2004, the entire specification of which applications is incorporated by reference herein.

BACKGROUND OF THE INVENTION Technical Field The present invention relates to the communication of signals, in particular, to the reception of digital signals. More specifically, the present invention relates to the recovery of a clock embedded within a serial data stream in a communications sysFem. The present invention is particularly applicable to interfaces between integrated circuits and for high-speed communications. The present invention is further applicable in test equipment for testing semiconductor memories and logic. Background of the Invention One common form of communications system involves digital signals representing data that is sent over wires or another communication medium, called a communication channel. In a communication system, a clock is often embedded within the data and transmitted through the communications channel. This clock may be decoded within the receiver at the far end of the communications channel and used for retransmission of the same data, for example, in a re-timer device. In such a system the data may be transmitted at the same frequency as the data is received. This is sometimes termed clock forwarding. In other systems it is permissible to re-transmit the received data at a frequency that is different to the frequency of the received data. In this type of system additional symbols or code words are inserted or deleted to match the received data rate to the transmitted data rate. This is sometimes termed rate adaptation. Consider the IEEE XFP standard, revision 3.0 as an example of a communications system that allows clock forwarding. The IEEE XFP standard allows for two modes of operation in an XFP module. The first mode of operation employs an external reference clock that is only used as a centering aid for the receiver phase locked loop (PLL). It is then the responsibility of the XFP module to extract the clock from the received data and use the clock to re-transmit the data at the same frequency as the received data. In the second, optional mode, a low noise clock synchronised to the incoming data is generated external to the XFP module as the reference clock. In the second mode of operation the reference clock is used with a clock multiplying PLL to re-transmit the data at a multiple of the reference clock. The drawback to this mode of operation is the cost of implementing a low-noise oscillator within the XFP host. This additional cost moves the XFP module designer to demand ASIC's that recover the clock from the data. In a communications system that uses over-sampling in the receiver, there are distinct benefits of using rate adaptation such as the improved tolerance to random jitter and eye-tracking, see, for example WO 02/078228 (US 10/038,868) and US provisional application 60/552,723 filed 15.03.2004, the entire specifications of these applications being incorporated by reference herein. In order to obtain the benefits of such a system and offer a solution that does not require a low noise external reference, clock recovery needs to be performed while retaining as many of the original benefits of over-sampling as possible. Similar problems arise in test systems for testing semiconductor devices; where each new generation of devices should be tested at the maximum speed of the new device. A testing apparatus for a digital circuit generates various waveforms at a desired timing and detects the voltage level of the waveforms, usually comparing data read from the device under test with what is expected. Thus, the receiver parameters are ones of the most critical specifications of a tester. Figure 1 shows a block diagram of a system for receiving serial data and decoding the same serial data into a parallel data word at a lower data rate, based on the over-sampling technique disclosed in US 10/038,868, the specification of which application is incorporated by reference herein in its entirety. The serial data stream signal 100 is conditioned by methods of amplification and equalisation by buffer 110, to an amplitude level where it is able to drive the input of a number of samplers 120 with their inputs connected in parallel. The clock input of each sampler is connected to one of the outputs of a sampling clock generator PLL 130. The sampling clock generator PLL 130 operates at a frequency of one-half of the data rate for example, 5GHz for a 10Gbps data stream. The outputs of the sampling clock generator PLL 130 are nominally equally-spaced in time and in this example, for a 5GHz oscillation frequency and an over-sampling ratio of 16X, each output is separated by 1/16^th of the period, i.e. 6.25ps. The sampling clock generator PLL 130 is locked to a reference frequency 160 of frequency 156.25MHz that may be asynchronous to the data frequency. The multi-phase outputs 135 of the sampling clock generator PLL 130 are connected to the clock inputs of samplers 120. Each phase samples the received data in the samplers 120. The outputs of the samplers 120 are passed to a deserialising circuit 140 that converts the serial data stream into a parallel data word 150. The parallel data word 150 represents 16 bits of the input signal sampled at 16X per bit, giving a total of 256 data bits every 2.56ns. The deserialiser 140 also produces a single clock output 170 to which all the deserialiser output data bits are aligned. The clock 170 is a divided version of one phase of the sampling clock generator 130 and is fed-back to the sampling clock generator PLL that is locked to the reference frequency 160. A conventional phase and frequency detector is used to produce an error signal that drives a charge pump. In turn the charge pump, in conjunction with the PLL loop filter, generates a control voltage to drive the VCO in the sampling clock generator and maintain the VCO feedback clock 170 locked to the reference frequency 160. The parallel output word 150 from the deserialiser 140 is passed to a signal processor block 180 that performs data recovery, eye tracking and other such functions.lt is possible to implement an over-sampling receiver that also performs clock recovery. One possible option would be to place a traditional clock recovery circuit in parallel with the over-sampling receiver. The disadvantage of this scheme is that additional hardware has to be implemented to operate at the same frequency as the data rate. This hardware may contribute significantly to the overall power dissipation. An example of a typical clock and data recovery circuit that operates on a serial data stream is described in patent 4,535,459 to Hogge et al. Another clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal is described in US 6,738,922 to Warwar et al. The clock recovery unit includes a frequency detection circuit and a phase locked loop (PLL) circuit to detect phase and frequency differences between a reference clock signal and a variable clock signal, and to adjust the variable clock frequency to recover a clock signal that corresponds to the transmitted data signal. This clock recovery unit does not operate on over-sampled data but uses a digital phase tracking circuit and eliminates the need to have high-level circuitry switch between two phase detectors while trying to achieve lock. A further example of a clock and data recovery circuit that operates on a serial data stream is shown in Figure 2A. Figure 2A shows an implementation of a serial-data recovery phase detector based on a circuit known as a half-rate bang- bang phase detector. The data is over-sampled twice per bit using quadrature clocks CKO and CK90 running at half the data rate. For example for a 10Gbps data rate these clocks could be generated by a 5GHz VCO with quadrature outputs or a VCO combined with a poly-phase filter. The data is sampled on each edge of the CKO and CK90 clocks in dual edge triggered flip-flops 210 and 220 respectively, producing the signals Q1 and Q2. It can be seen in the timing diagram of Figure 2B that when the clock CKO leads the data, Q1 will lag Q2. It can also be seen in the timing diagram of Figure 2C that when the clock CKO lags the data, Q1 leads Q2. Using the relationship between Q1 and Q2 can indicate whether to advance or retard the phase of the VCO. This relationship can be obtained by using Q1 to sample Q2. Latches 240 and 230 latch Q2 on rising and falling edges of Q1. Multiplexer 250 selects the output of latch 230 or 240 dependent on the polarity of Q1 , generating the signal Q3. It is the signal Q3 that indicates whether the clock leads the data or the clock lags the data. When there is a rising edge on Q1 , Q3 becomes equal to Q2 and when there is a falling edge on Q1 , Q3 becomes equal to the inverse of Q2. Q3 will be high when the clock leads the data and low when the clock lags the data. The signal Q3 could be used to drive the charge pump but in the situation where there are no data transitions produces a signal that causes the charge pump to continuously drive the loop-filter. Long periods of no data transitions produce excessive jitter on the VCO output. It is more useful to gate the signal Q3 by a conditioning pulse when a data transition is present. In the example shown in Figure 2A, the conditioning pulse is generated by the latches 260 and 270 and the XOR gate 280. In conjunction with Q3 the transition detector generates UP and DN pulses to drive a charge pump. In the absence of data transitions no UP or DN pulses. The logic block 290 generates the UP and DN pulses and the detailed implementation is obvious to someone skilled in the art. See for a further example, the paper by J.D.H. Alexander entitled "Clock Recovery from Random Binary Signals", Electronic Letters, Vol. 11 , No. 22, pages 541-2 (Oct. 1975). Another technique for clock and data recovery using multiphase clocks and over-sampling is described in patent 6,035,409. In this patent a delay locked loop generates clock phases at twice the data rate, that is, it employs an over-sampling ratio of 2X. Five bits of data are decoded directly from the incoming serial data stream. A single pumpup or pumpdn pulse is generated dependent on a majority voting system, thus losing some information related to the magnitude of the average phase error. This architecture is not particularly suited to an over- sampling receiver architecture described in WO 02/078228 (US 10/038,868). The implementation of a clock recovery circuit as detailed in Figure 2A in an over-sampling receiver would duplicate components that already exist, increasing power and area. It is highly advantageous to be able to recover the clock in an over-sampling receiver without a significant increase in power dissipation or component count. A clock and data recovery unit for recovering a received serial data bit stream having a phase adjustment means for adjustment of a sampling time in the center of a unit interval of an oversampled received data stream is disclosed in US patent application 2004/0202266 by Gregorius et al. The phase adjustment means comprises a multiphase clock generator; a deserialiser, a phase detection unit for detecting a phase difference between the received serial data bit stream and the rotated reference phase signal. In other words, the system described in 2004/0202266 by Gregorius et al operates on a parallel data word to recover the clock, uses EXOR gates between adjacent data samples to determine whether a transition has occurred in the input data, and uses that information to drive a loop filter. It would appear that in the Gregorius invention the manner in which the data frequency is tracked is through continuous adjustment of the phase generation. However, it is impossible to use the information from the transition detector to control an oscillator (VCO) to track the data frequency as there is no phase locked loop associated therefore. That is, in the Gregorius invention, a fixed reference frequency generates multiple phases from a delay locked loop at the same frequency as the reference frequency or multiple of the reference frequency. These phases are fed to a phase interpolation unit where control signals produce sampling phases aligned to the data. The effective frequency of the sampling signals to the over-sampling unit may be varied by continuous adjustment of the control signals. When the data frequency is higher than the reference frequency, the control lines to the phase interpolation unit continuously advance the output phases, thus effectively increasing the sampling frequency. Similarly, when the data frequency is lower than the reference frequency, the control lines to the phase interpolation unit retard the output phases. However, although the information from the transitions is used to drive the loop filter, a delay locked loop is used to generate fixed frequency clock phases and therefore, it shall be assumed that the reference frequency is not locked to the data frequency. This prevents from the accurate reading of data signals. Further, the digital control unit may track frequency differences between the reference frequency/delay locked loop and the data by controlling the manner in which sampling phases are generated, advancing or retarding all phases to maintain frequency lock between the data and the frequency of the sampling phases, however this technique is far from being sufficient for high frequency applications.

Furthermore, it is common with this technique that glitches may be generated when the phase interpolator is being changed and this can cause incorrect sampling or erroneous decoding of the data.

OBJECT OF THE PRESENT INVENTION It is therefore a primary objective of the present invention to provide a system that can be used to extract the clock from the data in an over-sampling receiver. It is another primary objective of the present invention to extract the clock from the data in an over-sampling receiver without the penalty of significant power dissipation. It is another primary objective of the present invention to provide a clock recovery circuit that can be economically implemented in a semiconductor integrated circuit. It is a further objective of the current invention to offer a clock recovery circuit that maintains improvements obtained from over-sampling techniques. Still further objective is to provide a testing system capable of efficient phase noise reduction.

BRIEF SUMMARY OF THE INVENTION The present invention relates to a device and method that performs clock extraction from an over-sampled data stream while maintaining the benefits of over-sampling along with lower power dissipation and circuit size. According to the invention, a high-speed receiver comprises: a sampling system which over-samples the data and provides a set of samples of the received signal; provided with a voltage controlled oscillator (VCO) generating multiple clocks for spreading the samples in time so that each bit interval is covered by several samples; the receiver further comprising a dual phase detector phase locked loop configured with a clock recovery phase detector, a phase and frequency detector and a lock detector; wherein the phase and frequency detector locks the VCO to an external reference frequency that is close to, but not exactly equal to, the frequency of the sampled data, and within the capture range of the clock recovery phase detector, wherein the frequency lock detector determines when lock is achieved, and once achieved, switches the phase detector to the clock recovery phase detector which extracts the frequency of the data from the over-sampled data to generate signals to achieve clock recovery. Preferably, the receiver further comprises a deserialising circuit connected to the output of the set of samplers, for converting the serial data stream into a parallel data word, wherein the output from the multiple clock generator is processed in the deserialising circuit to produce a feedback clock signal fed to the sampling clock generator PLL, whereby the multiple clock generator is adjusted to the frequency of data. Preferably, the clock recovery phase detector comprises a transition detector that compares each pair of adjacent samples in a data stream to detect data transitions. The obtained transition bits are further processed in an up-down detector which generates a plurality of control signals. Preferably, the clock recovery phase detector further comprises a multiplexer for selecting said up and down signals depending on said control signals, a charge pump which generates a control voltage to drive the VCO and maintain the VCO feedback clock locked to the reference frequency, and a loop filter for. Preferably also the clock recovery phase detector comprises a set of registers for pipelining the extracted data bits from the over-sampled data. The registers can be same as used by the sampling system. According to another aspect, a method of clock recovery is provided using a high speed receiver with clock recovery according to the first aspect of the invention. In still another aspect, an integrated circuit incorporating a high speed receiver with clock recovery according to the invention is provided. In a further aspect, a test apparatus is provided for high speed testing a memory device under test, the test apparatus comprising a transmitter for transmitting test signals for testing the memory device under test; a receiver for receiving the resulting test data signals from the memory device under test, the receiver comprising a sampling system which over-samples the test data and provides a set of samples of the received signal; and a reference clock generator for generating multiple clocks for spreading the samples in time so that each bit interval is covered by several samples, wherein the receiver further comprises a dual phase detector phase locked loop configured with a clock recovery phase detector, a phase and frequency detector and a lock detector; which locks the clock generator to an external reference frequency that is close to, but not exactly equal to, the frequency of the sampled data, and within the capture range of the clock recovery phase detector, wherein the frequency lock detector determines when lock is achieved, and once achieved, switches the phase detector to the clock recovery phase detector which extracts the frequency of the data from the over-sampled data to generate signals to achieve clock recovery.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality to the accompanying drawings in which: Figure 1 shows an over-sampling receiver as described in WO 02/078228. The receiver produces a parallel data word after deserialisation for processing to determine the optimum eye and eye tracking. The sampling clock generator is locked to an external reference clock source. Figure 2A shows an implementation of a serial, data recovery phase detector. Figure 2B shows a timing diagram for the data recovery phase detector in Figure 2A in the case where the clock leads the data. Figure 2C shows a timing diagram for the data recovery phase detector in Figure 2A in the case where the clock lags the data. Figure 3 shows a dual phase detector PLL. One phase detector is used to achieve initial frequency lock to an external reference and a second phase detector is used to lock to the incoming data. Figure 4 shows the separation of the desired samples from a series of samples in the over-sampled data word Figure 5A shows a block diagram of the parallel-data clock recovery phase detector. Figure 5B shows the preferred implementation of the transition detector used in the parallel data phase detector Figure 5C shows the preferred implementation of the UP_DN detector used in the parallel data phase detector Figure 6A shows a conventional charge pump implementation. Figure 6B shows a block diagram of an alternative charge pump with multiple control signals. Figure 6C shows the preferred implementation of charge pump the multiple control signals. Figure 7 shows the preferred implementation of a multiplexer for selecting the UP and DN signals from the two phase detectors. Figure 8 shows an example embodiment of a memory test system using an over sampling receiver with clock recovery function in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION The invention will now be described in detail without limitation to the generality of the present invention with the aid of example embodiments and accompanying drawings. It is well known that certain types of phase detectors used in PLL's that attempt to achieve frequency lock to a random data stream may result in locking to a harmonic or sub-harmonic of the data frequency. To circumnavigate this problem a dual phase detector PLL architecture is often used. In this approach the PLL is first configured using a conventional phase and frequency detector and locks the VCO to an external reference frequency that is close to, but not exactly equal to, the frequency of the data, and within the capture range of the clock recovery phase detector. A frequency lock detector is then used to determine when lock has been achieved and once achieved, switches the phase detector to the second data recovery phase detector. The PLL thus avoids locking to an incorrect frequency component in the incoming random data stream. In many communications systems a reference clock is supplied that, when multiplied up in a PLL, is very close to the frequency of the incoming data stream. This external reference clock is only used to help centre the PLL and does not have to have very low phase noise. An example is the external reference clock specified in the IEEE XFP standard. In this standard, the external reference clock is at a frequency of 1/64^th of the data rate. The absolute frequency of this reference clock may only deviate by 100ppm from the nominal frequency and the maximum difference between the external reference and the data frequency may be as much as 200ppm. Figure 3 shows the block diagram of a sampling clock generator PLL, such as the sampling clock generator 130 shown in Fig. 1 , that uses two phase- detectors and an external reference clock to perform initial frequency locking. The PLL comprises of a clock recovery phase detector 310, a dual 2-to-1 multiplexer 320, a charge pump 330, a multiphase voltage controlled oscillator (VCO) 340, a phase and frequency detector 350, a lock detector 360 and a loop filter 370. By means of an example, this PLL is configured to operate at 5GHz with an ^■ external reference of 156.25MHz and a random data stream of 10Gbps. To achieve the initial lock, the phase and frequency detector 350 is selected in conjunction with the external 156.25MHz reference clock 160. The output of the phase and frequency phase detector 350 will generate the UP0 and DN0 signals which are selected by the multiplexer 320 to drive the charge pump 330. The voltage on the loop filter 370 then drives the VCO 340 to attain lock. The output of the VCO is divided down in the deserialiser 140, producing the PLL feedback signal 170. Lock detector 360 determines when the PLL is frequency locked. Once lock to the reference clock 160, is achieved the lock detector 360 swaps the inputs to the charge pump 330 over to the clock recovery phase detector 310. In the current invention sampled data bits are taken from the parallel data word 150 and processed to produce the signals UP1 and DN1 to drive charge pump 330. The present invention includes a step of over-sampling input data signal 16x (16 times) and a step of comparison of pairs of samples separated by a further 16 samples. In other words, the sample that is used for comparison is one sample from each bit-cell, not adjacent over-sampled data bits. Furthermore, additionally, a second set of data transitions is produced from the over-sampled data stream by repeating the same process but offseting the over-sampled data stream by 8 samples. Thus, the above technique is very different from Gregorius patent application where an input signal is over-sampled by a factor of 4x and adjacent data samples in the over-sampled data stream are compared to detect a transition. Figure 4 shows how the desired samples required for clock recovery can be stripped out of the 256-bit over-sampled data word. Bits corresponding to the 0- degree sampling clock edges are defined as bits 0, 16, 32 and so forth up to 240. Bits corresponding to the 90-degree clock sampling clock edges are defined as bits 8, 24, 40 and so forth up to bit 248. A selective clock recovery from portions of digital data signal best suited therefore is disclosed in US 6,229,862 to Webb. A digital data signal is assessed to determine the occurrence of a peak in part of the signal and the suitability of that peak for providing timing information. According to this method, a peak detector determines the maximum over-sampled value in a symbol period and the sampling point at which that maximum occurred. The peak score associated with the maximum is compared with a similarly established minimum peak score and, if the selected score exceeds a threshold, updates a phase lock loop, with the sampling point at which that peak occurred. The implementation of the scheme detailed in US 6,229,862 at the serial data rates involved in 10Gbps communications is not possible without excessive power dissipation. The excessive power dissipation would result due to the large amount of logic that would have to be implemented to operate at the sampling rate that could be many times the serial data rate. The current invention performs operations on the data at a clock rate significantly lower than the symbol rate resulting in ease of implementation in standard CMOS technologies and at a lower power dissipation. According to the present invention, bits for clock recovery are selected in predetermined time intervals, with no regard to the amplitude of a data signal. Thus, it is also possible to use sampled data bits 1 , 17, 33 etc to represent data bits corresponding to the 0-degree clock and sampled data bits 9, 25, 41 etc to represent data bits corresponding to the 90-degree clock. This has become possible thanks to the oversampling technique used in US 10/038,868. In general, the samples corresponding to the 0-degree and 90-degree clocks must be spaced 16 bits apart. Further, 8 bits must separate the individual samples selected for the 0-degree clock and 90-degree clock. The data bits corresponding to the 0-degree clock edges are placed in register Q1 <31 :0> with the least significant bit corresponding to the bit 0 of the over-sampled data word. The data bits corresponding to the 90-degree clock edges are placed in register Q2<31 :0> with the least significant bit corresponding to the bit 8 of the over-sampled data word. Figure 5A shows a block diagram of the clock recovery phase detector 310. The clock recovery phase detector consists of four registers 510, 520, 530 and 540 used to pipeline the stripped data bits from the over-sampled data. Register 510 comprises of the samples corresponding to the 0-degree clock phase that is, data bits 0, 16, 32 and so forth up to data bit 240. The output of register 510 is labeled Q1A<31 :0>. Register 520 comprises of the samples corresponding to the 90-degree clock phase that is, data bits 8, 24, 40 and so forth up to data bit 248. The output of register 520 is labeled Q2A<31 :0>. Register 530 comprises of a delayed version of the data in register 510. The output of register 530 is labeled Q1 B<31 :0>. Register 540 comprises of a delayed version of the data in register 520. The output of register 540 is labeled Q2B<31 :0>. All of the registers 510, 520, 530 and 540 are generally already available in the signal processor 180 and do not constitute an overhead to the total circuit gate count. The data bits Q1 B<31 :0> and Q1A<31 > are processed in the transition detector 550, generating two sets of output data TR01<31 :0> and TR10<31 :0>.

Digital high's in buses TR01 and TR10 indicate whether 0-to-1 and 1-to-0 transitions respectively have been detected Figure 5B shows the preferred embodiment of the transition detector. The outputs from the individual register bits of Q1 B<31 :0> plus Q1A<31> are combined in pairs to detect whether adjacent bits of the data stream are different.

The data bits are paired Q1A<31 > and Q1 B<0>, Q1 B<0> and Q1 B<1 > and so forth up to Q1 B<30> and Q1 B<31 > In this manner all pairs of adjacent data samples are continuously compared. The logic for detecting data transitions between adjacent pairs of bits is straightforward to someone skilled in the art. The transition bits are processed in the UP DN detector 560 along with bus

Q2B. The UP_DN detector 560 generates two output buses UP and DN, both 32 bits wide. Figure 5c shows the preferred embodiment of the UP_DN detector. The following rules are implemented in this logic - When there is a 0 to 1 transition and the corresponding value of Q2 is low an UP1 pulse is generated, - When there is a 0 to 1 transition and the corresponding value of Q2 is high a DN1 pulse is generated, - When there is a 1 to 0 transition and the corresponding value of Q2 is low a DN1 pulse is generated, - When there is a 1 to 0 transition and the corresponding value of Q2 is high an UP1 pulse is generated The logic for implementing the above rules is straightforward to someone skilled in the art. Figure 6A shows a charge pump used in a conventional PLL to drive current into a loop filter, that in turn generates a voltage that changes the VCO frequency towards the stable operating point where the VCO frequency is matched to the incoming data frequency The conventional charge pump has only one UP and one DN signal. A current source formed by the transistor 601 is placed in series with a switch formed by a PMOS transistor 602 Current is injected into the loop filter by the UP signal controlling the PMOS switch 602. Applying a digital low signal to the gate of PMOS transistor 602 will place the PMOS transistor into a low impedance state and allow current to flow into the loop filter from the PMOS current source 601. A digital high signal applied to the PMOS switch 602 will place the switch in a high impedance state and disable current flow into the loop filter from current source 601. Similarly, a current source formed by NMOS transistor 603 is controlled by the NMOS switch 604. Applying a digital high to the gate of the NMOS transistor 604 will place the NMOS transistor into a low impedance state and allow current to flow out of the loop filter through the NMOS current source 603. A digital low signal applied to the NMOS switch 604 will place the switch in a high impedance state and disable current flow out of the loop filter through NMOS current source 603. This invention has a plurality of UP and DN control signals generated by the UP_DN detector 560 in the clock recovery phase detector 310. One method by which these UP and DN control signals may be combined would be to count the number of ones in the UP bus, count the number of ones in the DN bus and subtract the two counts to obtain a resulting count. The resulting count would then be applied to the input of a digital to analogue converter. The digital to analogue converter would produce an output current that could drive the loop filter 370 directly. The output of the digital to analogue converter would take on a number of discrete current levels with a zero current level being obtained when the number of UP and DN control signals was equal. Another implementation of the charge pump with a plurality of UP and DN control signals is shown in Figure 6B. Figure 6B shows a plurality of current sources 610 each in series with a switch 620, each switch being uniquely controlled by one element of the UP bus. Each switch allows current to be inserted into the loop filter. In addition, a plurality of current sources 630 each in series with a switch 640, each switch being uniquely controlled by one element of the DN bus allows current to be removed from the loop filter. Each switch 620 comprises a controlling terminal 621 and two non- controlling terminals 622 and 623. An appropriate signal level on the controlling terminal 621 creates a low impedance state between terminals 622 and 623, placing the switch in the ON condition. A signal of opposite polarity applied to the controlling terminal 621 creates a high impedance state between terminals 622 and 623, placing the switch into the OFF condition. Each signal in the UP bus is connected to the controlling terminal of a switch 620 in series with a current source 610. One terminal of each current source 610 is connected to the positive supply and the other terminal is connected to one non-controlling terminal of a switch 620. The other non-controlling terminal of the switch 620 connects to the common node that is connected to the loop filter of the PLL. A signal of the correct polarity on the controlling terminal of the switch enables a connection between the other two terminals of the switch 620, allowing current to flow into the loop filter from the positive supply, 3.3 Volts. Each signal in the DN bus is connected to the controlling terminal of a switch 640 in series with a current source 630. One terminal of each current source 630 is connected to the negative supply and the other terminal is connected to one non-controlling terminal of a switch 640. The other non- controlling terminal of the switch 640 connects to the common node that is connected to the loop filter of the PLL. A signal of the correct polarity on the controlling terminal of the switch enables a connection between the other two terminals of the switch 640, allowing current to flow out of the loop filter to the negative supply, 0 Volts. Figure 6C shows the preferred implementation of Figure 6B. Current sources 610 are formed from PMOS transistors 660. A voltage VBP on the gate of the PMOS transistors 660 causes current to flow from the source to the drain. Similarly, the current sources 630 are formed from NMOS transistors 680. A voltage VBN on the gate of the NMOS transistors 680 causes current to flow from the source to the drain. This gate voltage may be controlled in a number of ways in which someone skilled in the art can readily interpret. Switches 670 and 690 formed by PMOS and NMOS transistors respectively control current sources 660 and 680 respectively. PMOS transistors 670 form the switches 620. The gate, drain and source terminals of transistors 670 equate to the controlling terminal 621 and non- controlling terminals 622 and 623 respectively of switches 620. A digital low signal applied to the gate terminal of PMOS transistor 670 will place the transistor into the low impedance state and allow current to flow from the current source PMOS 660 into the loop filter. A digital high signal applied to the gate of the PMOS transistor 670 will place the transistor in a high impedance state and block current flow into the loop filter from PMOS current source 660. NMOS transistors 690 form the switches 640. The gate, drain and source terminals of transistors 690 equate to the controlling terminal 641 and non- controlling terminals 642 and 643 respectively of switches 640. A digital high signal applied to the gate terminal of NMOS transistor 690 will place the transistor into the low impedance state and allow current to flow from the loop filter through the current source NMOS 680 to the negative supply. A digital low signal applied to the gate of the NMOS transistor 690 will place the transistor in a high impedance state and block current flow out of the loop filter through the current source NMOS 680 to the negative supply. It is obvious to someone skilled in the art that other implementations of the charge pump are possible in other technologies and with other topologies. Figure 7 shows the preferred embodiment of the dual 2-to-1 multiplexer

320. There is only one UP0 and one DN0 signal from the phase and frequency detector 350. These signals can be connected to multiple inputs of the multiplexer 320 to allow for any difference in the gains between the phase detectors 310 and 350. The gain of the recovered clock phase detector is a function of the transition density which may vary from one system to another dependent on any code that is applied to the data. The transition density will always result in the gain of the clock recovery phase detector 310 being equal to or lower than the gain of the phase and frequency detector. Accordingly the gain of the charge pump 330 may be reduced to maintain stability and open-loop bandwidth when the phase and frequency detector 350 is selected. The reduced gain may be set by connecting the UP0 and DN0 signals to a limited number of the multiplexer 320 inputs and connecting the remaining inputs to 0 volts. Be means of an example the UP0 and DN0 signals are connected to 12 of the 32 2-to-1 multiplexers 321 in Figure 7. The embodiment of the 2-to-1 multiplexer 321 in Figure 7 is obvious to someone skilled in the art. In Fig.8, an example embodiment of the memory test system in accordance with the proposed invention is presented. The system is intended for testing a synchronous memory device under test 4, e.g. a DDR SDRAM type. A test pattern generator 11 provides an appropriate sequence of test signals including address, data, control and clock signals. Preferably, the test pattern generator can be any commercially available or manufactured by Acuid Corporation Ltd. Illustrated in Fig.8 are data transmitters 9 for driving the test signals from the test pattern generator to the memory device 4 under test, and receivers 1 for receiving a response data signal from the memory device 4 under test. A preferable transmitter for use within the claimed memory test system can be any commercially available transmitter. A preferable receiver for use within the claimed memory test system can be an over-sampling receiver as disclosed in US 10/038,868, the whole specification of which application being incorporated by reference herein. Connected to the outputs of the receivers is a fault comparator or fault logger 3 for comparing the response data signal received from the memory device with the expected data fed directly from the test pattern generator. The fault logger 3 can be constituted by a digital comparator. Preferably, the signals are transmitted from the transmitters to the device 4 under test via a relay matrix (not shown in the drawings for simplicity) to permit switching on/off the device 4 from the test system. The system operates as follows. The test pattern generator 11 generates an appropriate sequence of test signals fed to the transmitters 9 and then transmitted to the device 4. The response signals are outputted into the receivers 1 , and the data are fed to the fault logger 3 which compares real it with the expected reference data coming from the test pattern generator 1. The fault data from the fault logger 3 can further be downloaded to a central control unit of a controlling computer which preferably holds the accumulated data in an encoded format. The fault data can also be represented in a bitmap format for viewing the faults. Although the preferred embodiment only has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A high speed receiver comprising: a sampling system (120) for receiving an input data signal (100), over-sampling the received data signal and providing a set of samples (125) of the received data signal (100); a sampling clock generator phase locked loop (PLL) (130) connected to a source of external reference frequency (160) and provided with a multiple clock generator (340) for generating multiple clocks (135) for spreading the samples (125) in time so that each bit interval is covered by several samples; a deserialising circuit (140) connected to the output of the set of samplers (120), for converting the serial data stream into a parallel data word (150); wherein the output from the multiple clock generator (340) is processed in the deserialising circuit (140) to produce a feedback clock signal (170) fed to the sampling clock generator PLL (130), whereby the multiple clock generator is adjusted to the frequency of data.

2. 2. A receiver according to claim 1 , wherein the sampling clock generator phase locked loop comprises: a first phase detector (350) for achieving initial frequency lock to an external reference frequency (160); and a second phase detector (310) for locking to the frequency of the incoming data to achieve clock recovery.

3. A receiver according to claim 2, wherein the second phase detector (310) is a clock recovery phase detector, which extracts frequency of data from the over- sampled data and generates control signals to control the multiple clock generator.

4. A receiver according to claims 2 or 3, wherein the first phase detector (350) is a phase and frequency detector, which produces signals indicative of the difference between the external reference frequency (160) and the feedback clock signal (170).

5. A receiver according to any one of claims 2 to 4, wherein the sampling clock generator phase locked loop further comprises a frequency lock detector (360) for determining if the initial lock to an external reference frequency (160) is achieved by the multiple clock generator (340), and once the lock is achieved, switching from the phase and frequency detector to the clock recovery phase detector

6. A receiver according to any one of claims 2 to 5, wherein the clock recovery phase detector comprises a transition detector, which compares each pair of samples from adjacent bit cells in the parallel data word formed from the over- sampled serial data stream to detect data transitions.

7. A receiver according to any one of claims 2 to 6, wherein the input of the clock recovery phase detector (310) is connected to the output of the deserialising circuit (140) and the input data signal (1 10)

8. A receiver according to any one of claims 2 to 7, wherein the input of the phase and frequency detector (350) is connected to the external reference (160) and the feedback clock signal (170) from the multiple clock generator.

9. A receiver according to any one of claims 1 to 8, wherein the multiple clock generator is a multiphase voltage controlled oscillator (VCO).

10. A receiver according to claim 6, wherein the obtained transition bits from the transition detector are further processed in an up-down detector which generates a plurality of control signals for controlling the VCO frequency.

11. A receiver according to any one of claims 1 to 10, further comprising a multiplexer for selecting said UP and DN signals depending on the control signal from a frequency lock detector

12. A receiver according to any one of claims 1 to 11 , further comprising a charge pump which generates a control voltage to drive the VCO and maintain the VCO feedback clock locked to the reference frequency or data.

13. A receiver according to any one of claims 1 to 12, wherein the external reference frequency for locking VCO is close to, but not exactly equal to, the frequency of the sampled data

14. A receiver according to any one of claims 1 to 13, wherein the external reference frequency for locking VCO is within the capture range of the clock recovery phase detector.

15. A receiver of any one of claims 2 to 14, wherein the clock recovery phase detector comprises a set of registers for pipelining the extracted data bits from the oversampled data.

16. A receiver of any one of claims 9 to 15, wherein the multiplexor is a dual 2:1 multiplexor.

17. A receiver of any one of claims 1 to 16, wherein two sets of samples are selected, spaced 16 bits apart and offset by 8 samples.

18. A receiver of any one of claims 10 to 17, wherein the charge pump has a plurality of UP and DN inputs.

19. A receiver of any one of claims 10 to 18, wherein an alternative charge pump is implemented from the summation of the UP and DN bits generating a digital word to drive a digital to analogue converter.

20. A receiver of any one of claims 10 to 19, wherein the charge pump gain may be controlled by connecting the UP and DN signals from the phase and frequency detector to selected inputs of the plurality of charge pump input terminals and grounding the remaining input terminals.

21. A receiver according to any one of claims 2 to 20, wherein the clock recovery phase detector utilises components already present in the over-sampling receiver and low additional component count in implementing the clock recovery phase detector.

22. A receiver according to any one of claims 6 to 21 , where the phase number of the transition with respect to the recovered clock is used as an output from the receiver.

23. A method of clock recovery from a stream of over-sampled data, using an oversampling receiver of any one of claims 1 to 22.

24. A method of clock recovery from a stream of over-sampled data, comprising the steps of: receiving an input data signal; over-sampling data to provide a set of samples of a received signal; generating multiple clocks by a clock generator for spreading the samples in time so that each bit interval is covered by several samples; selecting an external reference frequency for the multiple clocks; locking a clock generator to the selected external reference frequency; and extracting the frequency of the sampled data from the over-sampled data; generating signals bearing the extracted frequency to achieve clock recovery.

25. A method of clock recovery of claim 24, wherein the initial lock is performed by a phase and frequency detector.

26. A method of clock recovery of claims 24 or 25, wherein, to determine that lock is achieved, a frequency lock detector is used.

27. A method of clock recovery of any one of claims 24 to 26, wherein the frequency of the data is extracted from the over-sampled data by a clock recovery phase detector.

28. A method of clock recovery of claims 24 to 27, wherein, first, it is determined that the lock is achieved, and then, the frequency lock detector switches from the phase and frequency detector to a clock recovery phase detector which extracts the frequency of the data from the over-sampled data to generate signals to achieve clock recovery.

29. A method of clock recovery of claims 24 to 28, wherein the external frequency is selected close to, but not exactly equal to, the frequency of the sampled data.

30. A method of clock recovery of claims 24 to 29, wherein the external frequency is selected within the capture range of a clock recovery phase detector.

31. A method of clock recovery of any one of claims 24 to 30, wherein each pair of adjacent samples in the parallel data word is formed from the over-sampled serial data stream is compared to detect data transitions.

32. A method of clock recovery of claim 31 , wherein the obtained transition bits are further processed in an up-down detector which generates a plurality of control signals for controlling the VCO frequency.

33. An integrated circuit incorporating an oversampling receiver with clock recovery function according to any one of claims 1 to 22.

34. A test apparatus for high speed testing a memory device under test, the test apparatus comprising: a transmitter for transmitting test signals for testing the memory device under test; a receiver for receiving the resulting test data signals from the memory device under test, the receiver comprising a sampling system which over- samples the test data and provides a set of samples of the received signal; and a reference clock generator for generating multiple clocks for spreading the samples in time so that each bit interval is covered by several samples, wherein the receiver is as claimed in any one of claims 1 to 22.

35. A test system of claim 34, wherein the polarity of the received signal is detected and stored along with the phase number of the transition with respect to the recovered clock for that transition.

36. A test system of claim 34, wherein the data bits are oversampled and the samples stored, with a finite state machine performing the clock data recovery.