KR19980019934A - Piel for Clock / Data Recovery Using Multiphase Clock - Google Patents

Abstract

The present invention relates to a PEL for recovering clock / data using a multi-phase clock. In the related art, it is inconvenient when a phase is adjusted to a system using a delay element to adjust an accurate phase, and it is difficult to accurately adjust the phase. There was a problem. Therefore, the present invention eliminates the need for a separate delay element by restoring the data and the clock of the receiver from the actual data of the transmitter by detecting the phase after adjusting the voltage controlled oscillator (VCO) to the center frequency using an external crystal oscillator. Make the circuit easier and simpler.

Description

Piel for Clock / Data Recovery Using Multiphase Clock

1 is a circuit diagram of a PLL for clock / data recovery using a multi-phase clock.

2 is a circuit diagram of a PEL for clock / data recovery using the multiphase clock of the present invention.

3 is a detailed circuit diagram of a phase frequency detector in FIG. 2;

4 is a detailed circuit diagram of the first charge pump in FIG.

5 is a circuit diagram of a voltage controlled oscillator in FIG.

6 is a detailed circuit diagram of a voltage controlled oscillator using the replica bias method.

7 is a linear range characteristic diagram of an output frequency with respect to an input voltage when one MOS transistor and two MOS transistors are used in FIG.

8 is a circuit diagram of a lock detector in FIG.

9 is a timing diagram of signals generated in respective units in FIG. 8;

10 is a timing diagram of a multiphase clock and an up signal according to the lock signal in FIG. 8;

11 is a detailed circuit diagram of a phase detector in FIG. 2;

FIG. 12 is a timing diagram of signals input and output to and from each unit in FIG.

13 is a detailed circuit diagram of an edge detector in FIG.

FIG. 14 is a circuit diagram for adjusting the V _P voltage of the voltage controlled oscillator in FIG. 2 after the second loop filter.

* Description of the symbols for the main parts of the drawings *

110: phase frequency detection unit 120: first charge pump

130: first loop filter 140: phase detection unit

150: second charge pump 160: second loop filter

170: voltage controlled oscillator 180: lock detection unit

190: latch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PEL for clock / data recovery using a multiphase clock, and in particular, to adjust the center frequency of a voltage controlled oscillator using an external crystal oscillator, and then to recover the clock and data from the input data using a digital phase detector. PEL for clock / data recovery using multi-phase.

The circuit configuration of PEL for clock / data recovery using a conventional multiphase clock includes: an external crystal oscillator (XTO) for oscillating by returning part or all of the output to an input, as shown in FIG. A clock generator (20) for generating a multiphase clock locked to the external crystal oscillator (XTO); A sampling unit (30) for receiving and sampling a bitstream using a multiphase clock generated from the clock generator (20) and storing the sampled data in a parallax register (40); It consists of a digital PLL 50 that recovers the received data and the clock using the data stored in the parallax register 40. In this case, the frequency of the multiphase clock is the same as that of the enhanced external quartz generator (XTO).

Looking at the conventional technology configured as described above are as follows.

When the clock is generated by the external crystal oscillator XTO, the clock generator 20 delays the multiphase VCD clock locked to the clock of the crystal oscillator XTO and transmits the delayed multiphase VCD clock to the sampling unit 30.

Accordingly, the sampling unit 30 samples the bit stream BIT STREAM input according to the clock delayed from the flip-flop, and transmits the bit stream to the parallax register 40 to store it.

The digital clock 50 restores the clock CLOCK and the data DATA using the data stored in the parallax register 40.

However, in the prior art as described above, in order to match an accurate phase, a plurality of digital PLs must be implemented, and the area of the entire chip becomes large. In addition, since the frequency of the analog clock generator of analog PIEL to make a multiphase clock is always the same as that of an external crystal oscillator (XTO), an additional circuit is needed for a circuit that combines a multiphase clock to make a desired clock in a multiphase clock. There is this.

Accordingly, an object of the present invention to solve the conventional problem is to adjust the voltage controlled oscillator (VCO) to the center frequency using an external crystal oscillator and then detect the phase to phase out the frequency of the voltage controlled oscillator without using digital PLL. The present invention provides a PEL for clock / data recovery using a multi-phase clock to restore the clock and the received data from the transmission data by changing the.

Another object of the present invention is to provide a PEL for clock / data recovery using a multiphase clock to recover accurate data using a multiphase clock without using a half delay cell when restoring data.

In order to achieve the above object, the PLL configuration for clock / data recovery using the multiphase clock according to the present invention receives an input system clock, detects a phase thereof, compares it with an input frequency and outputs an up or down signal accordingly. Phase frequency detection means; A first charge pump converting and outputting an analog signal capable of controlling an oscillator according to the output signal of the phase frequency detecting means; A first loop filter for removing high frequency components by low-passing the output of the first charge pump; Phase detection means for detecting a phase of the input energy data and comparing the phase with the input frequency phase and outputting an up or down signal according thereto; A second charge pump converting and outputting an analog signal for controlling an oscillator according to the output signal of the phase detecting means; A second loop filter for removing high frequency components by low-passing the output of the second charge pump; A voltage controlled oscillator for receiving the output voltages of the first and second loop filters, respectively, generating a multiphase clock and outputting the multiphase clocks to the phase frequency detecting means and the phase detecting means, respectively; Lock detection means for detecting a lock state in accordance with the output signal of the phase frequency detection means and controlling the operation of the phase frequency detection means or the second loop filter in accordance with the detected lock state; Energy data is stored in accordance with the control output of the voltage-controlled oscillator, and the latch is configured to restore the received data and the clock according to the selection signal.

The voltage controlled oscillator may include an associating amplifier configured to set an output level of a delay cell by amplifying an input reference voltage to a predetermined level; Amplifying means and a delay cell for generating a multi-phase clock of a desired frequency using a bias voltage corresponding to the voltage input from the first and second loop filters, the phase detection means is energy according to the clock frequency input from the voltage controlled oscillator Edge detection means for receiving data (NRZ data) and detecting and outputting an edge pulse having a predetermined width; First and second delay means for receiving an edge pulse of the edge detection means and delaying the output by a predetermined period; Down signal generating means for receiving the output signals of the first and second delay means to a reset and set input terminal to generate and output a down (dn) signal; And an up signal generating means for receiving the output signal of the second delay means to the set input terminal and receiving the clock ck0 of the voltage controlled oscillator to the reset input terminal to generate an up signal.

Hereinafter, with reference to the accompanying drawings in detail as follows.

The PEL circuit configuration for clock / data recovery using a multi-phase clock, as shown in FIG. 2, receives an input system clock, detects its phase, and compares it with an input frequency. (dn) a phase frequency detector 110 for outputting a signal; A first charge pump 120 for converting and outputting an analog signal capable of controlling an oscillator according to the output signal of the phase frequency detector 110; A first loop filter 130 for removing high frequency components by low-passing the output of the first charge pump 120; A frequency detector 140 which detects a phase of the input energy data and compares it with an input frequency and outputs an up or down dn signal accordingly; A second charge pump 150 for converting and outputting an analog signal for controlling an oscillator according to the output signal of the frequency detector 140; A second loop filter 160 for removing high frequency components by low-passing the output of the second charge pump 150; A voltage controlled oscillator for receiving the output voltages of the first and second loop filters 130 and 160, respectively, generating a multiphase clock, and outputting them to the phase frequency detector 110 and the phase detector 140, respectively. 170); The lock detector 180 detects a lock state according to the output signal of the phase frequency detector 110 and controls an operation of the phase frequency detector 110 or the second loop filter 160 according to the detected lock state. )Wow; A latch 190 is configured to store energy data according to the control output of the voltage controlled oscillator 170 and restore the received data and the clock according to the selection signal sel.

The configuration of the voltage controlled oscillator 170, the phase detector 140, and the lock detector 180 will be described later along with the operation description.

Referring to the operation and effect of the present invention configured as described in detail as follows.

At the beginning of the system, Loop 1 is enabled. Loop 2 is disabled.

Accordingly, the phase frequency detector 110 receives the input system clock (SYS CLX) and outputs an UP signal when the system clock frequency is high compared to the clock frequency input from the voltage controlled oscillator 170 and the voltage controlled oscillator. If the clock frequency of 170 is high, a down (dn) signal is output.

Referring to FIG. 3 for the operation of the phase frequency detector 110, for example, when the frequency f1 input to the phase frequency detector 110 is higher than the clock frequency f2 of the voltage control emitter 170. A high signal is input to the NAND gate ND1 and a low signal is input to the NAND gate ND4, respectively.

At this time, the lock signal is locked because it is not locked.

Accordingly, the high signal of the input frequency f1 is inputted to one side of the NAND gate ND3 through the NAND gate ND1 and ND2, and the low signal of the clock frequency f2 is supplied to the NAND gate (Ndgate). The low signal is input to one side of the NAND gate ND6 through ND4) and ND5.

At this time, the first latch 100a and the second latch 100b continue to latch the high signal and the low signal of the NAND gates ND2 and ND5, and the NAND gate ND11 receiving the latch signals receives the high signal. Output

Then, the NAND gate ND3 outputs a high state up signal through the inverter I1 as a high signal is input, and the NAND gate ND6 outputs a low signal that is an output signal of the second latch and the NAND gate, respectively. It receives the logic combination and outputs the low (dn) signal of the low state through the inverter I2.

Conversely, if the input frequency f1 is lower than the clock frequency f2 of the voltage controlled oscillator 170, the up signal goes low and the down dn signal goes high.

In addition, when the input frequency f1 and the clock frequency f2 of the voltage controlled oscillator 170 have the same phase (0,0), both the up signal and the down (dn) signal become zero, and the voltage controlled oscillator ( 170, and if the two frequency phases are the same, the (1, 1) up and down signals are fed back to the NAND gates ND2 and ND5, respectively. In addition, the inverter outputs an up signal and a down signal dn in a low state through the inverters I1 and I2 and the NAND gate ND3 and ND6.

The above operation is shown in the table below.

In operation as described above, if the loop 1 is locked, and the low lock signal lock is input to the NAND gate ND1 and ND4, the input frequency f1 and the voltage controlled oscillator 170 Disable is performed regardless of the clock frequency f2.

When the up signal and the down signal dn are output as described above, the first charge pump 120 and the lock detector 180 receive and operate the first charge pump 120, respectively. Based on FIG. 4, it is as follows.

When the high state signal is input, the logic is combined by the OR gate OR12 and the NAND gate ND13. When the low state dn signal is input, the high state signal lock is input. The PMOS transistor is logic-combined by the OR gate OR12 and the NAND gate ND13, and the logic-combined low and high signals are input to the gates of the PMOS and NMOS transistors PM2 and NM1, respectively. PM2 and NMOS transistor NM1 are turned on, respectively.

At this time, since the bias voltage is applied to the gates of the PMOS transistor PM1 and the NMOS transistor NM2, the transistor is always turned on.

Accordingly, the voltage Vcc is divided by the PMOS transistors PM1 and PM2 and the NMOS transistors NM1 and NM2, and the divided voltage is output through the final output terminal out.

Similarly, when the up signal in the low state and the down dn signal in the high state are input, the PMOS transistor PM2 is turned off because the OR gate OR12 outputs a high signal. Since the ND13 outputs a high signal, the NMOS transistor NM1 is turned on, so the ground output is applied to the final output terminal out.

When the high up signal and the down dn signal are input, the same as when the high up signal and the low down dn signal are input. Inputting the up signal and the down signal is the same as inputting the up signal in the low state and the down (dn) signal in the high state.

In this case, when the lock signal lok is applied in the locked state, the first charge pump 120 is in a disabled state.

As described above, the phase frequency detection unit 110 and the first charge pump 120 detects the phase frequency and changes the voltage value for controlling the voltage controlled oscillator 170 accordingly and outputs it to the first loop filter 130. The first loop filter 130 passes low pass to remove high pass components.

Here, the reason for removing the high frequency component is to reduce the damping factor since there is a trade off between the noise characteristics and the frequency tracking capability in the circuit design.

The oscillator receives a constant voltage without the high frequency component from the input terminal V _f and oscillates at a frequency synchronized with the system clock as shown in FIG. 5. The oscillating frequency generates 2M multiphase clocks.

Since 2M PLL clocks with different phases must be generated at the same frequency, a multi-phase clock of a desired frequency can be generated using the replica bias method as shown in FIG.

Referring to FIG. 6 for the operation of the voltage controlled oscillator 170, the input reference voltage Vref is amplified to a predetermined level in the operational amplifier A to thereby lower the output swing range of the delay cell. Adjust the voltage.

Then, the delay cell is a bias voltage (R-Bias) according to the voltage (V _f ) (V _P ) input from the first loop filter 130 and the second loop filter 160 according to the lowest voltage of the output swing range. Is adjusted and output to the differential amplifier 170a.

The PMOS transistor PMOS-1 of the differential amplifier 170a has a gate thereof, and a gate of the PMOS transistor PMOS-2 having a diode connected to the bias voltage R-Bias is a PMOS transistor PMOS-1. The multi-phase clock ck8 (ck0) is generated by differentially amplifying by the voltage obtained by being connected to the common drain of (PMOS-2).

The voltage is transmitted to the next stage again and is differentially amplified again to generate a multiphase clock of a desired frequency by repeating an operation such as generating a multiphase clock ck9 (ck1).

Here, the linear range of the output frequency with respect to the voltage controlled oscillator input voltage is defined by using the PMOS transistor (PMOS-2) periodically connected to the diode to the PMOS transistor (PMOS-1) used for the load in the delay cell. Widened as in the figure. In FIG. 7, when only one PMOS-1 transistor is used, the linear range of the output frequency is indicated by a dotted line. When two PMOS transistors are used, the linear range of the output frequency is represented by a solid line. As shown, the linear range is wider when two PMOS transistors are used.

However, it is difficult to achieve the desired output frequency over a wide voltage controlled oscillator input range when only a single stage differential amplifier is used for stability in the feedback path. However, when a PMOS-2 connected to a diode is inserted, The bias current can be sufficiently adjusted even if the current level to be flowed by the PMOS transistor PMOS-1 is controlled even by using a differential amplifier of one stage, so that the desired voltage controlled oscillator ( 170) can be obtained.

After a certain period of time, when the voltage-controlled oscillator 170 is synchronized to the system clock, the lock detector 180 is operated so that loop 1 is turned off, loop 2 is turned on, and the phase is turned on. The frequency detector 110 and the first charge pump 120 are disabled, which will be described with reference to FIG. 8 as follows.

As shown in FIG. 8, the lock detector 180 detects an up / down signal using a multi-phase clock which is delayed by an arbitrary phase from the input frequency, and then the first and second deflip-flops DF1 (DF2). )and; A control signal generator 180a for generating a clock and a reset signal for controlling a counter according to the output signals of the first and second flip-flops DF1 and DF2; A counter 180b that counts a clock generated by the control signal generator 180a and generates a lock signal when the clock is greater than a number input to an input terminal din is configured.

Referring to the operation of the lock detector 180, if the lock is at the input frequency of the system clock as shown in (a) of FIG. 9 in Loop 1, the same as in (d) and (e) of FIG. The up signal and the down signal dn are transmitted to the data input terminal D of the first and second dip-flops DF1 and DF2 of the first charge pump 120 and the lock detector 180. .

Here, the pulse width of the up / down signal is generally less than 1 ns when locked.

At this time, if the clock ck0 as shown in (b) of FIG. 9 of the multiphase clock of the voltage controlled oscillator 170 is exactly in frequency and phase with the input frequency, it is delayed by an arbitrary phase than the clock ck0. The up signal and the down signal dn are detected using a clock ck1 (ckm) as in (c).

That is, the second deflip-flop DF1 receives an up signal input to the input terminal D when the multi-phase clock ck1 of the high state is received by the clock pulse input terminal cp, and the non-inverting and inverting output terminals thereof. The second deflip-flop DF2 also outputs a down (dn) signal to its non-inverting and inverting output terminal Q (QN).

Then, the NAND gate ND16 of the control signal generation unit 180a is the inverted output terminal of the reset signal / rst inverted through the inverter I1 and the first and second deflip-flops DF1 and DF2. NAND combinations of the signals output through the NAND, and a reset signal generated by the NAND combinations are output to the reset terminal of the counter 180b.

If the reset signal input to the reset terminal of the counter 180b is in a high state, the count value thus far is erased. If the reset signal is in a low state, the count operation is continued.

While the NAND gate ND16 is operating, the AND gate AD1 receives and combines the multi-phase clock ckm and the lock signal lock, which are outputs of the counter 180b, as shown in FIG. 9C. The clock combination ck generated by this AND combination is transferred to the clock input terminal of the counter 180b.

Therefore, the counter 180b counts the number of '0' of the clock inputted to the clock input terminal and generates a lock signal when the counter 180b is larger than the number input to the data input terminal din.

The lock signal generated in this way is transmitted to one input side of the AND gate AD1 to mask the multi-phase clock ckm, and to disable the phase frequency detector 110 and the first charge pump 120. Let's do it.

When the up / down signal dn occurs in the middle of the counter 180b counting, the counter 180b is automatically reset by the NAND gate ND16 to count again from the beginning.

The timing chart of the operation so far is as shown in FIG.

The lock signal generated by the lock detector 180 disables loop 1, the voltage controlled oscillator 170 goes to the center frequency, and when the loop 2 is enabled, the phase detector 140 ) Detects a phase from the actual input energy data NRZ data, compares the detected phase with the phase of the clock ck [O: N-1] generated from the voltage controlled oscillator 170 and increases the corresponding phase accordingly. The up) signal and the down (dn) signal are output, which will be described with reference to FIGS. 11 and 12.

FIG. 11 is a configuration diagram of the phase detector 140. As shown therein, an edge detector 140a for detecting an edge of energy data NRZ data input to a clock input from a voltage controlled oscillator; First and second delay units (140b) (140c) receiving the edges detected through the edge detector (140a), respectively, and delaying the edges by a period (T) and one period; A down signal generator 140d for receiving a signal HF (FL) delayed through the first and second delay units 140b and 140c into a reset and set input terminal to generate and output a down (dn) signal; The output signal FL of the second delay unit 140c is set to the set input terminal, and is configured as an up signal generator 140e which receives the clock ck0 of the voltage controlled oscillator as the reset input terminal and generates an up signal.

Referring to the operation of the phase detector 140 configured as described above with reference to FIGS. 11 to 13, when the clock ([O: N-1]) is oscillated from the voltage controlled oscillator 170 to the phase detector 140. The multi-phase clocks ck0 to ck (N-1) input to the clock pulse input terminals of the deflip _- flops DF ₀ to DF _N-1 constituting the edge detection unit 140a, respectively. It outputs in synchronization with the phase of the energy data NRZ data input to the input terminal D. FIG.

For example, the phase of the energy data NRZ data shown in (a) is output in synchronization with the multi-phase synchronization ckm as shown in FIG. 12 (b).

The data Dout0 to Dout (N-1) output from the flip-flop DF ₀ to DF _N-1 is inputted to one side of the AND gate AND ₀ to AND _N-1 , and the other side thereof is the previous one. Inverts the data (Dout _N-1 to AND _N-2 ), receives the input, and outputs the result of the end combination.

The de-flip flops DF ₁₀ to DF _{1 (N-1)} receiving the outputs of the AND gates AND ₀ to AND _N-1 to the data input terminal D have a clock ck ( The phase of data synchronized with (N-1) / 2), CK ((N-1) / 2 + 1), ..., CK ((N-1) / 2-1) is output.

Then, the edge pulse edge01 (0) having the same width as in (c) of FIG. 12 is output.

As a result, the flip-flops DF ₁₀ to DF _{1 (N-1)} are edge pulses having a constant width with respect to the phase of the data input to the data input terminal by the clock pulse input to the clock pulse input terminal. , edge01 (1), ..., edge01 (N-1) are outputted.

The edge pulses generated in this way (edge01 (0), edge01 (1), ..., edge01 (N-1)) are input to the first delay section 140b and the second delay section 140c, respectively, and have a half cycle and one cycle. Is delayed and this delayed signal (HF) FL is output.

In other words, when there is an edge pulse as shown in (c) of FIG. 12, the signal HF delayed only ½ cycle is generated through the first delay unit 140b as shown in (f). The signal FL, which is outputted to the reset input terminal of the unit 140d and delayed by one cycle, is set through the second delay unit 140c as shown in (e) of the down and up signal generators 140d and 140e. Output to the input stage respectively.

Accordingly, the down signal generator 140d generates and outputs the same down signal dn in (h) of FIG. 12 using the signal HF (FL) input to the reset and set input terminals, and outputs the up signal generator. 140e receives the output signal FL of the second delay unit 140c through the set input terminal and receives a predetermined time (θ _e ) from the multiphase clock (ckm) as shown in (d) of FIG. 12 to the reset input terminal thereof. The delayed multi-phase clock ck0 is input to generate and output an up signal as shown in FIG.

When a fast locking time is required, not only the rising edge of the data but also the falling edge may be detected.

When using the phase detector 140 as described above, the reception range of the voltage controlled oscillator 170 is limited to within ± 3% of the frequency of the transmitter.

Therefore, in order to adjust the frequency of the voltage controlled oscillator 170 in a narrow range, the V _P voltage of the voltage controlled oscillator 170 is adjusted by using a circuit as shown in FIG. 14 next to the second loop filter 160. do.

That is, the voltage V _P is adjusted using the output voltage of the second charge pump 150, the lock signal lock, and the reference voltage Vref.

As described above, the loop 1 which detects the phase and the frequency by the phase frequency detector 110 to detect the phase difference of the oscillation output from the voltage controlled oscillator 170 and delivers the system clock to the voltage controlled oscillator 170 as described above. When loop 1) is operated and the voltage controlled oscillator 70 is synchronized with the system clock, the lock detector 180 is operated so that loop 1 is turned off and loop 2 is turned on to actually input energy. The phase is detected from the data and output to the voltage controlled oscillator 170.

When the phase of the system clock and the actual data is adjusted by the voltage controlled oscillator 170, the latch 190 restores the input energy data NRZ data and outputs the received signal sel.

As described in detail above, the present invention makes it easier and simpler when constructing a circuit by eliminating the need for a separate delay device by making a delay using a multiphase clock to adjust a phase and restoring data and a clock according to the phase. It is effective.

Claims (5)

A PEL for clock / data recovery using a multiphase clock comprising frequency detecting means for synchronizing an oscillator with a system clock, and phase detecting means for extracting data and clock signals from an input signal after said frequency detection. Phase frequency detecting means for detecting a phase from a system clock; A first charge pump for outputting an oscillator control signal according to the output signal of the phase frequency detecting means; Phase detection means for detecting a phase of the input data and comparing the phase with an input frequency phase; A second charge pump controlling the oscillator according to the output signal of the phase detection means; An oscillator for generating a multi phase clock and supplying a signal to the phase frequency detecting means and the phase detecting means under the control of the first and second charge pumps; And a lock detection means for detecting a lock state in accordance with an output signal of the phase frequency detection means and controlling the phase frequency detection means. 3. The lock detection means according to claim 2, further comprising: up / down signal detection means for detecting an up / down signal by using a multiphase clock which is delayed by an arbitrary phase from an input frequency; Control signal generating means for generating a clock and reset signal for controlling the counter in accordance with an output signal of said up / down detecting means; And a counter for generating a lock signal when the clock generated by the control signal generating means is greater than the number input through the input terminal. 4. The apparatus of claim 3, wherein the control signal generating means comprises: an inverter for inverting and outputting the reset signal; A NAND gate which receives a NAND combination of an output signal of an up / down detection means and an output signal of the inverter, and outputs the NAND combined reset signal; Regenerates the clock / data using the multiphase clock characterized in that it is inputted and combined with the multiphase clock which is delayed by an arbitrary phase than the input frequency, and the clock signal generated by the AND combination is configured as an AND gate. Dragon Piel. 3. The apparatus of claim 2, wherein the phase detecting means comprises: edge detecting means for receiving energy data (NRZ data) according to a clock frequency input from a voltage controlled oscillator and detecting and outputting an edge pulse having a predetermined width; First and second delay means for receiving an edge pulse of the edge detection means and delaying the output by a predetermined period; Down signal generating means for receiving the output signals of the first and second delay means to a reset and set input terminal to generate and output a down (dn) signal; A multiphase clock, comprising: an up signal generating means for receiving an output signal of the second delay means into a set input terminal and receiving a clock ck0 of a voltage controlled oscillator as a reset input terminal to generate an up signal; PEL for clock / data recovery using.