CN111541447A - Clock data recovery circuit for PAM4 receiver with waveform screening function and PAM4 receiver - Google Patents

Clock data recovery circuit for PAM4 receiver with waveform screening function and PAM4 receiver Download PDF

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CN111541447A
CN111541447A CN202010455938.8A CN202010455938A CN111541447A CN 111541447 A CN111541447 A CN 111541447A CN 202010455938 A CN202010455938 A CN 202010455938A CN 111541447 A CN111541447 A CN 111541447A
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comparator
output
indicating
sample point
circuit
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CN111541447B (en
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吕方旭
赖明澈
庞征斌
齐星云
王强
肖灿文
戴艺
徐佳庆
刘路
孙岩
曹继军
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National University of Defense Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a clock data recovery circuit for a PAM4 receiver with a waveform screening function and a PAM4 receiver, wherein the clock data recovery circuit for the PAM4 receiver comprises a clock data recovery circuit body with a comparator module and a phase discriminator module, and the front end of the phase discriminator module is connected with a waveform screening circuit which is used for selecting symmetrical waveforms in output signals of the comparator module as output in series; the PAM4 receiver includes the aforementioned clock data recovery circuit for a PAM4 receiver. In order to solve the problem that the CDR of the PAM4 receiver deteriorates the jitter performance of a recovery clock while the phase discrimination density is improved, the invention adds the waveform screening circuit, and selects symmetrical jump edges in output signals of three comparators as the input of the phase discriminator through the waveform screening circuit, so that the phase discrimination density is improved while the phase discrimination precision is improved, and the jitter performance of the CDR recovery clock is improved while the loop is ensured to be locked quickly.

Description

Clock data recovery circuit for PAM4 receiver with waveform screening function and PAM4 receiver
Technical Field
The invention belongs to the field of computers and optical communication, and particularly relates to a clock data recovery circuit for a PAM4 receiver with a waveform screening function and a PAM4 receiver, which can be applied to the fields of chip and backboard electric communication and optical communication.
Background
Clock and data recovery Circuits (CDR) are widely used in the fields of computers and optical communications, and their main functions are to extract clock information from input data with amplitude noise and phase noise and then retime the data.
The CDR is located in the receiver and its working principle is as follows: comparing the phase of input data with the phase of a local clock and acquiring phase difference information of the input data and the local clock; secondly, the phase difference information is utilized to control the phase of the local clock in real time, and the phase of the local clock is ensured to be synchronous with the phase of the input data; and thirdly, accurately sampling the input noise data by using a local clock. Because the input data usually contains a certain phase jitter, in order to ensure that the receiver still keeps the synchronization of the local clock and the input data within a certain jitter range, the phase difference information needs to be filtered before controlling the phase of the local clock. As shown in fig. 1, the existing CDR mainly includes a clock control loop composed of a phase detector, a filter, and a clock module, and a data recovery module. In a clock control loop, in order to ensure that a sampling clock can still quickly and accurately track the phase of input data under the condition of large input phase jitter, the phase discrimination density needs to be improved as much as possible.
Different from a receiver of a non-return-to-zero (NRZ) signal, the four-level pulse amplitude modulation (PAM4) receiver can simultaneously phase-detect three paths of decoded input signals, so that the phase-detection density can be improved. As shown in FIG. 2, in a PAM4 receiver including a conventional CDR, an input signal DINAfter passing through three comparators (comparator A-comparator C), the PAM4 signal is converted into three temperature code signals VA～VCThe three temperature code signals VA～VCThe NRZ signals are utilized, and the three signals are utilized for phase error extraction, so that the phase discrimination density can be further improved. However, the output jumping edges of the three comparators have large jitter, so that the phase discrimination precision is reduced. Since their input waveforms contain asymmetric zero-crossing points, as shown in the lower three sets of waveforms in fig. 3. IN fig. 3, Vref _ A, Vref _ B, Vref _ C is the reference level of comparator A, B, C, PAM4_ IP and PAM4_ IN are the P and N terminals of PAM4 input signal, ComA _ OP and ComA _ ON are the P and N terminals of comparator a output, ComB _ OP and ComB _ ON are the P and N terminals of comparator B output, and ComC _ OP and ComC _ ON are the P and N terminals of comparator C output, respectively. The following asymmetric transition edge waveforms in fig. 3 are also asymmetric after passing through the comparator. These asymmetric waveforms directly degrade the phase detection accuracy. The phase detector performs phase detection on the sampling results of the edges and the center of the data, so that whether the jump edge has symmetry directly influences the phase detection result of the phase detector, and finally the jitter performance of a CDR recovery clock is deteriorated.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a clock data recovery circuit for a PAM4 receiver with a waveform screening function and a PAM4 receiver, aiming at solving the problem that the clock jitter performance of the recovery clock is deteriorated while the phase discrimination density of the CDR of the PAM4 receiver is improved, the invention adds the waveform screening circuit, and the waveform screening circuit selects symmetrical jumping edges in the output signals of the three-way comparator as the input of the phase discriminator, so that the phase discrimination precision is improved while the phase discrimination density is improved, and the clock jitter performance of the clock recovery clock is improved while the loop is ensured to be locked quickly.
In order to solve the technical problems, the invention adopts the technical scheme that:
the utility model provides a PAM4 clock data recovery circuit for receiver with wave form screening function, includes the clock data recovery circuit body that has comparator module and phase discriminator module, the front end of phase discriminator module is concatenated and is used for selecting the symmetrical wave form in the comparator module output signal as the wave form screening circuit of output.
Optionally, the comparator module includes a comparator a, a comparator B, and a comparator C, the waveform selection circuit includes a waveform selection logic circuit a for selecting a symmetric waveform in an output signal of the comparator a as an output, a waveform selection logic circuit B for selecting a symmetric waveform in an output signal of the comparator B as an output, and a waveform selection logic circuit C for selecting a symmetric waveform in an output signal of the comparator C as an output, the comparator module is provided with a sampler at a rear end thereof, the sampler includes two data sampling points located behind each of the comparator a, the comparator B, and the comparator C, and a first data sampling point of the two data sampling points is a data sampling point and a second data sampling point of the two data sampling points is an edge sampling point.
Optionally, the waveform screening logic function expression of the waveform screening logic circuit a is:
(B1·C1)·(B2·C2)
in the above formula, B1Indicating that the output of the first data sample point of comparator B is high, C1Indicating that the output of the first data sample point of comparator C is high, B2Indicating that the output of the second data sample point of comparator B is high, C2Indicating that the output of the second data sample point of comparator C is high.
Optionally, the waveform screening logic circuit B selects a logic function expression for a pair of small-amplitude transition edge waveforms as follows:
Figure BDA0002509375710000021
in the above formula, the first and second carbon atoms are,
Figure BDA0002509375710000022
indicating that the output of the first data sample point of comparator A is low, C1Indicating that the output of the first data sample point of comparator C is high,
Figure BDA0002509375710000023
indicating that the output of the second data sample point of comparator A is low, C2The output of the second data sampling point of the comparator C is high level;
the waveform screening logic circuit B screens a logic function expression aiming at a pair of large-amplitude jump edge waveforms as follows:
Figure BDA0002509375710000024
in the above formula, A1Indicating that the output of the first data sample point of comparator A is high, B1Indicating that the output of the first data sample point of comparator B is high, C1Indicating that the output of the first data sample point of comparator C is high, A2Indicating that the output of the second data sample point of comparator A is high, B2Indicating that the output of the second data sample point of comparator B is high, C2Indicating that the output of the second data sample point of comparator C is high,
Figure BDA0002509375710000031
indicating that the output of the first data sample point of comparator a is low,
Figure BDA0002509375710000032
indicating that the output of the first data sample point of comparator B is low,
Figure BDA0002509375710000033
indicating that the output of the first data sample point of comparator C is low,
Figure BDA0002509375710000034
indicating that the output of the second data sample point of comparator a is low,
Figure BDA0002509375710000035
indicating that the output of the second data sample point of comparator B is low,
Figure BDA0002509375710000036
indicating that the output of the second data sample point of comparator C is low.
Optionally, the waveform screening logic function expression of the waveform screening logic circuit C is:
Figure BDA00025093757100000311
in the above formula, the first and second carbon atoms are,
Figure BDA0002509375710000037
indicating that the output of the first data sample point of comparator a is low,
Figure BDA0002509375710000038
indicating that the output of the first data sample point of comparator B is low,
Figure BDA0002509375710000039
indicating that the output of the second data sample point of comparator a is low,
Figure BDA00025093757100000310
indicating that the output of the second data sample point of comparator B is low.
Optionally, the clock data recovery circuit body further includes a voting circuit, a digital filter circuit, a weight coefficient configuration circuit, and a multiphase clock generator, an output end of the phase discriminator module is connected to the voting circuit, the digital filter circuit, and the weight coefficient configuration circuit in sequence, an input end of the multiphase clock generator is connected to the weight coefficient configuration circuit, and an output end of the multiphase clock generator is connected to the sampler.
In addition, the invention also provides a PAM4 receiver, and the PAM4 receiver is provided with the clock data recovery circuit for the PAM4 receiver with the waveform screening function.
Compared with the prior art, the invention has the following advantages: in order to solve the problem that the CDR of the PAM4 receiver deteriorates the jitter performance of a recovery clock while the phase discrimination density is improved, the invention adds the waveform screening circuit, and selects symmetrical jump edges in output signals of three comparators as the input of the phase discriminator through the waveform screening circuit, so that the phase discrimination density is improved while the phase discrimination precision is improved, and the jitter performance of the CDR recovery clock is improved while the loop is ensured to be locked quickly.
Drawings
FIG. 1 is a block diagram of a CDR system of the prior art.
Fig. 2 is a block diagram of a PAM4 receiver architecture incorporating a conventional CDR according to the prior art.
Fig. 3 shows the input waveform of a PAM4 receiver and the output waveforms of three comparators according to the prior art.
Fig. 4 is a block diagram of a clock data recovery circuit for a PAM4 receiver in an embodiment of the present invention.
Fig. 5 shows the transition edges and corresponding sequence numbers of the input waveform of the PAM4 receiver in the prior art.
Fig. 6 is a schematic block diagram of a waveform selection logic circuit a according to an embodiment of the present invention.
Fig. 7 is a schematic block diagram of a waveform selection logic circuit C according to an embodiment of the present invention.
Fig. 8 is a schematic circuit block diagram of a waveform selection logic circuit B for small-amplitude symmetric transition waveforms according to an embodiment of the present invention.
Fig. 9 is a schematic circuit block diagram of a waveform selection logic circuit B for large amplitude symmetric transition waveforms according to an embodiment of the present invention.
FIG. 10 is an eye diagram of the recovered clock after CDR loop locking according to the embodiment of the present invention.
Detailed Description
As shown in fig. 4, the clock data recovery circuit for PAM4 receiver with the waveform filtering function in this embodiment includes a clock data recovery circuit body having a comparator module and a phase detector module, and a waveform filtering circuit for selecting a symmetric waveform in an output signal of the comparator module as an output is connected in series to a front end of the phase detector module. In order to solve the problem that the CDR of the PAM4 receiver deteriorates the jitter performance of a recovery clock while the phase discrimination density is improved, the invention adds the waveform screening circuit, and selects symmetrical jump edges in output signals of three comparators as the input of the phase discriminator through the waveform screening circuit, so that the phase discrimination density is improved while the phase discrimination precision is improved, and the jitter performance of the CDR recovery clock is improved while the loop is ensured to be locked quickly.
As shown in fig. 4, the comparator module includes a comparator a, a comparator B, and a comparator C, the waveform selection circuit includes a waveform selection logic circuit a for selecting a symmetric waveform in an output signal of the comparator a as an output, a waveform selection logic circuit B for selecting a symmetric waveform in an output signal of the comparator B as an output, and a waveform selection logic circuit C for selecting a symmetric waveform in an output signal of the comparator C as an output, the comparator module is provided with a sampler at a rear end thereof, the sampler includes two data sampling points located behind each of the comparator a, the comparator B, and the comparator C, and a first data sampling point of the two data sampling points is a data sampling point and a second data sampling point of the two data sampling points is an edge sampling point.
Fig. 5 shows 12 variations of the input waveform of the prior PAM4 receiver. Analysis shows that the output of the comparator A has 6 kinds of jump waveforms in total, wherein only 1 and 4 are symmetrical zero-crossing waveforms; the output of the comparator B has 8 jump waveforms in total, wherein 3 and 10, 5 and 8 are symmetrical zero-crossing waveforms respectively; the output of comparator C has a total of 6 transition waveforms, of which only 9 and 12 are symmetrical zero-crossing waveforms. In order to reduce the error of the phase detector and improve the resolution of the phase detector, the PAM4 receiver with the waveform filtering function of the present embodiment expects to utilize all symmetric waveforms and simultaneously exclude all asymmetric waveforms with the clock data recovery circuit, so a waveform filtering circuit is designed before the phase detector module.
In the output waveform of comparator A, when the output of comparator A only has symmetrical small-amplitude transition edges, the outputs of comparator B and comparator C at the first and second data sampling points are logic high. Therefore, in this embodiment, the waveform selection logic function expression of the waveform selection logic circuit a is:
(B1·C1)·(B2·C2)
in the above formula, B1Indicating that the output of the first data sample point of comparator B is high, C1Indicating that the output of the first data sample point of comparator C is high, B2Indicating that the output of the second data sample point of comparator B is high, C2Indicating that the output of the second data sample point of comparator C is high.
As shown in fig. 6, the circuit in the figure is composed of a waveform selection circuit and a binary system peak-to-peak detector (BBPD) logic circuit, where a1, B1, and C1 are the first data sampling output results of the comparator A, B, C, a2, B2, and C2 are the second data sampling output results of the comparator A, B, C, and E1 is the edge sampling output result of the comparator a. CK0 and CK90 are respectively two adjacent clock signals of 1/4 rate clock with the phase difference of 90 degrees, and UP and DN are finally output by phase detection. By means of a waveform selection circuit (B)1·C1)·(B2·C2) The smaller amplitude waveform of the symmetrical zero-crossing of the comparator A can be screened out, and finally the waveform is subjected to phase discrimination, so that the phase discrimination precision of the comparator A is improved.
Similarly, when the output of comparator C only contains symmetrical transition edges, the outputs of comparator a and comparator B at the first and second data sampling points are both logic low. Therefore, in the present embodiment, the waveform filtering logic function expression of the waveform filtering logic circuit C is:
Figure BDA0002509375710000051
in the above formula, the first and second carbon atoms are,
Figure BDA0002509375710000052
indicating that the output of the first data sample point of comparator a is low,
Figure BDA0002509375710000053
indicating that the output of the first data sample point of comparator B is low,
Figure BDA0002509375710000054
indicating that the output of the second data sample point of comparator a is low,
Figure BDA0002509375710000055
indicating that the output of the second data sample point of comparator B is low.
As shown in fig. 7, the circuit is composed of a waveform selection circuit and a BBPD logic circuit, where a1, B1, and C1 are the first data sampling output results of the comparator A, B, C, a2, B2, and C2 are the second data sampling output results of the comparator A, B, C, and E1 is the edge sampling output result of the comparator C. CK0 and CK90 are respectively two adjacent clock signals of 1/4 rate clock with the phase difference of 90 degrees, and UP and DN are finally output by phase detection. By means of a waveform-screening circuit, implementing
Figure BDA0002509375710000056
And the logic is to screen out the amplitude waveform of the comparator C with smaller symmetrical zero-crossing, and finally to perform phase discrimination on the waveform, so as to improve the phase discrimination precision of the comparator C.
In this embodiment, the analysis results of the output transition edges of the comparator a, the comparator B, and the comparator C in the comparator module are shown in table 1:
table 1: each comparator outputs the analysis result of the transition edge.
Figure BDA0002509375710000057
In the above table, the path refers to the output paths of the comparator a, the comparator B, and the comparator C, the serial number refers to the serial number of 12 changes of the input waveform of the PAM4 receiver in the prior art, the transition edge refers to the transition edge change of the 12 waveforms, and whether the zero-crossing point exists in the transition edge change indicates whether the zero-crossing point exists in the transition edge change.
Referring to the above table, the output of comparator B has two pairs of waveforms with symmetrical transition edges, one pair being a small amplitude symmetrical transition edge waveform, generated by transition edges No. 5 and No. 8 in table 1. The other pair is a transition edge waveform with a large amplitude, resulting from transition edges # 3 and # 10 in table 1. Therefore, in the present embodiment, the waveform filtering logic function expression of the waveform filtering logic circuit B for a pair of small-amplitude transition edge waveforms is:
Figure BDA0002509375710000061
in the above formula, the first and second carbon atoms are,
Figure BDA0002509375710000062
indicating that the output of the first data sample point of comparator A is low, C1Indicating that the output of the first data sample point of comparator C is high,
Figure BDA0002509375710000063
indicating that the output of the second data sample point of comparator A is low, C2Indicating that the output of the second data sample point of comparator C is high.
Waveform selection logic circuit B is a waveform selection logic circuit for a pair of small-amplitude transition edge waveforms, as shown in fig. 8, and the circuit is composed of a waveform selection circuit and a BBPD logic circuit, where DA1, DB1, and DC1 are first-time data sampling output results of comparator A, B, C, DA2, DB2, and DC2 are second-time data sampling output results of comparator A, B, C, and EB1 is an edge sampling output result of comparator B. CK0 and CK90 are respectively two adjacent clock signals of 1/4 rate clock with the phase difference of 90 degrees, and UP and DN are finally output by phase detection. By means of a waveform-screening circuit, implementing
Figure BDA0002509375710000064
And the logic is to screen out the amplitude waveform of the comparator B with smaller symmetrical zero-crossing, and finally to perform phase discrimination on the waveform, so as to improve the phase discrimination precision of the comparator B. The waveform screening logic circuit B has the following waveform screening logic function expression aiming at a pair of large-amplitude jump edge waveforms:
Figure BDA0002509375710000065
in the above formula, A1Indicating that the output of the first data sample point of comparator A is high, B1Indicating that the output of the first data sample point of comparator B is high, C1Indicating that the output of the first data sample point of comparator C is high, A2Indicating that the output of the second data sample point of comparator A is high, B2Indicating that the output of the second data sample point of comparator B is high, C2Indicating that the output of the second data sample point of comparator C is high,
Figure BDA0002509375710000066
indicating that the output of the first data sample point of comparator a is low,
Figure BDA0002509375710000067
indicating that the output of the first data sample point of comparator B is low,
Figure BDA0002509375710000068
indicating that the output of the first data sample point of comparator C is low,
Figure BDA0002509375710000069
indicating that the output of the second data sample point of comparator a is low,
Figure BDA00025093757100000610
indicating that the output of the second data sample point of comparator B is low,
Figure BDA00025093757100000611
indicating that the output of the second data sample point of comparator C is low. The waveform selection logic circuit B for a pair of large-amplitude transition edge waveforms is shown in fig. 9, and the circuit is composed of a waveform selection circuit and a BBPD logic circuit, where DA1, DB1, and DC1 are the first data sampling output results of the comparator A, B, C, DA2, DB2, and DC2 are the second data sampling output results of the comparator A, B, C, and EB1 is the edge sampling output result of the comparator C. CK0 and CK90 are respectively two adjacent clock signals of 1/4 rate clock with the phase difference of 90 degrees, and UP and DN are finally output by phase detection. By means of a waveform-screening circuit, implementing
Figure BDA0002509375710000071
And the logic is to screen out the waveform with smaller symmetrical zero-crossing of the comparator B, and finally to perform phase discrimination on the waveform, so as to improve the phase discrimination precision of the comparator B.
As shown in fig. 4, the clock data recovery circuit body in this embodiment further includes a voting circuit, a digital filter circuit, a weight coefficient configuration circuit, and a multiphase clock generator, wherein an output end of the phase discriminator module is sequentially connected to the voting circuit, the digital filter circuit, and the weight coefficient configuration circuit, an input end of the multiphase clock generator is connected to the weight coefficient configuration circuit, and an output end of the multiphase clock generator is connected to the sampler. In addition, the embodiment also provides a PAM4 receiver, and the PAM4 receiver is provided with the clock data recovery circuit for the PAM4 receiver with the waveform screening function.
As a specific embodiment, when the transmitting end transmits PAM4 data of 40Gb/s, the PAM4 receiver is transmitted after channel attenuation of 12dB @10 Gb/s. The PAM4 receiver adopts the CDR added with the waveform screening circuit, and the working process of the CDR is as follows: the PAM4 signal is split into three NRZ signals after passing through a comparator, the output waveforms of which are shown in fig. 3. The waveform screening circuit respectively screens 1 and 4 of the 12 input waveforms of the FIG. 5 by using the four circuits of the FIG. 6, the FIG. 7, the FIG. 8 and the FIG. 9; 9. 12; 3. 10; 5. 8, and then detecting the phase difference between the local clock and the input data by using a BBPD phase detector. And finally, a filtering and clock generation control module passed by the clock control loop generates a sampling clock which is synchronous with the phase of the input data. Fig. 10 shows the recovered clock eye diagram of the output after CDR locking. As can be seen from the figure, the peak-to-peak jitter of the locked clock is 6.5 ps. Therefore, in the embodiment, the waveform screening circuit is added in the clock data recovery circuit, so that the phase discrimination precision can be improved while the phase discrimination density is improved, and the jitter performance of the clock recovery circuit for recovering the clock is improved while the loop is ensured to be locked quickly.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims (7)

1. The utility model provides a PAM4 clock data recovery circuit for receiver with wave form screening function, includes the clock data recovery circuit body that has comparator module and phase discriminator module, its characterized in that, the front end of phase discriminator module is concatenated the wave form screening circuit who is arranged in selecting the symmetrical wave form in the comparator module output signal as the output.
2. The clock data recovery circuit for PAM4 receiver with waveform filtering function according to claim 1, wherein the comparator module comprises a comparator A, a comparator B and a comparator C, the waveform filtering circuit comprises a waveform filtering logic circuit A for selecting a symmetric waveform in the output signal of the comparator A as output, a waveform filtering logic circuit B for selecting a symmetric waveform in the output signal of the comparator B as output, and a waveform filtering logic circuit C for selecting a symmetric waveform in the output signal of the comparator C as output, the comparator module is provided at the rear end with a sampler comprising two data sampling points located behind each of the comparator A, the comparator B and the comparator C, and the first data sampling point of the two data sampling points is the data sampling point, The second data sample is an edge sample.
3. The clock data recovery circuit for PAM4 receiver with waveform filtering function according to claim 2, wherein the waveform filtering logic function expression of the waveform filtering logic circuit a is:
(B1·C1)·(B2·C2)
in the above formula, B1Indicating that the output of the first data sample point of comparator B is high, C1Indicating that the output of the first data sample point of comparator C is high, B2Indicating that the output of the second data sample point of comparator B is high, C2Indicating that the output of the second data sample point of comparator C is high.
4. The clock data recovery circuit for PAM4 receiver with waveform filtering function according to claim 2, wherein the waveform filtering logic circuit B filters the waveforms for a pair of small amplitude transition edge waveforms with a logic function expression of:
Figure FDA0002509375700000011
in the above formula, the first and second carbon atoms are,
Figure FDA0002509375700000012
indicating that the output of the first data sample point of comparator A is low, C1Indicating that the output of the first data sample point of comparator C is high,
Figure FDA0002509375700000013
indicating that the output of the second data sample point of comparator A is low, C2The output of the second data sampling point of the comparator C is high level;
the waveform screening logic circuit B screens a logic function expression aiming at a pair of large-amplitude jump edge waveforms as follows:
Figure FDA0002509375700000014
in the above formula, A1Indicating that the output of the first data sample point of comparator A is high, B1Indicating that the output of the first data sample point of comparator B is high, C1Indicating that the output of the first data sample point of comparator C is high, A2Indicating that the output of the second data sample point of comparator A is high, B2Indicating that the output of the second data sample point of comparator B is high, C2Indicating that the output of the second data sample point of comparator C is high,
Figure FDA0002509375700000015
indicating that the output of the first data sample point of comparator a is low,
Figure FDA0002509375700000016
indicating that the output of the first data sample point of comparator B is low,
Figure FDA0002509375700000017
indicating that the output of the first data sample point of comparator C is low,
Figure FDA0002509375700000018
indicating that the output of the second data sample point of comparator a is low,
Figure FDA0002509375700000019
indicating that the output of the second data sample point of comparator B is low,
Figure FDA0002509375700000021
indicating the second data sample point of comparator CThe output is low.
5. The clock data recovery circuit for PAM4 receiver with waveform filtering function according to claim 2, wherein the waveform filtering logic function expression of the waveform filtering logic circuit C is:
Figure FDA0002509375700000022
in the above formula, the first and second carbon atoms are,
Figure FDA0002509375700000023
indicating that the output of the first data sample point of comparator a is low,
Figure FDA0002509375700000024
indicating that the output of the first data sample point of comparator B is low,
Figure FDA0002509375700000025
indicating that the output of the second data sample point of comparator a is low,
Figure FDA0002509375700000026
indicating that the output of the second data sample point of comparator B is low.
6. The clock data recovery circuit for the PAM4 receiver having the waveform filtering function according to claim 2, wherein the clock data recovery circuit body further includes a voting circuit, a digital filter circuit, a weight coefficient configuration circuit, and a multiphase clock generator, an output terminal of the phase discriminator module is connected to the voting circuit, the digital filter circuit, and the weight coefficient configuration circuit in sequence, an input terminal of the multiphase clock generator is connected to the weight coefficient configuration circuit, and an output terminal of the multiphase clock generator is connected to the sampler.
7. A PAM4 receiver, characterized in that, the PAM4 receiver is provided with the clock data recovery circuit for PAM4 receiver with the waveform filtering function of any claim 1-6.
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CN112737570A (en) * 2020-12-15 2021-04-30 中国科学技术大学 PAM4 signal clock data recovery method based on software phase-locked loop
CN113009654A (en) * 2021-03-31 2021-06-22 飞昂创新科技南通有限公司 High-performance optical fiber interconnection system
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CN113644909A (en) * 2021-08-20 2021-11-12 天津大学 Clock and data recovery circuit for PAM4 receiver
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CN113992319A (en) * 2021-10-18 2022-01-28 中国人民解放军国防科技大学 CDR circuit for receiver, Duo-Binary PAM4 receiver and transmission system

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CN112737570A (en) * 2020-12-15 2021-04-30 中国科学技术大学 PAM4 signal clock data recovery method based on software phase-locked loop
CN113009654A (en) * 2021-03-31 2021-06-22 飞昂创新科技南通有限公司 High-performance optical fiber interconnection system
CN113315726A (en) * 2021-07-29 2021-08-27 深圳市迅特通信技术股份有限公司 Phase demodulation circuit and optical module for NRZ burst reception
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CN113824443B (en) * 2021-08-18 2023-06-30 深圳市紫光同创电子有限公司 Clock data recovery circuit
CN113644909A (en) * 2021-08-20 2021-11-12 天津大学 Clock and data recovery circuit for PAM4 receiver
CN113644909B (en) * 2021-08-20 2023-08-29 天津大学 Clock and data recovery circuit for PAM4 receiver
CN113992319A (en) * 2021-10-18 2022-01-28 中国人民解放军国防科技大学 CDR circuit for receiver, Duo-Binary PAM4 receiver and transmission system
CN113992319B (en) * 2021-10-18 2023-10-13 中国人民解放军国防科技大学 CDR circuit for receiver, duo Binary PAM4 receiver and transmission system

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