CN1692597A - Transition detection, validation and memorization circuit - Google Patents
Transition detection, validation and memorization circuit Download PDFInfo
- Publication number
- CN1692597A CN1692597A CNA028189809A CN02818980A CN1692597A CN 1692597 A CN1692597 A CN 1692597A CN A028189809 A CNA028189809 A CN A028189809A CN 02818980 A CN02818980 A CN 02818980A CN 1692597 A CN1692597 A CN 1692597A
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- transition
- data
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/069—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by detecting edges or zero crossings
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position. The third section memorizes the validated transition position and generates a control signal that is used to recover the data. For instance, this control signal can be used in a sample selection/data alignment circuit to select the over sampled signal that is the best suited for subsequent processing.
Description
Cross reference to related application
Be listed in the application of the date submission identical under this paper cross reference: european patent application N with the application
O..., title " Method and circuit for recovering a data signal from a stream ofbinary data (being used for) " from the Method and circuits of binary data stream restore data signal; And european patent application N
O..., title " Sample Selection and Data Alignment circuit (sample is selected and the alignment of data circuit) ".
Technical field
The present invention relates to the serial communication of high speed binary data, be particularly related to a kind of transition detection, affirmation and memory circuit (transition detection, validation and memorization circuit), it produces and represents which signal that flows in the one group of signal that obtains by over-sampling input string row binary data (bit) is the control signal that will save as the best candidate of restore data.
Background technology
In the high speed binary data serial communication between integrated circuit (system), often generation can not be sampled on the predetermined clock signal reliably from the signal that an integrated circuit is transferred to another integrated circuit.In this case, commonly use n phase place of the reference clock signal that produces by the multi-phase clock generator that binary load is sampled according to stream.Then, use marginal detector to determine that in the sampled signal which is will preserve with expression to be used for best candidate with the restore data of reprocessing.These Sampling techniques are widely used in the situation of high-speed asynchronous serial data communication, and wherein, clock signal is not transferred to receiving system.There has been multiple solution at present in this subject matter, and as described in United States Patent (USP) 5577078, the document discloses a kind of marginal detector, and wherein, input data signal is coupled to the delay chain that forms its delayed version.It is right to select adjacent phase to postpone in once a pair of mode, and compares with clock signal, whether drop on the edge (or transition) of determining clock between the data signal edge of selected phase place centering or outside.Under latter instance, to another to repeating this processing to make comparisons.Double in clock frequency under the situation of data frequency, can sample to data at the trailing edge of clock.There are some inconveniences in this marginal detector.At first, be well known that delay line seriously depends on manufacture process (preferably and the ratio between the worst case often be 3).In addition, this circuit has relatively poor noise immunity, and speed is slower, because it need double the clock frequency of data frequency.
Summary of the invention
Therefore, main purpose of the present invention provides a kind of transition detection, affirmation and memory circuit, and this circuit produces the best control signal of representing binary load according to the data in (bit) stream of which signal in one group of oversampled signals of expression.
Another object of the present invention provides a kind of transition detection, affirmation and memory circuit that is applicable to high-speed serial binary data communication.
Another object of the present invention provides a kind of transition detection, affirmation and memory circuit that glitch (glitch) and error detection is had high noise immunity.
Another object of the present invention provide a kind of according to the LSSD Rule Design to obtain transition detection, affirmation and the memory circuit of high measurability.
According to the present invention, a kind of transition detection, affirmation and memory circuit (transition detectionvalidation and memorization has been described, TDVM) circuit, it produces the control signal of the transition position in expression input string row binary data (bit) stream.This control signal can be used for being suitable for most recovering to import data with a signal of reprocessing by selection from a plurality of over-sampling data.Input string row binary data (bit) stream is sampled in over-sampling circuit by multi-phase clock signal.Clock frequency be generally equal to input data frequency or its half.The over-sampling data-signal is put on described TDVM circuit, described TDVM circuit is handled according to six continuous oversampled signals are carried out the required signal specific of twice of three comparison (signal in the middle of all getting rid of) at every turn, on the position of two continuous sampling signals, detect transition, confirm the position of the oversampled signals of detection recently then, and finally store this position as the transition position.At last, it produces selects signal (G), this signal for example can be used for driving sample and select and alignment of data (sampleselection and data alignment, SSDA) circuit, thus make selected oversampled signals approximately be positioned at the central authorities of bit duration (bit duration) promptly from farthest, bit edge.The paired noise of TDVM circuit design is more insensitive, promptly ignores the sample error that produces because of glitch.
The novel characteristics that is considered to feature of the present invention is elaborated in claims.Yet, below reading in conjunction with the drawings to shown in detailed description of preferred embodiment, the present invention itself and other purposes thereof and advantage can become better understood.
Description of drawings
Fig. 1 illustrates the figure of the bit in typical case's 2.5 gigabit/sec serial data streams when transmitting influencing of being shaken.
Fig. 2 is the figure that the basic principle of oversampling technique of the present invention is shown, and wherein uses n=12 phase place, and these phase places are with C
0To C
11Expression, they are that oscillator by Fig. 4 obtains.
The framework of the schematically illustrated multichannel receiver of being made up of a plurality of data recovery circuits of Fig. 3, wherein each data recovery circuit includes transition detection of the present invention, affirmation and memory circuit and local multi-phase clock generator.
Fig. 4 illustrates 6 grades of oscillators of tradition of the required multi-phase clock signal of the proper operation that produces receiver.
Fig. 5 is illustrated in the over-sampling circuit based on LSSD that uses in the data recovery circuit of the present invention.
Fig. 6 a illustrates the basic circuit of forming transition detection/affirmation of the present invention/storage (TDVM) circuit to 6c, and it is the primary element of data recovery circuit, is used for producing the selection signal.
Fig. 7 illustrates combination with reference to the total figure of Fig. 6 a to the transition detection/affirmation/memory circuit of the described basic circuit of 6c.
The sample that Fig. 8 illustrates when being configured to bit of per clock cycle processing is selected and alignment of data (alignment) circuit (SSDA), and another that this circuit is a data recovery circuit must element.
Fig. 9 illustrates the sample selection of the Fig. 8 when being configured to two bits of per clock cycle processing and the design variations of alignment of data circuit.
Figure 10 illustrates optional overflow/underflow detection (OD) circuit that can be used for significantly improving the operation of sample selection and alignment of data circuit and therefore improve the overall operation of data recovery circuit.
Figure 11 illustrates the sample of the Fig. 8 when being configured to work with the overflow/underflow testing circuit of Figure 10 and selects and the alignment of data circuit.
Figure 12 illustrates expression with respect to the combination of the underflow/overflow bit (L) of selecting signal (G) and being produced by the overflow/underflow testing circuit of Figure 10, should select the table (when being configured to per clock cycle when handling a bit) of which sampled signal (S).
Embodiment
In traditional DR and ce circuit, use two outs of phase of the reference clock signal that postpones in time, one is used for detecting transition, and another is used for catching the data that are used for reprocessing.Yet, should admit, because possible metastability issues, is insecure by carry out the particular sample signal (or sample) that sampling obtains in data transition (logic state fades to 0 or opposite from 1) for the definite position of locating transition exactly, and this detection is owing to existing glitch and error detection even become more complicated.As a result, along with clock frequency continues sharply to increase, the traditional sampling technology that is realized up to now appears to approach the limit.
Fig. 2 is the example of typical data bit stream, supposes that clock frequency is half (frequency of multi-phase clock be generally equal to the frequency of input data signal or its half) of input data frequency.Can be clear from the top of Fig. 2, data fade to 1 (first transition) from 0 and get back to 0 (second transition) from 1 then, are to equal 0 second bit thereby equal after 1 first bit.The relative position in the forward position of the clock signal shown in the bottom of arrow and Fig. 2 is relevant.In this example, exist by the multi-phase clock generator produce with C
0To C
11N=12 clock signal of expression, the definite time/position that the data inlet flow is sampled of these clock signals.Because clock is with half hunting of frequency of input data, so clock signal C in this example
0And C
6Be delayed half period, and their phase place is opposite fully.Thereby, in each period T of clock signal, obtain 12 sampled signal S
0-S
11, wherein, S
0-S
5The sampled signal of expression data flow first bit, and S
6-S
11The sampled signal of expression data flow second bit.Note,, for example sent a series of " 1 ", then in this case, between two successive bits, no longer have transition if in the transmission data, do not change, and border but define by term " data edge " therebetween.
The above-mentioned over-sampling that will describe in detail now and signal specific are handled and significantly are different from described conventional art.According to the present invention, the signal specific of transition position, location is handled three comparisons specific one group of sampled signal being carried out based on when sampling at every turn in data flow.Still with reference to Fig. 2, for example, at position (m+2) or later on the position, to (m-2), (m-1), (m+1) and the sampled signal that (m+2) goes up acquisition are S in the position
M-2, S
M-1, S
M+1And S
M+2Carry out three comparisons, to check whether satisfy following rule of writing with mathematical form:
(1)S
m-2＝S
m-1
(2)S
m-1≠S
m+1
(3)S
m+1＝S
m+2
Suppose that these relational expressions (1)-(3) are verified, then this means on position (m) transition has taken place.Therefore, go up the transition that takes place at position (m) and will in position (m+2) or later position, obtain identification.Thereby, for detecting transition, need be based on twice operation (all getting rid of M signal) of three comparisons that relate to six oversampled signals at every turn.As a result, said method is judged based on " experience (posteriori) ".
It is noted that according to the present invention any transition is all with detected twice, this is because there are two oversampled signals all will satisfy rule (1)-(3).Can be clear from Fig. 4, position (m-1) also mates above-mentioned transition testing conditions as co-located (m).This means that transition is centered at oversampled signals S
M-1Or S
mPosition or position therebetween.The method according to this invention will only consider that second transition detects because it rearwards circuit extra delay is provided.
Therefore, according to the present invention, for the reliable process of avoiding to detect because of this double transition the mistake that causes, when on position (m), detecting transition, if before on position (m-1), detected transition, then this position (m-1) with invalid, and transition is considered to be on the position (m).Note,, will not use sampled signal S according to the present invention
m, because it is not considered to enough reliable.Exist in this object lesson of six samplings at every bit, the sampled signal on position (m+3) is because approximate central authorities that are positioned at bit duration but preferred, and it provides the Maximum tolerance to shake.In being described below, because the sampled signal on the position (m+3) is S
M+3Represent bit value reliably, will use this sampled signal (though position (m+1) and (m+2) on sampled signal also be enough).More generally, if detect transition on position (m), then the sampled signal that will preserve is the signal on the position (m+p), and wherein, p is 2 times (p=n/2xbs) of sample number n divided by the bit number b in the one-period of multi-phase clock signal.In example shown in Figure 2, the sequence of sampled signal is S
10=0, S
11=0, S
0=0, S
1=1, S
2=1, S
3=1, S
4=1 ..., or the like.In clock signal C
0And C
1The forward position detect transition, sampled signal S
1Be considered to represent transition, thereby the sampled signal that will use subsequently is in clock signal C
4The S that obtains of forward position
4Can also see that from Fig. 2 this method is interesting, because its very close sampled signal relatively mutually, compare greatly with the time interval between them but carry out the time that this comparison launches (open).
Fig. 3 illustrates the framework with the 21 multichannel receivers of representing of the present invention, and wherein, 21 pairs of a plurality of input traffics of multichannel receiver are carried out data and recovered to carry out high-speed serial data communication.Referring now to Fig. 3, receiver 21 comprises that at first multi-phase clock produces circuit 22 and with k the data restore circuit of 23-0 to 23-(k-1) expression, wherein each data recovery circuit is respectively applied for a data flow: data input 0 is to data inputs (k-1).
Each DR circuit 23 comprises over-sampling (OS) circuit 24, transition detection/affirmation/storage (TDVM) circuit 25 and sample selection and alignment of data circuit (SSDA) circuit 26.Alternatively, can use overflow/underflow to detect (OD) thus circuit 27 improves SSDA operation improvement DR circuit overall performance.Put on all circuit 24-27 of DR circuit 23 by the multi-phase clock signal of clock generation circuit 22 generations.If consider the DR circuit 23-0 of deal with data input 0 stream, then put on the first input end of TDVM circuit 25-0 and SSDA circuit 26-0 from the sampled signal S of OS circuit 24-0 output, wherein SSDA circuit 26-0 also receives the signal of representing with G that is produced by TDVM circuit 25-0 at second input.Next, SSDA circuit 26-0 produces two signals: recovered clock and restore data are data output 0 in this example.Recovered clock is the predetermined phase of multi-phase clock signal, and restore data fully with it the alignment, thereby allow good restore data with reprocessing.OD circuit 27-0 is connected to the output (it is driven by central corresponding 2 the signal G with bit duration) of TDM circuit 25-0, and the 3rd input of SSDA circuit 26-0.The effect of OD circuit 27 is selective powers of expansion SSDA circuit, and improves the jitter immunity of DR circuit 23 aspect shake, promptly tolerates the more shakes in the input traffic.
For the purpose of the example explanation, consider data recovery circuit 23-0.Serial data stream, data input 0 is in ten two clock signal C of each cycle of multi-phase clock signal by being produced by clock generation circuit 22
0To C
11In OS circuit 24-0, carry out over-sampling.The frequency of multi-phase clock signal owing to stability reasons be generally equal to input data frequency or its half.Sampled signal S input TDVM circuit 25-0 and SSDA circuit 26-0.The TDVM circuit 25-0 of novelty is made up of three parts.The transition detection circuit that first is more insensitive to noise around being designed to especially, promptly ignore the sample error that produces because of glitch makes up.The purpose of second portion is to follow hard on when second of same transition detects to make first transition detection invalid after first transition detects.The effect of third part is to store second position of detecting as the transition position.In itself, TDVM circuit 25-0 determines the transition position in the input traffic, and it eliminates the mistake that possibility produces owing to glitch, and its stores transition position at last.Be used for driving novelty SSDA circuit 26-0 by the signal of TDVM circuit 25-0 output and select sampled signal effectively reliably.SSDA circuit 26-0 can also be with respect to the synchronous selected sampled signal of the predetermined phase of multi-phase clock signal.In the described previous example of reference Fig. 2,, wherein think if on position (m), detect transition, then the sampled signal S on position (m+3) for 6 clock signals of each bit existence of input data
M+3Which point all is the most reliable from, turns back under 0 the situation from 1 then because be raised to 1 at bit signal from 0, and it is in from two extreme edges position farthest and is located substantially on the central authorities of bit duration.Note,, then will use this transition of being stored to determine the sampled signal of each bit central authorities if in input traffic, do not detect transition (for example, a series of " 1 ") subsequently.
The different circuit of forming multichannel receiver 21 are described now in more detail, i.e. clock generation circuit 22 and prevailingly with 23 data restore circuits of representing.
Clock generation circuit (CG) 22
Fig. 4 illustrates the preferred realization that produces (CG) circuit 22 based on the multi-phase clock of ring oscillator, but also can use known for a person skilled in the art a lot of traditional oscillating circuit to produce multi-phase clock signal.Fig. 4 illustrates and is applicable to the 6 grades of ring oscillators of typical case that are created in 12 required in the preferred embodiments of the present invention description phase places well.As shown in Figure 4, ring oscillator comprises that 6 basic differential buffers 28-1 that are cascaded in order to obtain high stability are to 28-6.The multi-phase clock signal that is obtained is with C among Fig. 2
0To C
11Those clock signals of expression.They derive from the Primary reference clock signal that frequency is NMHz (N=1/T), or by phase detectors (PD) circuit from the input extracting data.Notice that buffer 28-1 is controlled by the public PFD/ filter circuit that forms clock recovery unit to the delay of 28-6, wherein, clock recovery unit guarantee the frequency by the multi-phase clock signal of CG circuit 22 generations be substantially equal to the frequency of data flow or its half.As a result, under the situation of multichannel (being communication link), might from individual channel/link, extract clock, and use the recovered clock frequency to recover the data on each channel in other channels by the excute phase adjustment.
Data are recovered (DR) circuit 23
It is made up of some circuit that will describe in detail now.
Over-sampling (OS) circuit 24
OS circuit 24 shown in Figure 5 (24-0 that for example, is used for data input 0 stream) has the high stability of sampled data signal in the whole clock cycle that special structure is guaranteed its output.Because above-mentioned half rate clock, over-sampling circuit 24 is gathered two successive bits of serial data in 12 samples.Any data flow for example data input 0 sampling by the edge sensitive trigger or preferably as shown in Figure 5 principal and subordinate's latch 29-0 finish to 29-11.Principal and subordinate's latch is realized obtaining preferable measurability owing to enable level sensitive scan design (LSSD) but is preferred.For example, consider latch 29-6.The main latch data input pin is connected to data input common wire, and its input end of clock receives C
6Clock signal.When master clock signal turns back to low state (logical zero), catch the data in the data input stream and in the whole clock cycle, keep these data, and irrelevant with the variation that may take place thereon.At this on the one hand, clock signal C
6Guarantee to export highly stable sampled signal S
6, because put on the clock signal C of the input end of clock of subordinate latch
0As mentioned above with clock signal C
6Anti-phase.
Transition detection/affirmation/storage (TDVM) circuit 25
In itself, TDVM circuit 25 of the present invention is made up of three parts or level, and wherein each part is carried out different functions: detect, confirm and storage.
The circuit that forms first is shown in Fig. 6 a, and wherein, it has label 30.The effect of circuit 30 is any transition that detect in the input traffic.For example, suppose that circuit 30 belongs to TDVM circuit 25-0, the transition that then detects in data input 0 stream needs 12 same circuits 30.Fig. 6 a only illustrates a circuit 30 that uses current index i (i fades to 11 from 0), and it is configured to detect corresponding to sampled signal S
iPosition (i) go up the transition that will take place.As the back with reference to shown in Figure 7, as long as index i is faded to 11 complete or collected works that just are enough to obtain basically circuit 30 from 0.Discern the transition on the given position by checking relational expression that preceding two sampled signals and latter two sampled signal provide above whether satisfying when each sampling.If S
I-2=S
I-1, S
I-1≠ S
I+1And S
I+1=S
I+2, then discern transition and be positioned on the position (i).Notice that according to this method, transition will be detected methodically by two continuous circuits 30.There is big advantage in the special structure of circuit 30, because it is insensitive to the glitch that often is identified as transition in the standard edge sense circuit.The promptly very short spurious pulse (parastic pulse) of glitch will never satisfy above-mentioned relation formula (1)-(3).
Still consider Fig. 6 a, circuit 30 is made up of logical circuit 31 and level-sensitive latch 32.Logical circuit 31 by drive two-way (two-way) or (OR) two the piece 33-1 and the 33-2 of door 34 forms, wherein, piece 33-1 and 33-2 by three with (AND) door composition.The sampled signal that puts on piece 33-1 and 33-2 as input is specified in Fig. 6 a.If for the particular value of current index i, three above-mentioned relation formulas all are verified, and then logical circuit 31 produces the output signal D that is in high logic level (for example, " 1 ")
iThe output of logical circuit 31 is connected to the data input pin of level-sensitive latch 32, and clock signal C
I+2Put on its input end of clock and (use clock signal C
I+2Be because it is corresponding to sampled signal S
I+2, wherein this sampled signal is to put on signal nearest in the signal of logical circuit 31).From the signal of level-sensitive latch 32 output with E
iExpression.Therefore, first allows at the sampled signal S that does not consider corresponding to this transition
iSituation under discern transition.Since possible metastability issues, this particular sample signal S
iBe insecure.
Because the special structure of circuit 30 be sure of that any transition is all with detected twice.Now, according to the present invention, only will consider that second detects and to represent transition.For this reason, the second portion that makes up TDVM circuit 25 is only to keep last to avoid any conflict therebetween in twice (or more) continuous detecting.Therefore, the effect of this part is the position of confirming the last detection of same transition.Referring now to Fig. 6 b, this second portion adopts circuit 35 to realize.Put on and (AND) first input end of door 36 from the signal Ei of circuit 30 output.Signal E
I+lNegate in inverter (inverter) 37-1 puts on second input with door 36 then.Alternatively, can also be by inverter 37-2 signal E
I+3Put on and door 36 the 3rd input, eliminate to improve glitch.Put on the data input pin of level-sensitive latch 38 from signal, and its input end of clock is by clock signal C with door 36 output
I+8Drive and (select C
I+8Be because it and C
I+2Anti-phase to improve stability).The signal that is provided by level-sensitive latch 38 is with F
iExpression.Latch signal F
iTherefore expression detects through the transition of confirming, and remains valid in the whole clock cycle.Notice that (Fig. 6 a) can adopt single master/slave latch to making up measurability and the simplicity of design to be improved with 38 (Fig. 6 b) to level-sensitive latch 32, and wherein, their clock signal is anti-phase mutually, promptly is separated by half the clock cycle.For example, suppose that the clock signal that is produced by CG circuit 22 has the frequency that equals 1.25Ghz, and they are 12 phase places, then can discern transition at interval with each 70ps (800ps/12).The signal F of the output of circuit 35
iIn the whole clock cycle is to remain valid in the 800ps, and this will provide the plenty of time to carry out its processing for following circuit.Another advantage is by structure, if two signal E, for example E
I-1And E
iOrder arrives, and then not only preserves E
i, and use it to come reset signal E
I-1, and will adopt clock C later on
I+8Catch it.As a result, the E that has only the position of expression second or last (under the situations about detecting) detection more
iSignal just is identified, and is stored in the level-sensitive latch 38 as signal F with high level
iThis detection below will be called " detection transition ".
The third part of TDVM circuit 25 is stored the position of detecting transition in memory element.Any detection transition is set as high logic state (" 1 ") with memory element.In 3 sampled signals that add deduct any other detects all resets memory elements of transition.Below the obtainable signal of the output of memory element, be called " selection " signal of representing with G, because its optimum sampling signal S in will being used for selecting to gather.The important special feature of memory element is only another selection signal (for example, G is being set
j) just can reset afterwards and select signal (for example, G
I+3).Can expect that the new sampled signal of selecting will always appear on the position of the sampled signal that approaches to select previously, thereby selected at short notice two continuous sampling signals will not problems, because they are away from transition, thereby will have identical value.The exemplary hardware of third part is implemented among Fig. 6 c with circuit 39 expressions (must be clear, circuit 35 and 39 number and circuit 30 are as many).The signal F that provides by circuit 35
iPut on latch 40, it plays the part of the role of above-mentioned memory element.From the selection signal of its output with G
I+3Representing, promptly select the signal of correct sampled signal S according to above-mentioned principle, is S in this example
I+3Signal-G
I+3(by in inverter 41 to signal G
I+3Negate and obtain) ,-G
I+1With-G
I+2Put on and door 42, to produce signal K
iTherefore, K
iBe to be used in TDVM circuit 25, resetting first three signal individual and back three corresponding latchs 40.Signal-F
i, K
I-1And K
I+3Put on and non-(NAND) door 43.Signal and clock signal C from NAND gate 43 outputs
I+2Put on and door 44, to drive the input end of clock of latch 40.Because the special structure of circuit 39 can not allow all select signal G to be in low level simultaneously.Consider the situation of a per clock cycle bit, and supposition G
iBe in high level, if present signal G
I+1Uprise, then it will force G
iEnter low state, thereby after a clock cycle, will have only a signal is G
I+1Be in high state.Differently, under the situation of per clock cycle two bits, will have two to select signal effective simultaneously, and select signal corresponding to each bit for one, the second selection signal can not be owing to producing K
iSignal and reset and first select signal.
Fig. 7 illustrates the actual figure of TDVM circuit 25 interconnect schemes, wherein, TDVM circuit 25 interconnect schemes are made up of 12 same die (slice), wherein each circuit wafer corresponds essentially to integrated (some logic functions combine, and repeat to avoid unnecessary circuit) of basic circuit 30,35 and 39.Therefore, each circuit wafer is corresponding to the detection/affirmation/storage of the transition position of carrying out in set when sampling.Storage signal is the selection signal that is enough to select the optimum sampling signal.Notice that last circuit wafer is connected to first circuit wafer.TDVM circuit 25 has the number selection wire G identical with sampled signal S, and every selection wire G is corresponding to a sampled signal.Low level selection wire is represented to eliminate corresponding sample and the selection wire of high level is represented to preserve sample.In a word, have in the preferred embodiment of two bits in 12 samples, TDVM circuit 25 provides 12 to select signal G, in the middle of them, has two to select for example G of signal
iAnd G
I+6Be in high level, the ordering (rank) of the sampled signal of preserving as the optimum sampling signal in the sampled signal of each bit to indicate is S in this example
iAnd S
I+6These selection wire expections are not changed with input data rate.Under ideal conditions, after through setting, selection wire may not changed.Under the very large condition of noise, the translation activity on the selection wire still is considered to take place with the frequency that is significantly less than input data rate.
Sample selection/alignment of data circuit (SSDA) circuit 26
As described above with reference to Figure 7, select signal G
iIndex corresponding to sampled signal S
iSelect signal G
I+3To select sampled signal S
I+3(if phase two bits weekly) or S
I+6(if phase bit weekly), and more generally, select signal G
iTo select sampled signal S
I+n/2b(wherein, n is the number of phases of reference clock signal, and b is weekly the bit number of phase).SSDA circuit 26 is responsible for selecting enough sampled signals and align it on the predetermined phase of multi-phase clock signal.Fig. 8 schematically shows the preferred realization of the SSDA circuit 26 when to be designed to handle frequency that its speed equals CG circuit 22 be the data bit flow of a per clock cycle bit.Circuit 26 at first is made up of a series of 12 substantially the same logical blocks 45, and wherein each is made up of as shown in Figure 8 two-way multiplexer 46 or door 47 and level-sensitive latch 48.Note, in the first logical block 45-0, do not realize multiplexer 46 and or door 47 because select signal G
0There is not line (it there is no need).As clock phase signal C
0When being in high level, latch 48-0 store sample signal S
0Its output is connected to the first input end of multiplexer 46-1, sampled signal S
1Put on another input.Multiplexer 46-1 by or door 47 by selecting signal G
1Control.The output of multiplexer 46-1 is connected to the input data terminal of latch 48-1, and phase signal C
1Put on its input end of clock.As shown in Figure 8, similarly structure is applied to last logical block 45-11 always, last logical block 45-11 processing signals S
11, C
11And G
11, and the data input of supply latch 49, the input end of clock receive clock phase signal C of latch 49
5Note, in the end among the logical block 45-11, do not realize or door 47-1.Latch 48 and 49 is the level-sensitive type.Can obtain data outputs (restore data) at latch 49 outputs, and C
5Be called recovered clock.In the latch 48 each (for example, 48-1) is connected to its oneself clock phase (for example, C
1).Latch input sample signal (S
0..., S
11) or from the signal of last latch output.Therefore SSDA circuit 26 comprises a row latch and a corresponding row multiplexer substantially, thereby connects logical block 45 with daisy chaining.
Multiplexer is embodied as which sampled signal of control and supplies with and specify latch, and they connect into all sampled signals before the sampled signal of catching current selection in respective latch.After selected sampled signal, selection wire always is in low level.In latch, catch any sampled signal before the selected sampled signal, and ignore any sampled signal after the described sampled signal.Thereby, with the bottom of selected sample synchronous refresh (flush), will be described now this to row.If for example selected sampled signal is S
6, except selecting signal G
6Outside all select signal G
0To G
11All will be in low logic level (corresponding to the transition that on position 0, detects), that is, have only G
6Line is in effective status, promptly is in high logic level (" 1 "), then as corresponding C
6When clock signal was in high logic level, the latch among the logical block 45-5 was caught S
6Sample.Latch output thereby value are selected sample S
6Work as C
7When clock signal entered high logic level, the latch among the logical block 45-6 was caught this S
6Value.Repeat this process and be transferred to the last latch that latch is listed as the bottom, then selected sampled signal is transferred in the output latch 49 up to selected sampled signal.Do not preserve selected sample these samples before, but if sampled signal S is selected in cancellation
iAnd selection sampled signal S
I-1, then catch them and allow SSDA 26 not lose any sampled signal.Output latch 49 guarantees that the sampled signal of representing data is present in its output in the whole clock cycle.
Referring now to Fig. 9, the SSDA circuit is made up of two basic circuit 26-1 and 26-2 now, and it is devoted to the situation that the reference clock signal frequency is half (that is, two bits being arranged in a clock cycle) of input data rate.Last half circuit 26-1 is configured to use the selection signal G relevant with first bit of importing data
1To G
5Handle and clock phase signal C
0-C
5Corresponding six signal S
0-S
5Following half circuit 26-2 is identical with circuit 26-1 in all respects.It uses the selection signal G of second bit
7-G
11Handle six signal S
6-S
11It is noted that in this case, exist two DOL Data Output Line to transmit restore data, thereby following circuit must be configured to alternately obtain bit from these DOL Data Output Line.Equally, exist two clock lines to transmit recovered clock (anti-phase mutually).
Therefore, SSDA 26 circuit adopt bit of 12 sample process in a clock cycle, and SSDA circuit 26-1 and 26-2 adopt bit of six sample process in a clock cycle.Though the Detailed Inspection of SSDA circuit 26,26-1 and 26-2 shown between them have tangible difference, they have still the suitable like configurations based on two foundations.With reference to the SSDA circuit 26 of Figure 10, first is made up of a plurality of logical blocks 45, and second portion is made up of output latch 49.Each logical block 45 comprises multiplexer 46 or door 47 and the latch 48 that connects as mentioned above.At last, will there be selected sampled signal in trigger or master/slave latch to guarantee key characteristic according to the present invention to playing the part of the role of described output latch on DOL Data Output Line in the whole clock cycle.If use single latch, the clock phase signal that then puts on its input end of clock must be anti-phase with the clock phase of the latch that puts on last logical block (for example, being 45-11 under the situation of SSDA 26).
Similarly, data recovery circuit 23-0 can support data to import 0 stream and recovered clock and/or have differing between the high dither (in approaching the frequency range of data rate) of high-amplitude (half bit adds deduct).In order to optimize jitter immunity and to reduce phase error, need above-mentioned clock recovery unit to be designed to (as much as possible) alignment clock phase C
0Transition with the input data.
Overflow/underflow detects (OD) circuit 27
When transmitter and receiver reference clock have certain deviation or shake greatly offset data, will highly need expansion data range of choice.The SSDA circuit 26 of aforesaid DR piece 23 only supports to be limited to the jitter amplitude of 1 bit, and just, it is subject in the one-period of input data and handles sampled signal.TDVM circuit 25 and SSDA circuit 26 all are not designed to support underflow or overflow.Under the situation of a phase bit weekly, from S
0To S
11(at S
0It is underflow that selection before) is moved, and from S
11To S
0(at S
11It is overflow that selection afterwards) is moved.Under the situation of phase two bits weekly, from S
6To S
5Perhaps from S
0To S
11Selection to move be underflow, and from S
5To S
6Perhaps from S
11To S
0Selection to move be overflow.By detecting this overflow/underflow and selecting corresponding sampled signal, jitter toleration might be increased to 1.6 bits in theory.
Figure 10 illustrates and handles the preferred realization that overflow/underflow that its speed equals the data bit flow of clock frequency detects (OD) circuit 27.If there are two bits in input each cycle of data, then need two same circuits.OD circuit 27 detects the moment that TDVM circuit 25 are crossed the index (i) that mid point changes selected G signal.When (for example, G below the mid point crossed in the edge index
6To G
5) time, overflow/underflow bit L equals logical one, thus the expression underflow.When (for example, G more than the mid point crossed in the edge index
5To G
6) time, overflow/underflow bit L equals logical zero, thus the expression overflow.Therefore, it is handled to be positioned at and selects range of signal (G
0-G
11) middle selection signal G
5And G
6
Referring now to Figure 10, with signal G
5And G
6Put on by cross-linked a pair of latch 51 and 52 and a pair of two-way with the door 53 and 54 pieces of forming 50.Clock signal C
8And C
9The input end of clock that puts on latch 51 and 52 respectively (appears at and selects signal G
5And G
6Any stabilisation clock signal afterwards all will be suitable).Provide its input end of clock by clock phase C
9The latch 55 that drives is with overflow/underflow bit L.The data input pin of latch 55 by or door 56 output drive.Or an input of door 56 is connected to and the output of door 53, and another input is connected to and the output of door 57.The output of latch 55 puts on and door 57 first input end by the loop, and another input is connected to or the output of non-(NOR) door 58.NOR gate 58 receives (RESET) signal and by the signal that produces with door 54 of resetting.By signal negate in inverter 59 of latch 55 outputs, to produce above-mentioned overflow/underflow bit L.Therefore the role of OD circuit 27 is the transition that detects in selecting.For example, G
5To G
6Mean L=1, thereby there is overflow in expression, so index must fade to 6 from 5.Note, under the situation of phase two bits weekly, then will need two OD circuit 27-1 and 27-2, respectively processing selecting signal G
2/ G
3And G
8/ G
9
Figure 11 illustrates through revising the SSDA circuit 26 with the Fig. 8 that works with OD circuit 27, and it is with 26 ' expression now.Referring now to Figure 11, for each piece 45, except piece 45-5 and 45-6, the G signal by signal L or signal-L (negate in inverter 61) with door 60 in carry out gating.Which sampled signal S table 1 expression shown in Figure 12 should select with respect to the combination of G signal and underflow/overflow bit L.It should be noted that and can the incident outside the current period be taken in.In period T+1, can use the sampled signal S that in period T, obtains now
0The signal S that replaces generation in period T+1
0
Use SSDA circuit 26-1 and 26-2 (with circuit 27-1 and 27-2 combination) if substitute now, then following table 2 and 3 is suitable for.
Table 2
| ??G 4 | ??G 5 | ??G 0 | ??G 1 | ??G 2 | ??G 3 | ??G 4 | ??G 5 | ??G 0 | ??G 1 | |
| ??0 | ??0 | ??0 | ??0 | ??X | ??X | ??1 | ??1 | ??1 | ??1 | |
| ??S 10 | ??S 11 | ??S 0 | ??S 1 | ??S 2 | ??S 3 | ??S 4 | ??S 5 | ??S 6 | ??S 7 |
X=is random
Table 3 illustrates the situation of second bit.In this case, replace G
2And G
3Use signal G
8And G
9As input.
Table 3
| ??G 10 | ??G 11 | ??G 6 | ??G 7 | ??G 8 | ??G 9 | ??G 10 | ??G 11 | ??G 6 | ??G 7 | |
| ??0 | ??0 | ??0 | ??0 | ??X | ??X | ??1 | ??1 | ??1 | ??1 | |
| ??S 4 | ??S 5 | ??S 6 | ??S 7 | ??S 8 | ??S 9 | ??S 10 | ??S 11 | ??S 0 | ??S 1 |
Therefore, be cost with the simple relatively OS circuit 24 of realizing some sampled signal S of transmission (being 12 in this example), DR piece 23 can be distinguished the data in the 70ps width window reliably, wherein, clock has the cycle that equals T=800ps.A large amount of simulations shows that the DR circuit tolerated that the amplitude maximum can reach the data dithering in 1.5 times of input data clock cycles in 230 minutes well.DR circuit 23 is insensitive to the phase error between recovered clock and any restore data.
Used term " coupling " comprises various types of the connection in this specification and claim, and it can be directly or by one or more intermediate modules.
It will be apparent to those skilled in the art, under the situation that does not break away from the spirit or scope that are defined by the following claims, can be to carrying out various modifications at this exemplary described circuit.
Claims (7)
1. a transition detection, affirmation and memory circuit, be used for detecting the transition of flowing with the input string row binary data (bit) that produce one group of oversampled signals through over-sampling, and producing which sampled signal of expression is the control signal that is used for the optimum sampling signal of reprocessing, and described circuit comprises:
Data input pin is used for receiving one group of oversampled signals (S with binary data (bit) the stream acquisition of specific data speed serial transmission on the high-speed serial communication link
1..., S
N-1), this group signal is n phase place (C by the reference clock signal that is produced by the multi-phase clock signal generator with definite clock cycle
0..., C
N-1) come over-sampling;
N transition checkout gear, be coupled to described multi-phase clock signal generator and described data input pin, and be configured to carry out three more required signal specific processing, on the position of two continuous sampling signals, detect transition according to twice pair of five continuous oversampled signals (signal in the middle of getting rid of);
Confirm for n to be coupled to described multi-phase clock signal generator and described transition checkout gear by device, with the position confirming to detect at the latest as the transition position; And
N storage device is coupled to described multi-phase clock signal generator and described affirmation device, with the position of storing described nearest detection to produce corresponding selection signal (G
0..., G
N-1), wherein having only a selection signal indication is effectively with respect to definite delay of storage transition position, thereby represents which sampled signal is the optimum sampling signal that will keep.
2. circuit as claimed in claim 1, wherein, the described detection of transition position is based in each sampling or three comparisons carrying out later on, for example, if for oversampled signals S
I-1Do not detect transition, to sampled signal S
I-2, S
I-1, S
I+1And S
I+2Three comparisons carrying out:
(1)S
i-2＝S
i-1
(2)S
i-1≠S
i+1
(3) S
I+1=S
I+2Be verified, then this means oversampled signals S
iTransition has taken place, and will be to oversampled signals S
I+1Carry out another time detection.
3. circuit as claimed in claim 2, wherein, described transition checkout gear comprises:
First and door gear, be used for sampled signal S
I-2And S
I-1Carry out and operation, and second and door gear, be used for sampled signal-S
I+1With-S
I+2Carry out and operation, the output of these two devices is connected to the 3rd and door gear;
The 4th and door gear, be used for sampled signal-S
I-2With-S
I-1Carry out and operation, and the 5th and door gear, be used for sampled signal S
I+1And S
I+2Carry out and operation, the output of these two devices is connected to the 6th and door gear;
Or door gear, receive by the described the 3rd and the 6th with the signal of door output; And,
The level-sensitive latch devices is by clock signal phase C
I+2Control is used to store the detection signal E that is detected as the transition on the expression position (i) by data described or that door gear produces
i
4. circuit as claimed in claim 3, wherein, confirm that device comprises:
With door gear, receive the border and select signal E
iWith-E
I+1As input; And
Latch devices is by the clock signal phase C of the output that is connected to described and door gear
I+8Control is confirmed the affirmation signal F of the last transition that detects as the transition position to produce expression
i
5. circuit as claimed in claim 4, wherein, described storage device comprises:
Latch devices has input end of clock and data input pin, is configured to receive described confirmation signal F at its data input pin
iSelect signal G to produce
j, the index of the best oversampled signals of index (j) expression;
With door gear, receive and select signal G
I+p, G
I+1And G
I+2To produce gating signal K
iAnd
With door gear, be used for the clock input of control lock latch device, receive gating signal-F at first input end
iWith K
I-1With K
I+3, and in another input receiving phase clock signal C
I+2
6. circuit as claimed in claim 6, wherein, described index (j) is j=i+p, wherein, p=n/2 * b (b is the bit number of per clock cycle).
7. circuit as claimed in claim 1, wherein, the frequency of multi-phase clock signal equals to import speed or its aliquot of data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP01480101 | 2001-10-26 | ||
| EP01480101.3 | 2001-10-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1692597A true CN1692597A (en) | 2005-11-02 |
| CN100531026C CN100531026C (en) | 2009-08-19 |
Family
ID=8183415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028189809A Expired - Fee Related CN100531026C (en) | 2001-10-26 | 2002-10-10 | Transition detection, validation and memorization circuit |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP1438802B8 (en) |
| JP (1) | JP3813151B2 (en) |
| KR (1) | KR100634193B1 (en) |
| CN (1) | CN100531026C (en) |
| AT (1) | ATE334523T1 (en) |
| DE (1) | DE60213443T2 (en) |
| WO (1) | WO2003036853A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354688B (en) * | 2007-07-27 | 2010-08-25 | 佛山市顺德区顺达电脑厂有限公司 | Apparatus and method for regulating data transmission velocity |
| CN102457261A (en) * | 2010-10-15 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Glitch-free oversampling clock and data recovery |
| CN102510328A (en) * | 2011-12-29 | 2012-06-20 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN101599926B (en) * | 2008-06-04 | 2012-11-21 | 联咏科技股份有限公司 | Differential transmission device and automatic adjustment method for intercepting data thereof |
| CN104683324A (en) * | 2013-11-26 | 2015-06-03 | 希捷科技有限公司 | Indexed I/O symbol communications |
| CN117785014A (en) * | 2023-12-28 | 2024-03-29 | 湖南进芯电子科技有限公司 | High-speed serial data sampling circuit and method |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316391C (en) * | 2003-08-28 | 2007-05-16 | 旺宏电子股份有限公司 | Ultra-sampling document recovering apparatus and method thereof |
| JP4480536B2 (en) * | 2003-12-05 | 2010-06-16 | 株式会社リコー | Data recovery method and data recovery circuit |
| US7085668B2 (en) * | 2004-08-20 | 2006-08-01 | Teradyne, Inc. | Time measurement method using quadrature sine waves |
| US7292665B2 (en) | 2004-12-16 | 2007-11-06 | Genesis Microchip Inc. | Method and apparatus for reception of data over digital transmission link |
| CN100379193C (en) * | 2005-03-02 | 2008-04-02 | 威盛电子股份有限公司 | Method and circuit for acquiring clock for clock data regenerating system |
| JP4676792B2 (en) | 2005-03-17 | 2011-04-27 | 株式会社リコー | Data recovery method, data recovery circuit, data transmission / reception device, and information processing device |
| US7801257B2 (en) * | 2005-09-28 | 2010-09-21 | Genesis Microchip Inc | Adaptive reception techniques for over-sampled receivers |
| US9137008B2 (en) * | 2013-07-23 | 2015-09-15 | Qualcomm Incorporated | Three phase clock recovery delay calibration |
| CN212276404U (en) * | 2019-07-22 | 2021-01-01 | 珠海泰芯半导体有限公司 | Filtering unit, clock data recovery circuit and USB clock data recovery circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821297A (en) * | 1987-11-19 | 1989-04-11 | American Telephone And Telegraph Company, At&T Bell Laboratories | Digital phase locked loop clock recovery scheme |
| US6081561A (en) * | 1994-02-25 | 2000-06-27 | Texas Instruments Incorporated | Method and apparatus for receiving and reconstituting a data signal employing oversampling and selection of a sampled data signal remote from transitions in the data signal |
| US5822386A (en) * | 1995-11-29 | 1998-10-13 | Lucent Technologies Inc. | Phase recovery circuit for high speed and high density applications |
| US6307906B1 (en) * | 1997-10-07 | 2001-10-23 | Applied Micro Circuits Corporation | Clock and data recovery scheme for multi-channel data communications receivers |
| US6285722B1 (en) * | 1997-12-05 | 2001-09-04 | Telcordia Technologies, Inc. | Method and apparatus for variable bit rate clock recovery |
| JP3622685B2 (en) * | 2000-10-19 | 2005-02-23 | セイコーエプソン株式会社 | Sampling clock generation circuit, data transfer control device, and electronic device |
-
2002
- 2002-10-10 WO PCT/EP2002/012189 patent/WO2003036853A1/en active IP Right Grant
- 2002-10-10 DE DE60213443T patent/DE60213443T2/en not_active Expired - Lifetime
- 2002-10-10 JP JP2003539222A patent/JP3813151B2/en not_active Expired - Fee Related
- 2002-10-10 KR KR1020047004512A patent/KR100634193B1/en not_active IP Right Cessation
- 2002-10-10 AT AT02783062T patent/ATE334523T1/en not_active IP Right Cessation
- 2002-10-10 EP EP02783062A patent/EP1438802B8/en not_active Expired - Lifetime
- 2002-10-10 CN CNB028189809A patent/CN100531026C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354688B (en) * | 2007-07-27 | 2010-08-25 | 佛山市顺德区顺达电脑厂有限公司 | Apparatus and method for regulating data transmission velocity |
| CN101599926B (en) * | 2008-06-04 | 2012-11-21 | 联咏科技股份有限公司 | Differential transmission device and automatic adjustment method for intercepting data thereof |
| CN102457261A (en) * | 2010-10-15 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Glitch-free oversampling clock and data recovery |
| CN102457261B (en) * | 2010-10-15 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Glitch-free oversampling clock and data recovery |
| CN102510328A (en) * | 2011-12-29 | 2012-06-20 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN102510328B (en) * | 2011-12-29 | 2014-10-22 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN104683324A (en) * | 2013-11-26 | 2015-06-03 | 希捷科技有限公司 | Indexed I/O symbol communications |
| CN117785014A (en) * | 2023-12-28 | 2024-03-29 | 湖南进芯电子科技有限公司 | High-speed serial data sampling circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| ATE334523T1 (en) | 2006-08-15 |
| JP3813151B2 (en) | 2006-08-23 |
| EP1438802A1 (en) | 2004-07-21 |
| WO2003036853A1 (en) | 2003-05-01 |
| DE60213443T2 (en) | 2007-08-23 |
| KR20040045006A (en) | 2004-05-31 |
| DE60213443D1 (en) | 2006-09-07 |
| EP1438802B8 (en) | 2008-09-24 |
| EP1438802B1 (en) | 2006-07-26 |
| KR100634193B1 (en) | 2006-10-16 |
| JP2005506798A (en) | 2005-03-03 |
| CN100531026C (en) | 2009-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7180966B2 (en) | Transition detection, validation and memorization circuit | |
| CN100571118C (en) | The method and apparatus that is used for clock synchronization | |
| CN100531026C (en) | Transition detection, validation and memorization circuit | |
| CN105830386B (en) | Data sink and for data sink to be realized method in integrated circuits | |
| US8989317B1 (en) | Crossbar switch decoder for vector signaling codes | |
| CN101267204B (en) | Protocol-agnostic automatic rate negotiation for high-speed serial interface in a programmable logic device | |
| CN109450610B (en) | Channel phase alignment circuit and method | |
| JP4309754B2 (en) | Hybrid data recovery system | |
| CN104135413B (en) | A kind of high-speed serial bus sampling system suitable for multiple spot interconnecting application occasion | |
| CN103621005B (en) | The enhanced phase discriminator alignd for fast phase | |
| US6288656B1 (en) | Receive deserializer for regenerating parallel data serially transmitted over multiple channels | |
| US5101203A (en) | Digital data regeneration and deserialization circuits | |
| US7474716B2 (en) | Data recovery circuits using oversampling for maverick edge detection/suppression | |
| CN103401551B (en) | A kind of method of sampling of SerDes technology high speed serial signal and device | |
| US8391433B2 (en) | Flow controlled pulsed serial link | |
| US7054374B1 (en) | Differential simultaneous bi-directional receiver | |
| US20050135518A1 (en) | Improvements to data recovery circuits using oversampling for isi compensation | |
| CN1488947A (en) | Phase tester with improved timing boundary | |
| US20040042504A1 (en) | Aligning data bits in frequency synchronous data channels | |
| CN204206158U (en) | A kind of clock data recovery circuit | |
| US7694264B2 (en) | Pulse link and apparatus for transmitting data and timing information on a single line | |
| US9118536B2 (en) | Pulsed serial link transmitting data and timing information on a single line | |
| US8666006B1 (en) | Systems and methods for high speed data recovery with free running sampling clock | |
| Redman-White et al. | A robust 1.5 Gb/s+ 3Gb/s serial PHY with feed-forward correction clock and data recovery | |
| EP1545047B1 (en) | Improvements to data recovery circuits using oversampling for ISI compensation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090819 Termination date: 20101010 |