WO2006006893A1

WO2006006893A1 - Clock and data recovery circuit

Info

Publication number: WO2006006893A1
Application number: PCT/RU2005/000371
Authority: WO
Inventors: Igor Anatolievich Abrosimov; Alexander Roger Deas; David Coyne
Original assignee: Igor Anatolievich Abrosimov
Priority date: 2004-07-02
Filing date: 2005-07-04
Publication date: 2006-01-19

Abstract

A receiver containing a clock and data recovery circuit operating at a quarter-rate clock frequency is provided for high-speed signalling between integrated circuits. Each integrated circuit comprises a receiver for receiving a first signal from the other integrated circuit. The receiver has a clock and data recovery phase locked loop.

Description

CLOCK AND DATA RECOVERY CIRCUIT

Technical Field

The present invention relates to sampling and re-timing of data in a high speed communications interface between integrated circuits. Specifically the present invention comprises a method and technique for clock and data recovery from a serial data stream.

Background of the Invention A communications receiver typically consists of a number of channels.

Several types of multi-channel communications systems exist today, examples being XAUI where there are 4 unidirectional channels in each direction and PCI- Express where there may be as many as 16 channels in each direction. One difference between these two communications systems is that XAUI is a plesiochronous system and PCI-Express a mesochronous system. In XAUI the clock for retiming the data is typically recovered from the data itself whereas in PCI- Express a clock synchronous to the data is transferred in the communications channel along with the data and said clock used for retiming the data.

Different circuits are used to recover the data in each of these two communications systems. In PCI-Express the reference clock transmitted across the channel multiplied up in a PLL, typically to the same frequency as the data rate, then, in each receiver a delayed version of the clock used to sample the data. Figure 1 shows a typical implementation of such a technique consisting of a PLL 10 and retimer 20. The input to PLL 10 is reference clock REFCLK 2 and the output of PLL 10 is VCO_CLK 61. PLL 10 comprises phase and frequency detector (PFD) 30, charge pump (CP) 40, loop filter (LF) 50, voltage controlled oscillator (VCO) 60 and feedback divider (FBDIV) 70. The operation of the PLL comprising these components as well as the design and analysis of the PLL is well understood to those practiced in the art. The PLL generates a VCO_CLK 61 at the data sampling frequency, generally the same frequency as the data, and a delayed version DLY_CLK 81 is produced in clock delay element 80.

The retimer 20 has as inputs DATA 1 and delay control signal DELCTRL 3 and comprises a clock delay element 80 and sense amplifier and latch 90. The signal DELCTRL 3 controls the delay in clock delay element 80. Various methods exist for the control of the clock delay element and are not discussed here. Clock 81 is delayed to coincide with the optimum sampling point of the data and the data is sampled in sense amplifier 90, producing the retimed data signal DATAOUT 21. It is common practice to produce a buffered version of clock signal 81 and route this to the output as CLK_OUT 22.

For multiple communications channels PLL 10 can be used to provide a clock to a plurality of retimers 20, with one retimer 20 for each data channel.

In a plesiochronous communications system such as that defined in the IEEE 802.3, XAUI standard, no clock synchronous to the data is present. A clock and data recovery (CDR) PLL is typically included in at each channel. Typically the phase detector function embedded in a CDR PLL has the unwanted ability to lock to harmonics and sub-harmonics of the desired clock frequency. Accordingly, it is common practice to implement the CDR PLL architecture with a dual phase detector. In the dual phase detector PLL architecture two phase detectors are used, the first being a standard phase and frequency detector (PFD) while the second is a CDR circuit. A multiplexer is used to select between the outputs of the phase detectors and route signals to a charge pump that controls the VCO frequency. In this method a local reference clock of similar frequency to the received data is used to first lock the PLL to the reference frequency using the standard PFD. The reference frequency must be sufficiently close to the frequency of the received data to ensure that, when control is subsequently switched to the CDR phase detector, the VCO frequency is within the PLL capture range. A frequency lock detector determines when the PLL is locked to the external reference. Once lock is achieved, control of the PLL is switched to the CDR phase detector and the VCO locks to the received data. Figure 2 shows a typical implementation of such a dual phase detector PLL.

Conventional frequency and phase detectors such as the dual D-type flip- flop PFD generate very narrow pulses when locked. Implementing a CDR with a phase detector generating narrow pulses when locked would be difficult at very high data rates as the width of the output pulses to the charge pump would be too small and lead to increased jitter. It would be beneficial for a phase detector used at high data rates and frequencies to generate wider pulses to allow a simpler charge pump design that could result in lower jitter.

An example of a CDR phase detector is given in patent US 4,535,459, Signal Detection Apparatus by C. R. Hogge. Although potentially simple, this CDR operates at the same frequency as the data and performs no deserialisation. Operation of a CDR phase detector at the same frequency as the data rate could incur a significant penalty in power dissipation. It is not uncommon to design integrated circuits in lower cost, mature processes at frequencies that go beyond the region where power and frequency are linearly related. As the operating frequency approaches the limit for the process the power dissipation must be increased disproportionately, often resulting in excessive power dissipation for reliable operation of the integrated circuit. There are significant benefits operating at lower clock frequencies whilst maintaining the higher data rates. For this reason it is not uncommon to operate a CDR with a half-rate clock. It has been shown in patent application PCT/RU05/00250 that significant benefits can be obtained from coding the data in the communications channel resulting in an increased transmission distance, bit error rate reduction or a combination of both increased transmission distance and bit error rate reduction. Patent application PCT/RU05/00250described a method for clock recovery in an over-sampling receiver which used a quarter-rate clock and sampling pairs of data bits. Although the over-sampling technique can result in higher performance, it does have significantly more signal processing requirement, albeit at the lower deserialised clock frequency and can result in higher power dissipation. Further, jitter can result due to the quantisation of the multiple phases of the clock. Applying coded as described in patent application PCT/RU05/00250 to a conventional CDR suing a full-rate or half-rate clocking scheme would result in doubling of the clock frequency and an associated increase in power consumption.

A CDR that could operate with both coded and non-coded data as described in patent application PCT/RU05/00250 could be beneficial to a multi-standard receiver.

Latency, the time from the receipt of the first serial data bit to the output of the first parallel data word is important in many applications, an example being the advanced memory buffer (AMB) standard. In patent application PCT/RU05/00250 the over-sampled data word is processed through several cycles of the deserialised clock resulting in a latency that may be excessive for some applications.

In conventional deserialisers it is common to deserialiser to a parallel data word size twice the symbol size in order to make symbol detection easier. However, again this introduces additional latency. It would be beneficial to deserialiser to a data word size equal to the symbol size. However, the data bits in the data word may not be aligned to the symbol and it may be required to search across data words to align symbols to the deserialiser clock. The minimum latency would be achieved if the bits in the data word aligned to the symbol frame. Thus, it has been shown that it would be highly advantageous in a communications receiver for a clock and data recovery circuit to operate at a sub- multiple of the data rate for lower power dissipation. Further, it is highly advantageous to use coding techniques to obtain improvements in BER, communication distance or increased data rate in a given communications medium and utilise a clock and data recovery circuit that can handle both coded and non- coded data. Further, it has been shown that it would be highly advantageous to allow the deserialised data word to be aligned to the symbol frame and minimise latency.

OBJECT OF THE PRESENT INVENTION

It is a primary object of the present invention to reduce the clock frequency of a VCO in a clock and data recovery circuit to a quarter of the data rate.

It is a further object of the present invention to reduce the power consumption of a clock and data recovery circuit. It is further object of the present invention to reduce the latency associated with the conversion of a serial data stream to parallel data words.

It is another primary objective to increase the communication channel length with coding.

It is another primary objective of the present invention to provide a clock and data recovery circuit for use with coded and non-coded data where the coded data has a minimum run-length greater than one bit.

It is another primary objective to decrease the bit error rate (BER) of a communications system through coding. The method, proposed in this invention, is applicable to all coded data where the minimum run-length of the code is 2 or more bits.

The alternate method, proposed in this invention, is applicable to non-coded data. A particular form of the invention is suitable for memory to processor interfaces, high speed network interfaces and ASIC to ASIC interfaces.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a device and method that uses a quarter- rate clock in a clock and data recovery circuit suitable for use with coded and non- coded data.

Preferably the clock and data recovery unit extracts information from the data to generate control signals that are fed to the charge pump and lock the VCO to the data. Preferably the clock and data recovery unit comprises an input data processor, a transition processor, an output data processor and a clock generator.

Preferably the data input processor includes a means of sampling the data in the middle of each two-bit period.

Preferably, the input data processor comprises a pair of dual edge-triggered flip-flops, wherein the input data processor samples the received data with both edges of quadrature clocks, wherein each dual edge-triggered flip-flop comprises two latches, a multiplexer and an inverter. Preferably the transition processor comprises a plurality of transition detector cells and a charge pump generator, wherein a plurality of transition detector cells detect transitions in the received data for control of the output data processor, wherein a plurality of transition detector cells generate fixed width reference pulses, wherein a plurality of transition detector cells generate variable width pulses where the width of the pulses relative to a fixed width pulse determines the VCO frequency Preferably a transition detector cell comprises a dual edge-triggered flip-flop and an OR gate.

Preferably the charge pump generator comprises a means of gating the fixed width pulses and variable width pulses together to form UP and DN pulses to drive a charge pump.

Preferably the output data processor comprises a means of decoding the two bit-period sampled data from the input data processor though the control signals from the transition processor to generate an output data word of four bits at one quarter the frequency of the received data, wherein the output data processor comprises a plurality of multiplexers for selecting the data from the input data processor or the previously formed output data bit by means of the control signals from the transition processor, wherein the output data processor further comprises a plurality of latches to sequentially store the output of the multiplexers on every rising edge of the quadrature clocks, wherein the output data processor further comprises a plurality of latches to store data, producing a deserialised data word with all bits of the data word aligned to one of the quadrature clock edges.

Preferably the output data processor comprises a buffer with a clock output aligned to the deserialised data word.

Preferably the clock generator produces quadrature clocks at one quarter the data rate of the received data and window conditioning pulses of width equal to one data bit offset by one half a data bit and centred on the edges of the quadrature clocks. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality to the accompanying drawings in which: Fig. 1 shows a block diagram of a PLL and retimer typically used in mesochronous communications systems. Fig. 2 shows a block diagram of a phase locked loop that utilises the clock and data recovery circuit in the current invention.

Fig. 3 shows a block diagram of the clock and data recovery circuit used in the phase locked loop. Fig. 4 shows the timing diagram associated with the clock and data recovery circuit.

Fig. 4a shows the timing diagram associated with the generation of signals for the charge pump in the phase locked loop.

Fig. 5 shows the input data processor of the clock and data recovery circuit. Fig. 5a shows the implementation of a dual edge-triggered flip-flop.

Fig. 6 shows the transition processor of the clock and data recovery circuit.

Fig. 6a shows the implementation of the transition detector circuit.

Fig. 6b shows the implementation of the charge pump generator circuit.

Fig. 6c shows an alternate implementation of the charge pump generator circuit and charge pumps suitable for non-coded data.

Fig. 6d shows the timing diagram associated with the implementation of the alternate charge pump generator circuit.

Fig. 7 shows the output data processor of the clock and data recovery circuit.

Fig. 8 shows the block diagram of the second stage deserialiser and symbol aligner circuit.

Fig. 8a shows the timing diagram associated with the second stage deserialiser and symbol alignment circuit.

Fig. 8b shows the implementation of the hold synchroniser circuit.

Fig. 8c shows the implementation of the hold counter circuit. Fig. 8d shows the implementation of the deserialiser counter.

Fig. 8e shows the implementation of the decoder in the deserialiser counter. DETAILED DESCRIPTION OF THE INVENTION

Figure 2 shows a block diagram of a phase locked loop (PLL) for clock and data recovery and data de-serialisation based on the present invention. The PLL is a dual phase detector type and contains a phase and frequency detector (PFD) 200, a clock and data recovery unit (CDR) 300, a dual 2 to 1 multiplexer (MUX) 400, a charge pump (CP) 500, a loop filter (LF) 600, a voltage controlled oscillator (VCO) 700, a feedback divider (FBDIV) 800 and a deserialiser (DESER) 900. The PLL has as inputs received data signal DATA 101 , reference clock REFCLK 102 that may be at or close to the same frequency as the data, control signal DATLOCK 103 that may be alternatively generated within PFD 200.

On start-up the PLL is configured to lock to REFCLK 102 by setting control signal DATALOCK 103 to the appropriate state. In this mode the PLL behaves as a convention PLL with FBDIV 800 dividing the output of VCO 700 to generate FBCLK 801 which is compared to REFCLK 102 in PFD 200 producing the control signals 201 and 202, typically pulses UP and DN, that are selected by MUX 300 to drive CP 400 and LF 500 forcing VCO 700 to lock to a multiple of REFCLK 102. Once lock between REFCLK 102 and FBCLK 801 is achieved, either by detection within the PLL or through some external means, signal DATALOCK 103 changes state and selects CDR 300 to control the CP 500 and lock VCO 700 to the signal DATA 101. In clock and data recovery mode signal DATA 101 and VCO output 801 , or derivatives of the VCO output, are combined in the CDR 300 to produce control signals 301 and 302, typically UP and DN pulses, that are selected by MUX 400 to drive CP 500 and modify the control voltage on the input to VCO 700. The VCO frequency is then adjusted so as to align the VCO clock edges to the edges of DATA 101.

CDR 300 also performs first-level of de-serialisation of DATA 101 , generating data bus signal 303 and a clock signal 304 aligned to the data bus signal 303. A second stage of de-serialisation occurs in DESER 900, producing a bus RTDATA 106 and associated clock CLKOUT 107.

It is obvious to someone skilled in the art how to design the components of, and, analyse a PLL to lock to a constant reference frequency and that detail is not covered in this invention. The embodiment of the CDR 300 is now described.

Figure 3 shows a block diagram of the preferred embodiment of the clock and data recovery circuit (CDR) 300. CDR 300 comprises of input data processor 320, transition processor 340, output data processor 360 and clock generator 380. Clock generator 380 takes as input clock signals 701 and 702 from VCO 700 and generates quadrature clock signals PHO 381 , nPHO 382, PH90 383 and nPH90 384. The relationship between these clock signals can be clearly seen in the timing diagram of figure 3. Additionally, clock generator 380 generates window signals WIN<0> 385, WIN<1> 386, WIN<2> 387 and WIN<3> 388. The window signals are at the same quarter-rate frequency of the VCO 700 and, preferably, non- overlapping with a 1 :3 mark to space ratio. The four window signals are spaced equally across the quarter-rate period. The timing diagram of figure 3 shows the relationship of the window signals 385, 386, 387 and 388 to the quadrature clock signals 381 , 382, 383 and 384. For each rising edge of quadrature clock signals 381 , 382, 383, 384 there exists a window signal that spans an interval of ±0.5UI either side of the clock edge. It is obvious to someone skilled in the art that methods exist to generate the clocks required in clock generator 380 and as such are not covered in the present invention. Signal DATA 101 is sampled in input data processor 320. Every pair of data bits in DATA 101 are sampled by quadrature clocks PHO 381 and PH90 383 producing signals EVEN2B 321 and ODD2B 322.

The transition processor 340 detects the presence of transitions in DATA 101. The signals TRAN<0> 341 , TRAN<1> 342, TRAN<2> 343 and TRAN<3> 344 indicate the presence of a transition in DATA at the rising edges of clocks PHO 381 , PH90 383, nPHO 382 and nPH90 384 respectively. This information is used in output data processor 360 to generate valid output data from signals EVEN2B 321 and ODD2B 322. Output data processor 360 produces de-serialised data DOUT<0> 303, DOUT<1 > 304, DOUT<2> 305 and DOUT<3> 306. The de- serialised data is aligned to the rising edge of clock PHO 381 and is at one-quarter the rate of DATA 101. Buffered versions of quadrature clocks PHO 381 and PH90 383 are outputs DPHO 307 and DPH90 308 from output data processor 360.

Transition processor 340 also produces signals UP 301 and DN 302 as an indication of the phase error between the quadrature clocks and DATA 101.

Figure 4 shows the timing diagram associated with CDR 300. In the timing diagram of figure 3, it can be seen that three states are associated with EVEN2B 321 and ODD2B 322. The levels are defined as the normal logic levels 0 and 1 or low and high plus a third level of T, indicating the value may be metastable or incorrect due to the presence of a transition in the receive data coinciding with the edge of one of the phases of the clocks PHO 381 or PH90 383. In reality, due to the presence of jitter on the received data, it is well understood that the logic value after sampling in input data processor 320 may well be a logic 0 or 1 state however, the concept of a third value is used to denote the presence of a transition which will be detected in transition processor 340.

Figure 5 shows the preferred embodiment of input data processor 320. The received signal DATA 101 is sampled in the dual edge-triggered flip-flops 323 and

324 by clock phases PHO 381 and PH90 383 producing the output signals EVEN2B

321 and ODD2B 322, corresponding to the edges of PHO 381 and PH90 383 respectively.

The preferred embodiment of dual, edge-triggered flip-flops 323 and 324 shown in figure 5a. Data input D 332 is routed to the output Q 333 whenever the clock CK 331 changes state. The dual edge-triggered flip-flop 323 and 324 may be formed by transparent latches 334 clock inverter 335 and 2-to-1 multiplexer 336.

Latches 334 are transparent such that when the enable input, G, is high the data input, D, propagates to the output of the latch. When one latch is transparent the multiplexer selects the output of the latch that is in hold mode for this reason CK is used to enable one latch, the inverse of CK enables the other latch and CK also connects to the multiplexer selection pin.

Figure 6 shows the preferred embodiment of transition processor 340 and comprises the three main functions of transition detection, UP pulse generation and

DN pulse generation. A bank of transition detector cells 350, detect transitions in

DATA 101. A second bank of transition detector cells 351 , detects transitions in

VCO clock signals PHO 381 , nPHO 382, PH90 383 and nPH90 384. The outputs of the transition detector cells 350 are gated together in charge pump generator 352 producing the signal UP 301. The outputs of transition detector cells 351 are gated together in charge pump generator 352 to produce the signal DN 302. Signals UP

301 and DN 302 connect to the charge pump 500 through multiplexer 400.

Figure 6a shows the preferred embodiment of transition detector cells 350 and 351 and comprises of logic OR gate 353 and a dual edge triggered D-type flip- flop 354. Transition detector cells 350 and 351 have as inputs a clock signal CK 355, an enable signal EN 356 and a reset signal RES 357. A latching circuit is formed by dual edge-triggered D-type 354 and OR gate 353. The latch is enabled when EN 356 is high and reset when RES 357 is high. The latch is set when EN 356 is high and CK 355 transitions from low to high or from high to low. The timing of the EN 356 and RES 357 signals must be staggered to ensure correct operation. A logic high state on output signal TR_DET 358 indicates the presence of a transition on input CK 355 when EN 356 is high and RES 357 is low. Conversely, a logic low state indicates the absence of a transition under the same conditions of EN 356 and RES 357.

Figure 6 shows the connections between the transition detector cells 350 and 351 , charge pump generator 352, and the various timing signals. The four transition detector cells 350 generating TRAN<3:0> have a common CK 353 input, connecting to DATA 101. For each of transition detector cells 350, input EN 354 is connected to one element of bus WIN<3:0>. Each element of the WIN<3:0> bus is connected to the EN input of the transition detector cells 350 generating TRAN<3:0>. The RES input for each transition detector cells 350 are also taken from the WIN<3:0> bus and are selected so as to occur two bit-periods later. That is:

- For transition detector cell 350 that generates TRAN<0> 341 the EN input is WIN<0> 385 and the RES input is WIN<2> 387.

- For transition detector cell 350 that generates TRAN<1> 342 the EN input is WIN<1 > 386 and the RES input is WIN<3> 388.

- For transition detector cell 350 that generates TRAN<2> 343 the EN input is WIN<2> 387 and the RES input is WIN<0> 385.

- For transition detector cell 350 that generates TRAN<3> 344 the EN input is WIN<3> 388 and the RES input is WIN<1> 386.

It should be noted that, ignoring the effects of jitter from DATA 101 , the pulse generated on the elements of bus TRAN<3:0> is nominally 1.5 bit-periods when the data is locked to the VCO. When DATA 101 leads the VCO in phase the width of the pulses in bus TRAN<3:0> increase in width. Conversely, when DATA 101 lags the VCO in phase the width of the pulses in bus TRAN<3:0> decrease in width. Thereto, this information may be used to control the VCO and lock the VCO to the data. Transition detector cells 351 are used to generate fixed width pulses of 1.5 bit-periods. A fixed width reference pulse is generated for every pulse generated and output on bus TRAN<3:0>. Each element in bus TRAN<3:0> is connected to the EN 356 input of one of transition detector cells 351. The CK 355 input of transition detector cells 351 is connected to one phase of the quadrature clock. The RES 357 input of transition detector cells is connected to one element in bus WIN<3:0>. That is:

- For transition detector cell 351 that generates REF<0> 345 the CK input is PH90 383, the EN input is TRAN<0> 341 and the RES input is WIN<3>

388.

- For transition detector cell 351 that generates REF<1 > 346 the CK input is nPHO 382, the EN input is TRAN<1> 342 and the RES input is WIN<0> 385. - For transition detector cell 351 that generates REF<2> 347 the CK input is nPH90 384, the EN input is TRAN<2> 343 and the RES input is WIN<1 > 386.

- For transition detector cell 351 that generates REF<3> 348 the CK input is PHO 381 , the EN input is TRAN<3> 343 and the RES input is WIN<2> 387. A pulse will only be generated on bus REF<3:0> should a transition be detected and a pulse occur on bus TRAN<3:0>. In this manner there is a balance between the pulses on bus TRAN<3:0> and the pulses on bus REF<3:0>. The pulses on bus REF<3:0> are skewed one bit-period with respect to the corresponding pulses on bus TRAN<3:0>. The pulses in bus TRAN<3:0> and REF<3:0> are combined in charge pump generator 352 to produce signals UP 301 and DN 302 respectively. The preferred embodiment of charge pump generator 352 is shown in figure 6b. Gate 401 combines all the elements of bus TRAN<3:0> in a logical OR operation and gate 402 also combines all elements of bus REF<3:0> in a logical OR operation. Gate 401 produces signal UP 301 and gate 402 produces signal DN 302. Signals UP 301 and DN 302 are suitable for driving a conventional charge pump.

Figure 4a shows an example of the timing of the generation of a DN pulse following a TRAN pulse. The shaded areas represent possible edge movement due to jitter on DATA 101. The separation between an UP pulse and the associated DN pulse is 1.0 bit-periods.

It is obvious to someone skilled in the art that other implementations may exist to generate the necessary DN signal 302 to use in a conventional charge pump with the UP signal 301.

It is further obvious to someone skilled in the art that a simpler transition detector cell could be designed to generate the REF pulse using a single-edge- triggered flip-flop for example. However, it is important that for low clock to data skew that the delays in the signal paths are matched and the cells generating the TRAN<3:0> and REF<3:0> signals identical.

The preferred embodiment of transition detector 340 will not generate the correct signal UP 301 and signal DN 302 for CP 500 when used with non-coded data. The gating of the elements of bus TRAN<3:0> in gate 401 elements of bus REF in gate 402 will result in the loss of edge data and may cause problems with the PLL locking to the data. For applications where non-coded data is used, the present invention may be modified to overcome this potential problem.

Figure 6c shows a modification to charge pump generator 352 and figure 6d shows the timing diagram associated with this enhancement. Elements of bus TRAN<3:0> are combined in gates 550 and 551 to produce signals UP_02 540 and UP_13 541 and the elements of bus REF<3:0> are combined in gates 552 and 553 to produce signals DN_02 542 and DNJ 3 543. That is:

- Signal UP_02 540 is produced from the logical OR of TRAN<0> and TRAN<2> in gate 550.

- Signal UP_13 541 is produced from the logical AND of TRAN<1 > and

TRAN<3> in gate 551. - Signal DN_02 540 is produced from the logical AND of REF<0> and

REF<2> in gate 552. - Signal DN_13 543 is produced from the logical AND of REF<1 > and

REF<3> in gate 553. With two pairs of UP and DN signals the CP 500 must be modified and the preferred embodiment in figure 6c shows two charge pumps 560 and 561 connected to the two pairs of UP and DN signals while their outputs are joined and jointly drive the loop filter. The signals UP_02 540 and DN_02 541 drive charge pump 560 while the signals UP_13 542 and DN_13 543 drive charge pump 561. The outputs of charge pumps 560 and 561 are joined together and connect to the loop filter 600. Within this circuit the modified UP and DN signals are do not lose the information in the edges of the signal DATA 101 and clock signal 701 and 702 when some elements are gated together in this fashion. It is obvious to someone skilled in the art that further solutions exist, in particular, it is obvious that four charge pumps could be connected with their outputs joined and separate inputs. Each element in the bus TRAN<3:0> could be connected to the UP input of each charge pump and each element of the REF<3:0> bus could be similarly connected to the corresponding DN input of each charge pump.

Figure 7 shows the output data processor which comprises multiplexers 370 and D-type flip-flops 371 and 372. The signals in bus TRAN<3:0> are used to control the multiplexers 370. When no transition is detected in DATA 101 , the corresponding element of bus TRAN<3:0> is low and selects the present state of signal EVEN2B 321 or ODD2B 322 from the input data processor 320. When a transition is detected in DATA 101 the corresponding element of bus TRAN<3:0> is high and selects the inverse of the previously output data. By means of an example, assume that TRAN<1> is low, then, the data on ODD2B is sampled by flip-flop 370 on the rising edge of nPHO, eventually generating the DOUT<1> signal aligned to the rising edge of PHO. While, if TRAN<1> is high then the inverse of the data bit latched in the previous state by the rising edge of PH90 is sampled and eventually routed to DOUT<1> on the following rising edge of PHO.

Inverters 373 invert clock phases PHO and PH90. The output of inverters 373 form output clocks DPHO 307 and DPH90 and 308 to the deserialiser. The delays of inverters 373 and 374 are nominally matched to the delays of flip-flops 372.

When DATA 101 is not encoded and has a minimum run length equal to one bit, it is noted that the output data processor may not operate correctly with a continuous data stream of alternating ones and zeros. With non-coded data it is a requirement for correct synchronisation that this continuous pattern not occur. However, long runs of alternating ones and zeros will be tolerated as CDR 300 only requires that one data bit be two bit-periods wide to achieve correct decoding of the input data and resolve this limitation. Output data decoder 360 de-serialises the DATA 101 to the same frequency as the quarter-rate clock and to a four bit data word with the introduction of flip-flops 372. That is, the output data appears as a parallel four bit data word aligned, in the preferred embodiment, to the rising edge of the VCO clock PHO 381. It is obvious to someone skilled in the art that de-serialisation to one bit or two bits is possible within the output data processor and may be usefully used in building a second stage deserialiser with an output data word that is not a multiple of four bits.

It is further noted that the input data processor may also be formed in such a way with four single edge-triggered flip-flops with DATA 101 sampled on each edge of the quadrature clocks 381 , 382, 383 and 384. The resulting four-bit output bus would be connected directly to the inputs of the multiplexers 370 in output data processor 340.

The present invention de-serialises the data to a four-bit data word at one quarter of the data rate. However, it may be necessary to de-serialise to μ wider/ data word at a lower frequency in other applications. It is a common practice to de¬ serialise to a double word, for example de-serialise to 20 bits when the symbol is a 10 bit word. Circuits beyond the deserialiser search for symbols embedded in deserialised data to attain symbol lock. This may increase latency and requires handling symbols that may lie across 'the double word boundaries. The present invention includes de-serialiser 900 to further deserialise DOUT<3:0> to 20' and 32 bit words with low latency by performing symbol alignment in the second de¬ serialisation stage. The preferred embodiment of deserialiser 900 is now described. Figure 8 shows the block diagram of deserialiser DESER 900 and comprises LATCH ARRAY 920, HOLD SYNCHRONISER 940, HOLD COUNTER 960, DESERIALISER COUNTER 980 and SYMBOL DETECTOR 1000. DESERIALISER COUNTER 980 is a timing circuit that generates signals MODA, MODB etc in bus 981 aligned to clock DPHO 307. The signals in bus 981 enable latches in LATCH ARRAY 920 to store DOUT<3:0> and build up symbols, producing the retimed data bus RTDATA 106.

In many communications channels unique symbols are introduced into the data to allow bit alignment. Symbol detector 1000 detects symbols in RTDATA 106, across word boundaries and determines the offset of the data with respect to the symbol boundary. An offset value is generated on bus OFFSET 912 and a signal HOLD_COUNT 914 is sent to the other parts of DESER 900 to hold-off the DESERIALISER COUNTER 980 and align the data to the symbol boundary. In this way data from subsequent symbols occurring on RTDATA do not cross word boundaries and latency is reduced. The implementation of SYMBOL DETECTOR 1000 is obvious to someone skilled in the art and not considered in the current invention.

Figure 8a shows the timing associated with the preferred embodiment of HOLD SYNCHRONISER 940, HOLD COUNTER 960 and DESERIALISER COUNTER 980.

Figure 8b shows the preferred embodiment of the HOLD SYNCHRONISER 940. Signal HOLD_COUNT from SYMBOL DETECTOR 1000 may not be aligned to the higher frequency clock DPHO and HOLD SYNCHRONISER 940 generates a pulse aligned to deserialiser clock DPHO 307 of one period width. The preferred embodiment of HOLD SYNCHRONISER 940 comprises three flip-flops 950, 951 and 952. The rising edge of signal HOLD__COUNT 914 sets the output of flip-flop 950. On the next rising edge of deserialiser clock DPHO 307, flip-flop 951^' goes high. The output of flip-flop 952 follows the output of flip-flop 951 on the next rising edge of DPHO 307 and generates a signal 942 to reset flip-flops 950 and 951. Accordingly, a pulse is generated at the output of flip-flop 952 as signal LOADJ3FFSET 941 to control HOLD COUNTER 960. It is obvious to someone skilled in the art that other implementations of the HOLD SYNCHRONISER 940 are possible.

Figure 8c shows the preferred embodiment of HOLD COUNTER 960 which is a serial shift register with parallel load capability. Multiplexers 971 are configured to route OFFSET<8:0> to the inputs of D-type flip-flops 970 when signal LOADJDFFSET 941 is high. When signal LOAD_OFFSET 941 is low multiplexers 971 are configured to connect the outputs of one flip-flop to the input of the next flip- flop forming a serial shift register. The output of the last flip-flop in HOLD COUNTER 960 generates the signal HOLD 961 which is used in DESERIALISER COUNTER 980 to hold the current state of the counter. A logic zero programmed into OFFSET<8:0> at any point disables DESERIALISER COUNTER 980 for one clock period. OFFSET<8:0> is shown as a nine-bit bus in figure 7c as an example of a mechanism that could generate a hold delay of up to nine clock periods. Although it is obvious to someone skilled in the art that other embodiments of HOLD COUNTER 960 may result in minimal gate count it must be recognised that many applications are required to operate at high frequencies where such designs may be difficult or if not impossible to implement.

Figure 8d shows the preferred embodiment of DESERIALISER COUNTER 980 and comprises flip-flops 990, multiplexers 991 , 992, logic gate 993 and decoder 994. Flip-flops 990, multiplexer 992 and logic gate 993 form the basic counter and in conjunction with decoder 994 generates timing signals MODA, MODB etc 981 for latching the DOUT<3:0> from CDR 300 in LATCH ARRAY 920. Signal CODE 104 determines the counter modulus. In the preferred embodiment a logic low on signal CODE 104 will configure the counter with a modulo-5 count while a logic high on signal CODE 104 will configure the counter with a module-8 count.

Multiplexers 991 are configured such that when signal HOLD 961 is low the counter operates normally and when signal HOLD 961 is high the counter holds its present state by looping back the outputs of flip-flops 990 to the inputs of the same flip-flops through multiplexers 991. DECODER 994 combines the outputs for flip- flops 990 and signal CODE 104 to produce signals for latching DOUT<3:0> into the LATCH ARRAY 920. It is obvious to someone skilled in the art the methods to implement the LATCH ARRAY 920 and this is not considered here.

Figure 8e shows the preferred embodiment of DECODER 940 and consists of logic gating of the outputs of flip-flops 990 and signal CODE 104. The preferred implementation shows decoding to produce 20 bit and 32 bit output data words dependant on the state of signal CODE 104. It is obvious to someone skilled in the art how to implement logic for other code word widths.

Claims

WE CLAIM:

1. A multi-channel communications receiver comprising:

- a sampling system which samples data with quadrature clocks at one quarter the data rate;

- a voltage controlled oscillator (VCO) generating clocks and windowing signals for sampling pairs of data bits;

- a second stage deserialiser generating a parallel data word; and a clock and data recovery circuit for extracting information from the data to generate control signals for locking the VCO to the data, wherein the clock and data recovery circuit operates at a sub-multiple of the data rate.

2. A receiver according to claim 1 , wherein the clock and data recovery circuit operates at a quarter of the data rate.

3. A receiver according to claim 1 or 2, wherein the clock and data recovery circuit comprises an input data processor, a transition processor, an output data processor and a clock generator.

4. A receiver according to claim 3, wherein the input data processor samples the received data on both edges of quadrature clocks operating at one quarter the frequency of the data.

5. A receiver according to claim 3, wherein the input data processor comprises a means of sampling the received data in the middle of each two-bit period.

6. A receiver according to claim 3, wherein the input data processor comprises a pair of dual edge-triggered flip-flops.

7. A receiver according to claim 6, wherein the dual edge-triggered flip-flop comprises two latches, multiplexer and inverter.

8. A receiver according to claim 3, wherein the transition processor comprises a first set of transition detector cells generating variable width pulses for the charge pump, one pulse generated for every transition in the received data; a second set of transition detector cells generating fixed width pulses of the charge pump, one pulse generated for every pulse generated in the first set of transition detector cells; a charge pump generator for generating the signals for the charge pump based on the outputs of the first and second set of transition detector cells.

9. A receiver according to claim 8, wherein the transition detector cell from the first set of transition detector cells has a clock input connected to the received data, wherein the output responds to a transition of either polarity from the signal on the clock input.

10. A receiver according to claim 8 or 9, wherein the transition detector cell from the first set of transition detector cells has an enable input wherein the enable signal is one bit period wide and centred on the rising edge of one of the quadrature clock phases.

11. A receiver according to any one of claims 8-10, wherein the transition detector cell from the first set of transition detector cells has a reset input in addition to the enable input, wherein the reset signal is locked to the enable signal producing an output pulse width nominally one and one-half bit periods wide when the VCO is locked to the data.

12. A receiver according to claim 8, wherein the transition detector cell from the second set of transition detector cells has a clock input connected to one of the quadrature clock signals, wherein the output responds to a transition of either polarity from the signal on the clock input.

13.A receiver according to any one of claims 8 to 12, wherein the transition detector cell from the second set of transition detector cells has enable signal which is one of the signals from the first set of transition detector cells.

14. A receiver according to any one of claims 8, 12 or 13, wherein the transition detector cell from the second set of transition detector cells has a reset input in addition to the enable input, wherein the reset signal is locked to the enable signal producing an output pulse width one and one- half bit periods wide.

15.A receiver according to any one of claims 8 to 15, wherein the transition detector cell comprises a dual edge-triggered flip-flop with reset and logic OR gate.

16.A receiver according to claim 8, wherein the charge pump generator comprises logic gates combining the outputs of the first set of transition detector cells to generate a control signal for the charge pump to increase the VCO frequency.

17. A receiver according to claim 8, wherein the charge pump generator comprises logic gates combining the outputs of the second set of transition detector cells to generate a control signal for the charge pump to decrease the VCO frequency.

18.A receiver according to claim 8, wherein the charge pump generator is adapted for non-coded data and generates a pair of UP signals and a pair of DN signals.

19.A receiver according to claim 18, wherein the charge pump generator comprises logic gates forming the OR of two pairs of signals from the outputs from the first set of transition detector cells to generate the UP signals.

20. A receiver according to claim 18, wherein the charge pump generator comprises logic gates forming the OR of two pairs of signals from the outputs from the second set of transition detector cells to generate the DN signals.

21. A receiver according to claim 3, wherein the output data processor comprises a means of decoding the data from the input data processor under the control of the transitions detected by the transition processor.

22. A receiver according to claims 4 or 21 , wherein the output data processor comprises a plurality of multiplexers and latches.

23.A receiver according to claim 22, wherein the multiplexers select data from the input data processor or the previously formed output data bit under the control of the output signals from the transition processor.

24.A receiver according to claim 22, wherein the plurality of latches determine the validity of the current two bit-period data sample from the input data processor.

25.A receiver according to claim 4, wherein the output data processor comprises a means to resynchronise the sampled output data, producing a data word with all bits of the data word aligned to one of the quadrature clock edges.

26.A receiver according to claim 1 , wherein the second stage deserialiser comprises a latch array, a hold synchroniser, a hold counter, a deserialiser counter and a symbol detector

27.A receiver according to claim 26, wherein the symbol detector detects the presence of unique symbol characters in the output parallel data output of the deserialiser.

28.A receiver according to claim 26, wherein the symbol detector determines the offset of the symbol relative to the symbol frame timing.

29.A receiver according to claim 26 or 28, wherein the symbol detector further generates a pulse to indicate to the deserialiser to align the received data to the symbol frame, the number of clock periods delay being posted in the offset.

30. A receiver according to claim 26, wherein the hold synchroniser generates a pulse one bit-period wide.

31. A receiver according to claims 26 or 30, wherein the hold counter on receipt of the pulse from the hold synchroniser generates a signal of duration equal to the number of bit-periods of the value posted in the offset.

32.A receiver according to claim 26, wherein the deserialiser counter counts bit-periods over one or several different modulus counts.

33.A receiver according to claim 32, wherein the deserialiser counter holds the count for the duration of the pulse width from the hold counter.

34.A method of high speed communication comprising the steps of: - sampling data with quadrature clocks at one quarter the data rate;

- generating clocks and windowing signals for sampling pairs of data bits;

- deserialising the sampled data to generate a parallel data word; wherein the method further comprises: - extracting information from the data to generate control signals for locking the frequency of the clock generator to the data rate, wherein the clock frequency is reduced to a sub-multiple of the data rate using a receiver of any one of claims 1 to 33.

35.A method of reducing the clock frequency and power consumption of a clock and data recovery circuit using coded data where the minimum run- length of the coded data is greater than one bit, using a receiver according to any one of claims 1 to 17 and 21 to 33.

36.A method of reducing the clock frequency and power consumption of a clock and data recovery circuit using non-coded data using a receiver according to any one of claims 18 to 20.

37.A high speed multi-channel communications system for chip-to-chip communication, wherein each chip comprises a receiver according to any one of claims 1 to 33.

38.A memory to processor interface comprising a receiver according to any one of claims 1 to 33.

39.A high speed network interface comprising a receiver according to any one of claims 1 to 33.

40.An ASIC to ACIS interface comprising a receiver according to any one of claims 1 to 33.