KR20000002424A - Clock restoration circuit of synchronized serial data communication - Google Patents

Abstract

PURPOSE: A clock restoration circuit of synchronized serial data communication is provided to simplify the circuit organization, to reduce the power consumption and to easily apply to a high speed serial data communication. CONSTITUTION: A clock restoration circuit comprises: a first divider(52) to divide a standard clock to 1/n during be rested at '0' of a logic value of filtered and deglitched input data and having '1' of logic value and to output(Q1) the first reserve restoration clock; an inverter(53) to turn over the filtered and deglitched input data; a second divider(54) to output(Q2) the second reserve restoration clock; and an OR circuit(55) to output the receptive clock finally restored.

Description

Clock recovery method and clock recovery circuit in synchronous serial data communication system

The present invention relates to a method and circuitry for recovering a receiver clock in a synchronous serial data communication system.

As is known, synchronous serial data communication is one of the communication methods for at least two or more processors exchanging information with each other using one common data communication line.

In the synchronous serial data communication system, data must be transmitted using a clock synchronized with each other. Therefore, both transmitting and receiving sides are supplied with the same data communication clock or a synchronization signal to synchronize their clock phases. Only accurate data communication is secured.

Therefore, in the data receiving apparatus of the synchronous serial data communication system, which is not supplied with a synchronous clock or a synchronous signal, the clock is recovered from the received data and the data is extracted and restored using this clock. Circuits are widely used.

1 is a conventional clock recovery circuit using a PLL circuit, in which a data transition detection unit 11 detects a transition from an input data, that is, a rising edge or a falling edge, and extracts an input clock. The detector 12 compares and detects the phase of the input clock and the output clock fed back from the voltage controlled oscillator 14, outputs data corresponding to the difference in a clock form, and outputs a low pass filter 13 Removes the high frequency component from the output of the phase difference detection unit 12 and converts it into a DC voltage component, and the voltage controlled oscillator 14 adjusts the frequency of the output clock according to the voltage level input from the low pass filter 13. .

That is, in the conventional PLL circuit, when the phase difference detector 12 has a phase difference of 90 degrees between the input clock and the output clock, the frequency of the output clock output from the voltage controlled oscillator 14 is locked. Accurate data reception is achieved by sampling the input data bits at the rising edge of the recovery clock.

However, the conventional clock recovery technique of FIG. 1 is not suitable for high-speed data communication due to this limitation because it is difficult to configure the oscillation frequency of the voltage controlled oscillator to a sufficient enough amount in the actual clock recovery circuit configuration.

2 shows another conventional clock restoring technique, which discloses Korean Patent Publication No. 97-2949 (Clock generation method and circuit thereof) of a digital communication system, and briefly describes its operation.

First, the phase difference detector 21 detects a phase of an input data bit stream using four clocks CK0-CK3 and outputs control signals CTRL.

The loop filter 22 receives a control signal output from the phase difference detecting unit 21 and outputs a phase control signal V _CTL from which high frequency components are removed from the input components.

On the other hand, the clock generator 23 outputs four clocks CK0-CK3 which have the same frequency and each have a phase delay of 90 degrees, and input the same to the phase controller 24.

The phase controller 24 controls the phase delay of the clocks CK0-CK3 from the clock generator 23 in response to the phase control signal input from the loop filter 22 to receive data of the phase delay controlled clock. The circuit is supplied as a synchronous clock and also supplied to the phase difference detecting section 21 so as to detect a phase difference with the input data.

The conventional clock restoration technique of FIG. 2 generates 2n (n is a natural number) clocks having a frequency of 1 / 2n of the maximum transmission rate of input data and having a phase difference of 2π / 2n, respectively. By comparing the phase with the bit string and consequently phase-adjusting (collectively adjusting the phase of the clocks above or below), each clock locks to have a rising edge at the midpoint of the corresponding data bit in turn among the data bits. It is a technology to supply to the synchronous clock used for sampling the input data.

That is, the prior art of FIG. 2 uses a plurality of clocks, and controls the phases of these clocks in a fast (true) or slow (ground) phase delay with respect to the input data bit string to accurately sample the logic level of the data bits. have.

However, the prior art of FIG. 2 has the following problems.

First, a number of reference clocks must be used, and a high phase control technique is required in which each reference clock maintains an equal phase difference.

In addition, a circuit for sampling data must be redundantly provided for each rising edge of each reference clock, and a circuit for multiplexing the result of sampling must be added.

Therefore, the circuit configuration is complicated overall, requires a high degree of phase control (advanced, ground), it is difficult to actually apply to a high-speed data communication system because of the operating characteristics that the response speed of the phase control circuit is slow.

3 shows another conventional clock restoration technique, which is described in Korean Patent Publication No. 95-7325 (Clock Restoration Circuit) and briefly describes its operation.

First, the edge detector 31 detects a rising edge or falling edge of input data by using a preset reference clock therein, and outputs an edge detection pulse. The edge detector 31 generates a reference by the PLL input clock generator 32 according to the edge detection pulse. The clock is divided to generate a PLL input clock.

On the other hand, the phase and frequency detector 33, the low pass filter 34, the voltage controlled oscillator 35, and the divider 36 form a known PLL circuit and output the PLL input from the PLL input clock generator 32. The output pulses fed back from the clock and the voltage controlled oscillator 35 are input, and the output pulses are fixed in a direction in which the phase difference between the two clocks decreases.

However, the prior art of FIG. 3 is limited in the data transmission rate because it uses a high frequency reference clock of 256 times the data transmission rate.

In Fig. 3, for example, a reference clock of 8.192 MHz is used for data communication of 32 Kbps.

The width of the rising or falling edge detection pulse of the data corresponds to one period of the reference clock. During this time, since the frequency divider constituting the PLL input clock generator 32 is reset, 256 times the data communication speed. If the frequency reference clock is divided by 256 during the time when the frequency divider is not reset, it is actually difficult to synchronize with the complete transmission clock.

Moreover, the frequency of the reference clock cannot exceed 20 MHz to 25 MHz in order for the edge detector and the general digital counter circuit to be used in this case stably, so inverting the maximum data rate that can be transmitted from this reference clock frequency is 20 × 10. ^6/256 ≒ 78Kbps to 25 × 10 ^6/256 ≒ 97Kbps degree, enough to handle the data rate of this extent, there is a problem becomes an actually impossible to apply a high-speed data communication over 1Mbps.

In addition to the conventional clock recovery techniques shown in FIGS. 1 to 3 described above, a zero point crossing point of data is detected using a reference clock having a frequency of 256 times the transmission rate of digital data, and at this zero point crossing point A technique for restoring a reception synchronization clock by dividing the reference clock with a period of transmission data while triggering has been proposed (Korean Patent Publication No. 95-22366), but this technique also uses a reference clock as shown in FIG. Since it has a frequency of 256 times, it has the technical limitations of FIG. 3 as well as a problem that the data transmission rate is limited as shown in FIG. 3.

On the other hand, as another conventional clock recovery technique, a data sampler selects a clock phase representing a clock signal, generates a recovered clock in a clock multiplexer based on the selected clock phase, and based on the restored clock signal. A technique for retiming a received data stream has been proposed (Korean Patent Publication No. 97-8903), but this technique also performs loop filtering with a signal that detects a phase difference or a phase difference based on a PLL. Because of the control of the clock multiplexer, it is difficult to sufficiently overcome the problems of the prior art of FIGS. 1 and 2, and it is only partially supplemented as a technique for adding an additional circuit to the PLL circuit.

As a background of the clock recovery technology of the present invention as well as the conventional technology as described above with reference to Figure 4 looks at the signal characteristics of the clock and data in the synchronous serial data transmission technology, and further looks at the problems with the prior art from this.

As shown in Fig. 4, the transmission clock on the transmitting side and the data transmitted according to this clock have a signal transition period (rising edge and falling edge) and stabilization time of valid data, respectively.

That is, the clock, which is generally referred to as a square wave, has a predetermined delay time corresponding to a rising edge (or falling edge), as indicated by ta, and can be interpreted as a substantially trapezoidal waveform.

The serial data (BIT 0 to BIT n) transmitted in synchronization with this transmission clock is transmitted in a serial bit stream in synchronization with one bit during one cycle (T) of the transmission clock, and for each polling edge of the transmission clock. In order to be loaded on the data communication line in turn, a minimum setup time (tb) is required before the data on the communication line is stabilized.

Therefore, as shown in the clock and data timing diagram of FIG. 4, the remaining time (te = tc + td) excluding the setup time tb (where tc is a period from which the data bit starts to stabilize to the rising edge of the clock). td means a period during which the data bit remains stable from the rising edge of the clock.) Since the data bit maintains a stable value during the period (te), the receiving side receives a reception clock so that data can be accessed during this period (te). The rising edge of is matched in te.

That is, even during one period (T) of the transmission clock, te is the time that the data bit maintains a stable value during te except for the setup time (tb). By accessing the data at the rising edge, the correct data value can be recognized. Normally, the rising edge of the reception clock is at the intermediate timing of the data bits.

Therefore, in the present invention as well as the conventional clock recovery techniques, in order to recover the reception clock from the data, to achieve a reception clock having a rising edge in the stable interval of the data bit while having the same frequency as the transmission clock, in particular the conventional techniques Efforts to match the phases of the transmit and reconstructed receive clocks rather than recovering the receive clocks with the rising edges within the stable periods (te) to ensure that data access is possible in the data intervals (te). First of all, additional phases, such as PLL circuits, were required by matching the phases so that the rising edge of the receive clock would enter the stable period of the data bits.

However, as already seen in the signal characteristic of Fig. 4, even though it is practically impossible to recover a reception clock whose phase coincides with the transmission clock only by the reception data, even if the data is unstable in the setup delay time (tb) of the input data, it is impossible to recover the reception clock. Most clock recovery techniques are based on PLL technology to match the phase of the receive clock to that of the transmit clock.

The present invention is directed to a receiver of a synchronous serial data communication system; In recovering the reception clock from the input data, it is not based on the PLL and provides a clock recovery method and a clock recovery circuit that can be applied to a high speed data transmission system as well as a low speed data transmission system with a simple circuit configuration.

The present invention is directed to a receiver of a synchronous serial data communication system; In restoring the reception clock from the input data, the bit stream type input data transmitted from the transmitter has a first logic level and a second logic level, and is reset when the input data is the second logic level. At the same time, the first preliminary recovery clock divided by 1 / n of the reference clock of n times the data transfer rate is output during the first logical level, and is reset when the input data is at the first logical level. Outputs a second preliminary restoration clock obtained by dividing the reference clock by 1 / n during a period of logic level 2, and restores the ORed signal of the first and second preliminary restoration clocks to the final reception clock. Provide a clock recovery method and a clock recovery circuit.

1 is a block diagram of a PLL circuit used for conventional clock recovery.

2 is a block diagram showing an embodiment of a conventional clock recovery circuit.

3 is a block diagram showing another embodiment of a conventional clock recovery circuit.

4 is a waveform diagram illustrating characteristics of data and a clock in a synchronous serial data communication system;

Figure 5 is a block diagram of one embodiment of a clock recovery circuit of the present invention.

6 is a signal waveform diagram for explaining a clock recovery method of the present invention.

Fig. 5 shows an embodiment of a clock recovery circuit of the synchronous serial data communication system of the present invention, and more precisely, a dotted block except for the preprocessor 51 is a clock recovery circuit of the present invention.

The preprocessing unit 51 performs filtering processing such as matching of physical layers of data communication and noise cancellation for input data, and the clock restoring circuit of the present invention; A first divider 52 for dividing the reference clock by 1 / n and outputting the first preliminary restoration clock during a period reset to a logic value '0' of the preprocessed input data and a logic value '1'. And an inverter 53 for inverting the preprocessed input data and a logic of the input data reset and inverted at a logic value '0' (the logic value '1' of the original data) of the input data inverted through the inverter. A second divider 54 for dividing the reference clock by 1 / n and outputting a second preliminary restored clock during a period having a value of '1' (the logical value of the original data '0'); And an OR circuit 55 for ORing the divider and the output Q1 (Q2) of the second divider and outputting the last recovered reception clock.

The reference clock is a frequency n times the transmission clock (n is a positive integer, 4≤n≤16) and is provided by a known oscillator circuit, not shown.

In this case, the inverter 53 uses the first divider 52 and the second divider 54 as a divider circuit having the same configuration in which '0' = reset & '1' = 1 / n division operation. If the second divider 54 is constituted by a divider circuit for performing '1' = reset & '0' = 1 / n division operation, it may be omitted as a matter of course.

In the clock recovery circuit of the present invention configured as described above, generating a clock obtained by dividing a reference clock of n × fi by 1 / n with respect to the frequency fi of the transmission clock during a period of the logic value '0' of the input data; Generating a clock obtained by dividing a reference clock of n × fi by 1 / n with respect to the frequency fi of the transmission clock during the period of the logical value '1' of the data; and performing the logical sum of the generated clocks as a final recovery reception clock. The clock recovery is performed in the step of outputting, and the operation thereof will be described with reference to the circuit of FIG. 5 and the waveform diagram of FIG. 6.

The data output from the preprocessor 51 is input to the first divider 52 and the inverter 53, and the inverter 53 inverts the input data and inputs it to the second divider 54.

The input data comes in synchronization with the transmission clock (period = T, frequency fi = 1 / T). For example, it is assumed that the input data is inputted as a bit string of '1,1,0,1,0,0 ...' The reference clock is n × fi.

The first divider 52 is reset during a period where the input data is '0', and the output thereof becomes '0', and divides the reference clock at 1 / n during the period where the input data is '1'.

Therefore, the first frequency divider 52 has a frequency equal to the transmission clock from the input data is "1" up to the phase difference interval (t _f) is 0≤t _f ≤T / n the first preliminary recovered clock output (Q1 of )

On the other hand, the second divider 54 is reset by the signal '0' inverted by the inverter 53 during the period in which the input data is' 1 ', and the output thereof becomes' 0', and the input data is' The reference clock is divided by 1 / n in the signal '1' section inverted by the inverter 53 during the section that is 0 '.

Therefore, a second frequency divider (54) is a frequency equal to the transmission clock from the input data is '0', up to the phase difference interval (t _f) is 0≤t _f ≤T / n in a second preliminary output recovered clock signals (Q2 of )

The outputs Q1 and Q2 of the first divider 52 and the second divider 54 are input to the OR circuit 55 and are ORed together, and are the same frequency as the transmission clock and have a maximum phase difference t _f . Finally outputs a recovery reception clock of 0 ≦ _{t f} ≦ T / n.

Here, the maximum phase difference t _f is a delay time value for the phase difference between the transmission clock and the reception clock, and the value is maximum and within one period of the reference clock.

Therefore, if the data rate is assumed to be 1 Mbps and the frequency of the reference clock is 16 MHz, which is 16 times the data rate, the first divider 52 and the second divider 54 are implemented using one hexadecimal counter. One period of the data transmission clock is 1,000 nsec (1 / (1 × 10 ⁶ ) = 1,000 nsec), and the stability period (te) of the data bit is about 980 nsec, whereas the rising edge and the transmission of the finally restored reception clock are transmitted. The time deviation t _f of the clock from the rising edge is only 62.5 nsec (1 / (16 × 10 ⁶ ) = 62.5 nsec) at the maximum, and thus the data can be detected very stably.

In addition, the reference clock of about 16 MHz can be provided by an oscillator circuit that is simply and easily configured, so that it can be applied to high-speed data communication of 1 Mbps or more. Since the receive clock can be recovered from the input data, the circuit configuration can be simplified, and a low cost and high efficiency synchronous clock recovery technology with small power consumption can be obtained.

The clock recovery method and the clock recovery circuit of the synchronous serial data communication system of the present invention have a simple circuit configuration and a low power consumption circuit configuration.

The clock recovery method and clock recovery circuit of the synchronous serial data communication system of the present invention can recover the reception clock synchronized with the transmission clock even if the data communication speed is set to 1 Mbps, but the frequency of the reference clock is set to about 16 MHz. The circuit can be easily implemented by simply applying the oscillation circuit and the gate circuit.

The clock recovery method and the clock recovery circuit of the synchronous serial data communication system of the present invention provide high-speed data communication because the time difference between the rising edge of the finally received recovery clock and the rising edge of the transmission clock is extremely short compared to the total data settling time. It can be applied to the system at all, and data can be stably detected even in a high speed data transmission system.

The clock recovery method and the clock recovery circuit of the synchronous serial data communication system of the present invention can reduce the area occupied by the circuits related to the clock recovery in the serial data communication system because no PLL circuit is required at all. Power consumption can also be reduced.

Claims (3)

At a receiver of a synchronous serial data communication system; In recovering the reception clock from the input data, Generating a clock divided by 1 / n of a reference clock of n × fi (n is a positive integer of 2 or more) with respect to the frequency fi of the transmission clock during a period of the logic value '0' of the input data; Generating a clock obtained by dividing a reference clock of n × fi by 1 / n with respect to the frequency fi of the transmission clock during a period of the logic value '1', outputting as a final recovery reception clock by ORing the generated clocks A clock recovery method of a synchronous serial data communication system, characterized in that for performing a clock recovery. At a receiver of a synchronous serial data communication system; In recovering the reception clock from the input data, Input data in the form of a bit string transmitted from the transmitting side has a first logic level and a second logic level, and is reset when the input data is the second logic level, and the data during the first logical level. Means for outputting a first preliminary recovery clock divided by 1 / n of a reference clock of n (n is a positive integer of at least two or more) of the transmission rate, and simultaneously reset when the input data is at a first logic level Means for outputting a second preliminary reconstruction clock divided by a reference clock by 1 / n during a period of a second logic level, and a final receiver clock signal obtained by ORing the first and second preliminary reconstruction clocks; The clock recovery circuit of the synchronous serial data communication system, characterized in that the means for restoring and outputting. At a receiver of a synchronous serial data communication system; In recovering the reception clock from the input data, A first divider 52 for dividing the reference clock by 1 / n and outputting the first preliminary restoration clock during a period reset from the logic value '0' of the input data and the logic value '1', and An inverter 53 for inverting the preprocessed input data and a logic value of the input data reset and inverted at a logic value '0' (the logic value '1' of the original data) of the input data inverted through the inverter. A second divider 54 for dividing the reference clock by 1 / n and outputting a second preliminary restored clock during a period of 1 '(the logical value' 0 'of one data); and the first divider And an OR circuit (55) for ORing the outputs (Q1) (Q2) of the second divider to output the last recovered reception clock.