CN107294526A - A kind of improved digital clock and data recovery method - Google Patents
A kind of improved digital clock and data recovery method Download PDFInfo
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- CN107294526A CN107294526A CN201610220774.4A CN201610220774A CN107294526A CN 107294526 A CN107294526 A CN 107294526A CN 201610220774 A CN201610220774 A CN 201610220774A CN 107294526 A CN107294526 A CN 107294526A
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- clock
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- data recovery
- phase
- improved digital
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- 238000011084 recovery Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000005070 sampling Methods 0.000 claims description 8
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 239000013307 optical fiber Substances 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 239000000835 fiber Substances 0.000 description 3
- 241001269238 Data Species 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009123 feedback regulation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
It is exactly that digital high frequency clock carries out clock and data recovery to input serial data specifically the invention provides the improved digital clock and data recovery method of one kind, the method for demodulating input signal.
Description
Technical field
The present invention is a kind of improved digital clock and data recovery method, specifically, is exactly that digital high frequency clock carries out clock and data recovery to input serial data, the method for demodulating input signal.
Background technology
With the popularization of network, the scope that network topology has been had a strong impact on using limitation of twisted-pair wire net, and with the maturation of optic fibre manufacture process, its cost is further reduced, increasing remote, middle distance is all using centralized optical fiber wire laying mode so that the application of fiber plant is intended to low cost, portability.
Fiber-optic signal is high-speed differential signal, high-speed serial data is converted to through optical fiber module and device, usual decoded serial data is that the voltage controlled oscillator carried out using phaselocked loop in data recovery, but phaselocked loop is complex mostly, realize that difficulty is larger with analog device, and may be by technogenic influence；It is of the invention then realize digital clock and data recovery using 4 frequency doubling clocks so as to be the data decoding that 100,000,000 optical fiber can be achieved in master clock only 500MHz；Data storage, recovered clock pulse are carried out simultaneously including the positive and negative edge of clock and carries out a variety of improvement such as data recovery, to realize the decoding request of high speed fibre data transfer.
The content of the invention
A kind of improved digital clock and data recovery method, this method comprises the following steps：By the clock of locally generated 4 times of input data clock frequencies；Input signal is sampled and stored respectively by the positive and negative edge of local clock；Phase difference calculating is carried out to the data that sampling is obtained, adjusting current data sample clock according to phase difference result is advanced or delayed half of clock cycle；Data recovery is carried out to the data sampled with current data sample clock.
Brief description of the drawings
Subject of the present invention is specifically described in detail now with reference to the following drawings, and the relevant structure and implementation method and its purpose, feature and advantage of the present invention is expressly understood：
The improved digital clock data recovery circuit structures of Fig. 1；
Fig. 2 input signal samples storage schematic diagrames；
Fig. 3 phase discriminator structural representations；
Fig. 4 loop filter structure schematic diagrames；
Fig. 5 digital controlled oscillator structural representations.
Embodiment
Although certain this feature and a kind of embodiment described herein as describing the present invention; but for persons skilled in the art; it will occur that many modifications, replacement, change and equivalent substitution, therefore, protection scope of the present invention are defined by the scope of appended claim.
Improved digital clock data recovery circuit is a kind of phase feedback control system, input data sampling module used of the invention is clock double edge trigger, so improve the accuracy of sampling input data signal, using 500MHz clocks, sampling precision is that can reach 1ns, it carries out continuous feedback regulation according to the phase difference between input signal and local estimation clock to local estimation clock, so as to reach the purpose for making local estimation clock phase and input signal clock phase difference close to zero；The present invention is made up of 5 modules, as shown in Figure 1, respectively signal sampling module 100, digital phase discriminator 101, digital loop filters 102, digital controlled oscillator 103, data recovery module 104.
1st, digital controlled oscillator 103 exports 2 groups（4）Different pulse signals, as shown in figure 5, respectively Clock_R0, Clock_F0, Clock_R1, Clock_F, then：
When being output as Clock_R0, Clock_F0, xor operation is carried out using Data_2bits low level in Fig. 3；
When being output as Clock_R1, Clock_F1, xor operation is carried out using the high-order of Data_2bits in Fig. 3.
2nd, Fig. 2 is input data samples storage operation chart, in the rising edge of Clk_4x master clocks（R points in Fig. 2）And trailing edge（F points in Fig. 2）A samples storage is respectively carried out, then P points are combined the data storage of R, F point in fig. 2, and R point datas are in a high position, and F point datas are in low level, i.e. P={ R, F }.
3rd, Fig. 3 is that the phase discriminator in phase discriminator and data recovery operation schematic diagram, the present invention is binary phase discriminator, i.e. only two kinds of phase difference polarity of lead and lag, and phase discriminator is in clock edge transition pulse（Clock_R and Clock_F）A high position or low data on place's sampling Data_2bits（Exported and determined according to DCO, with reference to 1）, it is deposited with Memmory, their correspondences is sent in two-way XOR again at trailing edge pulse Clock_F, phase error information is judged and exports, it is that phase is advanced that Sign, which provides phase error polarity, i.e. Clock_R, Clock_F relative to source data clock,（Sign=1）Or it is delayed（Sign=0）, AbsVal provides phase error absolute value：If data have saltus step, judge effective, AbsVal outputs 1；If data are without saltus step, judge invalid；AbsVal outputs 0 carry out data calculating due to the rising edge pulse and trailing edge pulse in the present invention using local estimation clock, so carrying out data recovery using rising edge pulse in data recovery, it can so ensure to ensure the correctness for recovering data in the case where participating in without loop filter, then enter line number in the d points and b points shown in Fig. 3 and can recover current data according to xor operation to be 0 or be 1.
4th, Fig. 4 is loop filter schematic diagram, and filter function is realized using algebraically summary counter, and control signal is phase difference the judged result Sign and AbsVal of phase discriminator；Algebraically accumulator initial value is set as M/2, carries out algebraically accumulation operations according to control signal Sign and AbsVal, after counter reaches boundary value 0 or M, accumulator count value reverts to M/2, while responsively output DCO control signals Up or Down.Phase error output is cancelled out each other due to keeping the probability of same polarity minimum for a long time in algebraically accumulator caused by random noise, the accuracy without influenceing control signal Up and Down, has reached the purpose of denoising.
5th, Fig. 5 is digital controlled oscillator schematic diagram, digital controlled oscillator is driven by stable Clk_4x master clocks, due to the rising edge and trailing edge Simultaneous Sampling Data signal of present invention application Clk_4x clocks, so 1/2 cycle of master clock is the Phase Tracking precision under phase lock loop locks state, when digital controlled oscillator DCO does not have high impulse to occur on control signal Up and Down, frequency counter CntS only carries out once Jia 2 operation, produces the data recovery clock locally estimated；When having high impulse to occur on control signal Up, operation that frequency counter progress once Jia 3, so as to realize the estimation delayed master clock cycle of clock phase, reaches the effect for adjusting phase backward, while 2 groups of DCO outputs（4）Clock edge pulse signal is switched over；Equally, when having high impulse to occur on control signal Down, operation that frequency counter progress once Jia 1, so as to realize the estimation super previous master clock cycle of clock phase, reaches the effect for adjusting phase forward, while 2 groups of DCO outputs（4）Clock edge pulse signal is switched over；So far, the data clock locally estimated is locked when reaching that a phase difference is less than an Adjustment precision with optical fiber transmitting terminal real data clock, and DCO exports 2 groups used for data recovery（4）Clock edge pulse, can reach the target for accurately recovering transmission data.
Claims (1)
1. a kind of improved digital clock and data recovery method, this method comprises the following steps：By the clock of locally generated 4 times of input data clock frequencies；Input signal is sampled and stored respectively by the positive and negative edge of local clock；Phase difference calculating is carried out to the data that sampling is obtained, adjusting current data sample clock according to phase difference result is advanced or delayed half of clock cycle；Data recovery is carried out to the data sampled with current data sample clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610220774.4A CN107294526A (en) | 2016-04-11 | 2016-04-11 | A kind of improved digital clock and data recovery method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610220774.4A CN107294526A (en) | 2016-04-11 | 2016-04-11 | A kind of improved digital clock and data recovery method |
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| CN107294526A true CN107294526A (en) | 2017-10-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610220774.4A Pending CN107294526A (en) | 2016-04-11 | 2016-04-11 | A kind of improved digital clock and data recovery method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113886300A (en) * | 2021-09-23 | 2022-01-04 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87104871A (en) * | 1986-07-15 | 1988-02-03 | 哈依斯微型计算机产品公司 | The modulator-demodulator that has improved digital signal processor |
| CN1360396A (en) * | 2000-12-21 | 2002-07-24 | 日本电气株式会社 | Clock and data restoring circuit and its clock control method |
| CN1633027A (en) * | 2003-12-22 | 2005-06-29 | 上海贝岭股份有限公司 | A frequency and phase discriminator circuit with effective double frequency error-locking suppression |
| CN1706143A (en) * | 2002-09-16 | 2005-12-07 | 希格纳尔集成产品公司 | Clock recovery method for bursty communications |
| CN1913359A (en) * | 2005-08-11 | 2007-02-14 | 三星电子株式会社 | Apparatus and method for clock data recovery with low lock frequency |
| CN1968063A (en) * | 2006-10-26 | 2007-05-23 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101339798A (en) * | 2007-07-02 | 2009-01-07 | 索尼株式会社 | Clock generation circuit, recording device and clock generation method |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN102629863A (en) * | 2012-04-06 | 2012-08-08 | 开源集成电路(苏州)有限公司 | PWM (Pulse Width Modulation) circuit and LED drive circuit |
| CN102946306A (en) * | 2012-11-23 | 2013-02-27 | 中国电子科技集团公司第三十二研究所 | Clock data recovery circuit structure and digitization clock data recovery method |
| CN103152155A (en) * | 2012-10-22 | 2013-06-12 | 杭州开鼎科技有限公司 | Method for fast clock data recovery |
| CN103368566A (en) * | 2012-04-01 | 2013-10-23 | 北京新岸线移动多媒体技术有限公司 | Clock control circuit and clock control method |
| CN103684447A (en) * | 2014-01-07 | 2014-03-26 | 英特格灵芯片(天津)有限公司 | Clock data recovery circuit and judgment method for data locking |
| CN103713194A (en) * | 2012-10-08 | 2014-04-09 | 富士通株式会社 | Phase detection method for clock recovery and apparatuses |
| CN104363016A (en) * | 2014-10-17 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Clock and data recovery circuit and clock and data recovery method |
-
2016
- 2016-04-11 CN CN201610220774.4A patent/CN107294526A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87104871A (en) * | 1986-07-15 | 1988-02-03 | 哈依斯微型计算机产品公司 | The modulator-demodulator that has improved digital signal processor |
| CN1360396A (en) * | 2000-12-21 | 2002-07-24 | 日本电气株式会社 | Clock and data restoring circuit and its clock control method |
| CN1706143A (en) * | 2002-09-16 | 2005-12-07 | 希格纳尔集成产品公司 | Clock recovery method for bursty communications |
| CN1633027A (en) * | 2003-12-22 | 2005-06-29 | 上海贝岭股份有限公司 | A frequency and phase discriminator circuit with effective double frequency error-locking suppression |
| CN1913359A (en) * | 2005-08-11 | 2007-02-14 | 三星电子株式会社 | Apparatus and method for clock data recovery with low lock frequency |
| CN1968063A (en) * | 2006-10-26 | 2007-05-23 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101339798A (en) * | 2007-07-02 | 2009-01-07 | 索尼株式会社 | Clock generation circuit, recording device and clock generation method |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN103368566A (en) * | 2012-04-01 | 2013-10-23 | 北京新岸线移动多媒体技术有限公司 | Clock control circuit and clock control method |
| CN102629863A (en) * | 2012-04-06 | 2012-08-08 | 开源集成电路(苏州)有限公司 | PWM (Pulse Width Modulation) circuit and LED drive circuit |
| CN103713194A (en) * | 2012-10-08 | 2014-04-09 | 富士通株式会社 | Phase detection method for clock recovery and apparatuses |
| CN103152155A (en) * | 2012-10-22 | 2013-06-12 | 杭州开鼎科技有限公司 | Method for fast clock data recovery |
| CN102946306A (en) * | 2012-11-23 | 2013-02-27 | 中国电子科技集团公司第三十二研究所 | Clock data recovery circuit structure and digitization clock data recovery method |
| CN103684447A (en) * | 2014-01-07 | 2014-03-26 | 英特格灵芯片(天津)有限公司 | Clock data recovery circuit and judgment method for data locking |
| CN104363016A (en) * | 2014-10-17 | 2015-02-18 | 青岛歌尔声学科技有限公司 | Clock and data recovery circuit and clock and data recovery method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113886300A (en) * | 2021-09-23 | 2022-01-04 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
| CN113886300B (en) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
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