CN100428647C - Method for keeping uniform of main/stand-by clock of communication system - Google Patents
Method for keeping uniform of main/stand-by clock of communication system Download PDFInfo
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- CN100428647C CN100428647C CNB2005100349634A CN200510034963A CN100428647C CN 100428647 C CN100428647 C CN 100428647C CN B2005100349634 A CNB2005100349634 A CN B2005100349634A CN 200510034963 A CN200510034963 A CN 200510034963A CN 100428647 C CN100428647 C CN 100428647C
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Abstract
The present invention discloses a method for keeping the uniformity of a main clock board and a backup clock board of a communication system. The main clock board can be kept in a free oscillation state or a keeping state. Moreover, a series of clock signals output by the main clock board is used as reference sources of the backup clock board. The backup clock board tracks the clock signals output by the main clock board and synchronizes output clock frequency with the output clock frequency of the main clock board. Under the condition that the output frequencies of the main and the backup clock boards are uniform, the phase adjustment of the output signals of the backup clock board is used for locking the main output signals, and thus, the uniformity of the output phases of the main clock board and the backup clock board can be ensured. The scheme ensures the effect that the backup clock board always tracks the output of the main clock board and the uniformity of the main clock board and the backup clock board. Therefore, the communication system can be disengaged from an external synchronization reference source and can not be influenced by the external synchronization reference source. The stability of communication devices is raised, the devices are simplified simultaneously, and the costs of the devices are reduced.
Description
[technical field]
The present invention relates to the clock board of communication apparatus, relate in particular to the method that is consistent at the main/stand-by clock that does not have to make under the situation of External synchronous reference source system.
[background technology]
Clock is communication equipment stable operation, and the basis of good data and voice service is provided.So guarantee that the accuracy of communication equipment clock and stability are very important for communication equipment.So each correspondence entity, country and operator all will carry out strict test to the clock performance of equipment before equipment networks.The index of clock mainly comprises long-term stability, and long-term accuracy keeps performance, phase transient and phase discontinuity etc.
Communication equipment generally has two mutually clock boards of backup, provides system clock by the clock board of main usefulness wherein.Keep the consistent of phase place and frequency during for active/standby single board changeover, must when normal operation, guarantee that active and standby plate frequency is consistent with phase place.Generally, active and standby plate is followed the tracks of same reference source simultaneously, can guarantee the unanimity of output frequency, by the phase place adjustment to the standby plate output signal, goes to lock the main unanimity that can guarantee output phase with output signal.Guarantee that standby output signal is consistent with output signal with main, must at first will guarantee active and standbyly to be consistent with output signal frequency.
But under some environment, be subjected to the restriction of equipment network site of living in, communication equipment can not obtain reference source from the outside.The output signal frequency of main and standby boards is decided by the frequency of crystal on the veneer in this case, because the otherness of crystal can not guarantee that the frequency of two veneers is consistent, can not guarantee the unanimity of phase place more, when carrying out masterslave switchover, will cause the saltus step of device systems clock, influence the performance of equipment.
In order to solve the clock reference source problem of main and standby boards, common scheme is GP configuring S (Global:Position System on main and standby boards, be global positioning system) module, IPPS (the Pulse Per second that utilizes GPS to provide, be the umber of pulse of per second) as external reference source, main and standby boards is followed the tracks of the IPPS signal that GPS provides simultaneously.The shortcoming of this technology is: 1) reference source is too single, too relies on gps satellite signal, if gps satellite signal breaks down or suffers artificial interference, main and standby boards will be in the reference source-free state again so.2) increased engineering complexity.The GPS module comprises that satellite accepts card portion and antenna part, and the installation of antenna has greatly increased to the complexity of engineering.3) increased the cost of equipment.
[summary of the invention]
Main purpose of the present invention just provides the method that a kind of main/stand-by clock that makes communication system under the situation that does not have the external clock reference source is consistent.
For achieving the above object, method that a kind of main/stand-by clock that makes communication system is consistent that the present invention proposes, comprise the control main/stand-by clock frequency one control main/stand-by clock phase place unanimity of making peace, wherein the realization of main/stand-by clock phase place unanimity is based on the basis of main/stand-by clock frequency unanimity, consistent may further comprise the steps of described control main/stand-by clock frequency:
It is invalid that the External synchronous reference source of active clock plate is set to, make the active clock plate be in free-running operation or hold mode, and with the road clock signal that is suitable for the reference of standby clock plate of the active clock plate output reference synchronization source as the standby clock plate, the clock signal output interface that a road of standby clock plate is suitable for the reference of active clock plate is connected with the External synchronous reference source interface of active clock plate;
The standby clock plate is followed the tracks of clock signal, will export the clock frequency of the Frequency Synchronization of clock to the output of active clock plate.
The method that makes the active clock plate be in free-running operation or hold mode can be any in the following scheme:
A) make the External synchronous reference source interface of active clock plate vacant;
B) External synchronous reference source of active clock plate be set to invalid.
Convenient when switching for the main/stand-by clock plate, it is invalid that preferred version is that the External synchronous reference source of active clock plate is set to, the clock signal output interface that a road of standby clock plate is suitable for the reference of active clock plate is connected with the External synchronous reference source interface of active clock plate, and the clock signal of the clock signal of standby clock plate output and the output of active clock plate is set to identical type.
When the main/stand-by clock plate is switched, after former standby clock plate becomes new active clock plate, former active clock plate and becomes new standby clock plate, make new active clock plate be in hold mode, and with the road clock signal that is suitable for new standby clock plate reference of the new active clock plate output External synchronous reference source as new standby clock plate; New standby clock plate is followed the tracks of clock signal, the Frequency Synchronization of output clock is arrived the clock frequency of new active clock plate output.
The invention has the beneficial effects as follows: 1) this programme has broken away from External synchronous reference source, is not subjected to the influence of External synchronous reference source, and the while has also simplified equipment, reduced the cost of equipment.Be that this programme is not having under the situation of External synchronous reference source, still can guarantee the primary, spare clock unanimity of system.Do not having under the situation of External synchronous reference source, the output of active clock plate is connected with the External synchronous reference source interface of standby clock plate, the active clock plate then is in free-running operation or hold mode because of no External synchronous reference source, and the standby clock plate can go the output of active clock plate to follow the tracks of as External synchronous reference source at this moment, thereby the frequency output that can guarantee the main/stand-by clock plate is consistent.2) easier when the main/stand-by clock plate is switched, while also is connected the output of standby clock plate with the External synchronous reference source interface of active clock plate, and the External synchronous reference source of forcing to be provided with the active clock plate is invalid, and the active clock plate still is in free-running operation or hold mode.When the main/stand-by clock plate was switched, standby clock plate originally became the active clock plate, and it is invalid that External synchronous reference source is forced to be made as, become the frequency state that keeps original, active clock plate originally becomes the standby clock plate, and reference source becomes effectively, begins to follow the tracks of External synchronous reference source.So just guaranteed that under this pattern no matter all keep the standby clock plate to follow the tracks of the active clock plate after still switching before switching, and the output frequency of main/stand-by clock plate is consistent.
Feature of the present invention and advantage will be elaborated in conjunction with the accompanying drawings by embodiment.
[description of drawings]
Fig. 1 is the main/stand-by clock plate connection diagram of a kind of embodiment of the present invention;
Fig. 2 is the invalid flow chart that is provided with in External Reference source of the active clock plate of a kind of embodiment of the present invention.
[embodiment]
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
(for example communication apparatus) needs two clock boards of active and standby usefulness in some equipment, when equipment normally moves wherein one for the active clock plate, for whole system provides clock signal accurately.Another piece is the standby clock plate, the standby clock signal of action system, promptly as the backup of active clock plate, every clock board all has one road External synchronous reference source interface, be used to receive the reference signal of outside input, if outer synchronous reference signal is arranged, when working, clock board can follow the tracks of synchronous reference signal outside this.Simultaneously clock board also has a plurality of clock signal output interfaces and is used to communication system that multiple clock signal is provided, but only meets just being suitable for as the clock board reference of following condition: the reference synchronization source signal of the signal of output and design is that the frequency of reference synchronization source signal of same signal type or its frequency and design is close.One of them clock signal output interface when making test with or offer other system's use, meet above-mentioned condition, can be used as the reference synchronization source of standby clock plate.
Every clock board comprises detection module, control module, relying on External synchronous reference source to guarantee under the situation of main/stand-by clock plate output frequency unanimity, detection module is by being connected with the External synchronous reference source interface to detect the External synchronous reference source signal, according to whether having the External synchronous reference source signal to export different signals, for example when having detected the input of External synchronous reference source signal, detection module output high level is when detecting when not having the input of External synchronous reference source signal the detection module output low level.Control module receives the signal of the detection module output of same clock board, judge according to this signal, if the External synchronous reference source signal is arranged then control this clock board and follow the tracks of the External synchronous reference source signal, if do not have the External synchronous reference source signal then to the signal of the no External synchronous reference source of this clock board output, this clock board then can be in free-running operation or hold mode.
In the present embodiment, the annexation of main/stand-by clock plate as shown in Figure 1, the clock signal output interface 1 of active clock plate is connected with the External synchronous reference source interface 2 of standby clock plate, the clock signal output interface 3 of standby clock plate is connected with the External synchronous reference source interface 4 of active clock plate, the clock signal output interface 1 that the active clock plate is set in addition has identical type with the clock signal output interface 3 of standby clock plate to the signal of External synchronous reference source interface 4 outputs of active clock plate to the signal of External synchronous reference source interface 2 outputs of standby clock plate, it is the input of active clock plate and standby clock plate, the signal type of output signal is identical, can be set to 2MHz, the signal of 10MHz or 2Mbits.Various signal types are set by the following method: for the signal type of output signal, the signal of output certain frequency by the software control frequency dividing circuit, produces the signal of different frequency earlier.For example export the signal of 10MHz earlier,, can produce the signal of 2MHz by frequency dividing circuit.For the signal type of input signal, by the signal of interface circuit input different frequency, according to the frequency of input signal, by software setting, the may command electronic switch switches to corresponding circuit.
The transmission of signal between the main/stand-by clock plate can also can be by backboard (wiring board that can peg graft) by cable.
Cause from ring in order to prevent that the main/stand-by clock plate from following the tracks of mutually, thereby make clock frequency more and more depart from required value, the External synchronous reference source that present embodiment is provided with the active clock plate is invalid, specifically is that the step by as shown in Figure 2 realizes:
1) detection module detects the External synchronous reference source signal, and according to whether the External synchronous reference source signal being arranged to the different signal of control module output; When the External synchronous reference source signal was arranged, detection module was exported high level signal to control module, and during no External synchronous reference source signal, detection module is to control module output low level signal;
2) control module receives the signal of detection module output, and to the signal of the no External synchronous reference source of active clock plate output, promptly control module is high level or low level signal regardless of what receive, all exports the signal of no External synchronous reference source to the active clock plate.
The active clock plate is in free-running operation or hold mode under the situation of no External synchronous reference source, the clock frequency of output is decided by the frequency of self crystal.
The External synchronous reference source of active clock plate is set to invalidly also can realize by following steps:
1) detection module detects the External synchronous reference source signal, all exports the signal of no External synchronous reference source to control module;
2) control module receives the signal of detection module output, to the signal of the no External synchronous reference source of active clock plate output.
It is invalid that the External synchronous reference source of standby clock plate is not set to, thus the frequency of the clock output tracking External synchronous reference source signal of standby clock plate, and output is synchronized to the clock output of active clock plate.
Because the clock signal output interface of main/stand-by clock plate is the existing interface that is used to test, so the present invention can realize breaking away from External synchronous reference source on the basis that need not change existing design substantially, and the consistency of assurance master/backup clock signal, reduced manufacturing cost and use cost.
In the foregoing description, the clock signal output interface can also be other clock signal output terminals, if guarantee the signal of its output be suitable for as the signal type of the reference source of active clock plate or standby clock plate and the output of main/stand-by clock plate identical.
Another embodiment is that the External synchronous reference source that the active clock plate is set is vacant state, and detection module detects less than the External synchronous reference source signal, then to the signal of the no External synchronous reference source of control module output; Control module receives the signal of detection module output, to the signal of the no External synchronous reference source of active clock plate output.Thereby make the active clock plate be in free-running operation or hold mode.
When the main/stand-by clock plate is switched, be after former standby clock plate becomes new active clock plate, former active clock plate and becomes new standby clock plate, it is invalid that the External Reference source of then new active clock plate is set to, and with the clock signal of the new active clock plate output reference synchronization source as new standby clock plate, the clock signal output interface of new standby clock plate is connected with the reference synchronization source interface of new active clock plate.New standby clock plate is followed the tracks of clock signal, the Frequency Synchronization of output clock is arrived the clock frequency of new active clock plate output.
The present invention has guaranteed it is the clock frequency output that the standby clock plate is followed the tracks of the active clock plate all the time in the system, and has guaranteed the unanimity of main/stand-by clock plate output frequency.There have been above two assurances just can realize that the output phase of standby clock plate also goes to follow the tracks of the phase place of active clock plate output clock, the method that guarantees the phase place unanimity can same prior art, thereby realized the unanimity of main/stand-by clock plate in reference source-free situation lower frequency phase place, guarantee the stability of phase place in the clock board reversed process, thereby increased the stability of communication equipment.
The present invention not only can be applicable in the communication apparatus, all can use for any equipment with master/backup clock.
Claims (7)
1. method that the main/stand-by clock that makes communication system is consistent, comprise the control main/stand-by clock frequency one control main/stand-by clock phase place unanimity of making peace, wherein the realization of main/stand-by clock phase place unanimity is based on the basis of main/stand-by clock frequency unanimity, it is characterized in that: consistent may further comprise the steps of described control main/stand-by clock frequency:
It is invalid that the External synchronous reference source of active clock plate is set to, make the active clock plate be in free-running operation or hold mode, and with the road clock signal that is suitable for the reference of standby clock plate of the active clock plate output External synchronous reference source as the standby clock plate, the clock signal output interface that a road of standby clock plate is suitable for the reference of active clock plate is connected with the External synchronous reference source interface of active clock plate;
The standby clock plate is followed the tracks of described clock signal, will export the clock frequency of the Frequency Synchronization of clock to the output of active clock plate.
2. the method that the main/stand-by clock that makes communication system as claimed in claim 1 is consistent is characterized in that further comprising the steps of: with the output of standby clock plate
Clock signal is set to identical type with the clock signal of active clock plate output.
3. the method that the main/stand-by clock that makes communication system as claimed in claim 2 is consistent, it is characterized in that: described signal type is 2MHz, 10MHz or 2Mbits signal.
4. the method that the main/stand-by clock that makes communication system as claimed in claim 2 is consistent is characterized in that: the clock signal output interface that is used to test of active clock plate is connected with the External synchronous reference source interface of standby clock plate; The clock signal output interface that is used to test of standby clock plate is connected with the External synchronous reference source interface of active clock plate.
5. the method that the main/stand-by clock that makes communication system as claimed in claim 1 is consistent, it is characterized in that: the External synchronous reference source of described active clock plate is set to invalid may further comprise the steps:
Whether 1) detection module detects the External synchronous reference source signal, according to having the External synchronous reference source signal to export different signals;
2) control module receives the signal of detection module output, to the signal of the no External synchronous reference source of active clock plate output.
6. the method that the main/stand-by clock that makes communication system as claimed in claim 1 is consistent, it is characterized in that, described method further comprises: when the main/stand-by clock plate is switched, after former standby clock plate becomes new active clock plate, former active clock plate and becomes new standby clock plate, make new active clock plate be in hold mode, and with the road clock signal that is suitable for new standby clock plate reference of the new active clock plate output reference synchronization source as new standby clock plate; New standby clock plate is followed the tracks of described clock signal, the Frequency Synchronization of output clock is arrived the clock frequency of new active clock plate output.
7. the method that is consistent as each described main/stand-by clock that makes communication system in the claim 1 to 6, it is characterized in that: the signal transmission between described active clock plate and the standby clock plate is by cable transmission or backboard transmission.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100349634A CN100428647C (en) | 2005-05-27 | 2005-05-27 | Method for keeping uniform of main/stand-by clock of communication system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100349634A CN100428647C (en) | 2005-05-27 | 2005-05-27 | Method for keeping uniform of main/stand-by clock of communication system |
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| Publication Number | Publication Date |
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| CN1870453A CN1870453A (en) | 2006-11-29 |
| CN100428647C true CN100428647C (en) | 2008-10-22 |
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| CNB2005100349634A Expired - Fee Related CN100428647C (en) | 2005-05-27 | 2005-05-27 | Method for keeping uniform of main/stand-by clock of communication system |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903620A (en) * | 1996-06-28 | 1999-05-11 | Nec Corporation | System switching circuit based on phase matching |
| CN1324148A (en) * | 2000-07-11 | 2001-11-28 | 深圳市中兴通讯股份有限公司 | Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system |
| CN1553622A (en) * | 2003-06-04 | 2004-12-08 | 中兴通讯股份有限公司 | Method and device for realizing main backup of clock in synchronizing system |
| CN1555168A (en) * | 2003-12-24 | 2004-12-15 | 烽火通信科技股份有限公司 | Damage-free switching method for main and spare synchronous digital series device timing source |
-
2005
- 2005-05-27 CN CNB2005100349634A patent/CN100428647C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903620A (en) * | 1996-06-28 | 1999-05-11 | Nec Corporation | System switching circuit based on phase matching |
| CN1324148A (en) * | 2000-07-11 | 2001-11-28 | 深圳市中兴通讯股份有限公司 | Jitter-free change-over method and device for main and stand-by units capable of being hot plugged and unplugged in digital communication system |
| CN1553622A (en) * | 2003-06-04 | 2004-12-08 | 中兴通讯股份有限公司 | Method and device for realizing main backup of clock in synchronizing system |
| CN1555168A (en) * | 2003-12-24 | 2004-12-15 | 烽火通信科技股份有限公司 | Damage-free switching method for main and spare synchronous digital series device timing source |
Non-Patent Citations (2)
| Title |
|---|
| 小型SDH光纤通信环网的同步和保护. 王海涛.电力系统通信，第6期. 2002 |
| 小型SDH光纤通信环网的同步和保护. 王海涛.电力系统通信，第6期. 2002 * |
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