KR100279714B1 - Clock generator device - Google Patents

Abstract

end. TECHNICAL FIELD OF THE INVENTION

Description of the Related Art A clock generator apparatus for generating a digital clock in a synchronous transmission system.

I. The technical problem to be solved by the invention

It can be changed adaptively to various external clock changes, and at the same time, it can be used with minimal modification and component replacement when improving performance, and provides a clock generator device that can detect faults.

All. Summary of Solution of the Invention

The present invention relates to a clock generator device of a transmission system, comprising: a clock connection unit for receiving a clock from an external synchronization source and outputting an internally selected clock to other boards, a clock received from the clock connection unit, and respective boards of the transmission system; A reference signal selector which receives clocks received from the controller and selects a clock having the best clock state and outputs two different clocks; and a transmission PEL that phase-locks and outputs one clock received from the reference signal selector And a reception PEL for phase-locking and outputting another clock received from the reference signal selection unit, and a clock from the transmission PEL and the reception PEL and received by each board of the transmission system. Outputs clocks with equal phase delay and consists of field programmable gate arrays (FPGAs), programmable logic Is a controller configured to include a clock branching unit, a state controller for collecting the state information of each unit of the clock generator, and a programmable logic unit connected to a system control unit for controlling the overall operation of the transmission system and outputting the collected state information. And an oscillator for inputting a clock to the controller, wherein the configuration is made of one subboard.

la. Important uses of the invention

It can be used for synchronous transmission system or exchange system.

Description

Clock generator device

The present invention relates to a clock generator device, and more particularly to a clock generator device of a synchronous transmission system.

Typically, the most important factor for the transmission and recovery of data transmitted and received in the transmission system is the clock. This is because in the synchronous transmission system, when the clock is irregularly received or an error occurs in the clock, both the transmitted data and the restored data are lost. Such a synchronous transmission system is very complicated with the development of communication technology, and the clock used in the transmission system also requires various clocks. Therefore, the clocks used in the transmission system can be classified into: firstly, a clock received together with the transmitted data, secondly an internally generated clock, and thirdly a clock received from the outside, that is, another board. Many clocks are received and compared. The best clock is used among clocks satisfying the same condition. However, as described above, as the transmission system evolves and the types of transmission systems are diversified, clocks change according to the manufacturer or the amount of data to be transmitted or the configuration of a network connected to the transmission system. Therefore, the clock generator applied to the transmission system according to the network or the transmission speed needs to be adaptively implemented. In practice, however, the clock generator consists of a single unit, which requires a redesign of the board, which also requires time to verify the functionality. This acts as a factor to increase the cost of the transmission system, and because it adopts the integrated implementation method, it is not possible to search for failures, and the maintenance is difficult. In addition, since the clock generator is not connected to the system control unit of the transmission system, there is a problem that an operator cannot grasp the state information of the clock output from the clock generator.

Accordingly, an object of the present invention is to provide a clock generator device which can be changed in function according to the type of network and which can be adaptively used for each transmission system.

Another object of the present invention is to provide a clock generator that is inexpensive, has a fault detection, and is easy to maintain.

The present invention for achieving the above object is a clock generator apparatus of a transmission system, the clock connection unit for receiving a clock from an external synchronization source, and outputs the clock selected from the internal board, and a clock received from the clock connection unit and A reference signal selector which receives clocks received from each board of the transmission system, selects a clock having the best state of clock, and outputs two different clocks; and one clock received from the reference signal selector A transmission PEL that synchronously outputs, a reception PEL that phase-synchronizes and outputs another clock received from the reference signal selector, and receives a clock from the transmission PEL and the reception PEL, and the transmission system Programmable logic that outputs the clock required by each board in the same phase delay And a clock branching unit configured to be connected to a system control unit which collects state information of each unit of the clock generator and controls an overall operation of the transmission system, and outputs the collected state information and is configured as an FPGA which is programmable logic. A control unit and an oscillator for inputting a clock to the control unit are characterized in that the above configuration consists of one subboard.

1 is a block diagram of a clock generator device according to a preferred embodiment of the present invention;

2 is a block diagram of a controller implemented according to the present invention in a clock generator device;

3 is a block diagram illustrating a reference signal selector of a clock generator in accordance with a preferred embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a clock generator apparatus according to a preferred embodiment of the present invention. Reference numerals 10a and 10b shown in Fig. 1 have the same configuration, and are redundant clock generator devices for stabilizing clock supply in a synchronous transmission system, each consisting of one subboard. As a representative, the internal configuration will be described with reference to the subboard of the clock generator device 10a. The clock connection unit 11 receives a clock from an external synchronization source and simultaneously transmits the clock to the outside. In addition, the clock connection unit 11 outputs a clock received from the outside to the reference signal selector 200. In the embodiment of the present invention, the reference signal selector 200 is configured as a field programmable gate array (FPGA), which is programmable logic. The clock selected as the best clock is output as the reference clock signal. In this case, the clock received by the reference signal selector 200 may include a clock received from the clock connection unit 11, a clock received from a Tributary Unit (TU) board provided in the transmission system, and an LMU provided in the transmission system. Line Monitering Unit) receives a clock received from a board and clocks received from a pair of clock generator devices 10b. The state of the received clocks is checked, and the best clock is selected according to the check result. However, if all the received clocks are in a bad state and cannot be used, a signal (No Reference Source) is declared to be unavailable as a reference signal. Accordingly, the received PLL 12 phase-locks the clock signal received from the reference signal selector 200 as the reference clock and outputs the clock signal to the other clock generator 10b in pairs with the clock branching unit 14. The PLL 13 also phase-locks the clock signal received from the reference signal selector 200 as the reference clock and outputs the clock signal to the other clock generator 10b in pairs with the clock branching unit 14. Here, the detailed description and detailed configuration of the reception PEL 12 and the transmission PEL 13 are technologies other than the technical scope to be implemented in the present invention, and thus detailed descriptions thereof will be omitted. The clock branching unit 14 transfers the clocks received from the reception PEL 12 and the transmission PEL 13 to each board or rack of the transmission system so as to have the same phase so as to be synchronized with the same clock. The oscillator 15 generates a clock of 16.384 MHz, which is a clock used in a transmission system or an exchange system, and outputs the clock to the controller 100. The controller 100 is configured as a field programmable gate array (FPGA) that is programmable logic according to the present invention, performs control of each part of the clock generator 10a, collects state information, and controls on / off by LED logic. Output the signal. In addition, it transmits the information according to the clock state of the clock generator to the system control unit that performs the overall control of the transmission system. The controller 100 is connected to each unit of the clock generator 10a through a bus 16 to collect information according to the clock status and the operation state of each unit. In addition, the control unit 100 includes a memory and stores information according to the collected result.

As such, the reference signal selector 200 and the controller 100 are configured as FPGAs, which are programmable logic, so that even when a performance improvement operation is required, only the FPGA is modified without a circuit modification, and a program is stored according to the operation. It can be improved simply by replacing only the memory. Next, an internal configuration of the controller 100 and the reference signal selector 200 will be described with reference to FIGS. 2 and 3.

2 is a block diagram of a controller implemented according to the present invention in a clock generator device. Hereinafter, the configuration and operation of the controller according to the present invention will be described in detail with reference to FIGS. 1 to 2. The first monitoring controller 101 is connected to each part of the clock generator 10a through the bus 16 to transmit and receive data. The first surveillance controller 101 outputs the received data to the second surveillance controller 105 or stores the received data in the internal memory of the first connection unit 106. Since the first connection unit 106 is connected to the system control unit, the system control unit can check the clock state of the clock generator by reading data stored in the internal memory of the first connection unit 106 from time to time. The timing generator 102 receives a clock received from the oscillator 15 and various clocks received from the reference signal selector 200 and outputs a clock signal to the first monitoring controller 101 and the failure detector 103 for use as an internal clock. The failure detector 103 detects whether the clock received from the timing generator 102 is enabled or disabled by the control of the second monitoring controller 105, and outputs the detected result to the reference signal selector 200. The transfer controller 104 performs switching control when performing transfer with the clock generator 10b on the other side in pairs under the control of the second supervisor controller 105. The LED controller 108 displays the operation state of the clock generator 10a by LED logic (not shown in FIG. 2) under the control of the second supervisor controller 105. The second connection unit 107 is connected to the system control unit of the transmission system and receives control signals such as a system clock and a reset received from the system control unit and outputs the control signals to the second monitoring controller 105. The second monitoring controller 105 has a memory therein for storing data according to the operation state of each unit received from the first monitoring controller 101, and performs control of each unit included in the controller 100.

3 is a block diagram illustrating a reference signal selector of a clock generator according to an exemplary embodiment of the present invention. Hereinafter, the configuration and operation of the reference signal selector will be described in detail with reference to FIGS. 1 to 3. As described above, the TU board, the LMU board, and all kinds of clocks generated externally and internally of the transmission system are input to the reference signal selector 200 of the clock generator. Then, all kinds of clocks input to the reference signal selector 200 of the clock generator are input to the internal first fixed selector 201, the timing selector 204, and the second fixed selector 209. Accordingly, the timing selector 204 outputs the received clock to the first timing selector 203, the second timing selector 207, and the main controller 205. Accordingly, the main controller 205 checks the quality of the clock received from the timing selector 204, generates a control signal according to the clock selection, and outputs the clock selection signal to the first fixed selector 201 and the first timing selector 203. In addition, the main controller 205 outputs a control signal for selecting a clock output to the reception PEL side to the second fixed selector 209 and the second timing selector 207. Accordingly, the timing selector 204 selects a clock received by the control of the main controller 205 and outputs the clock to the first timing selector 203 and the second timing selector 207. Then, the first timing selector 203 and the second timing selector 207 phase-synchronize the selected clock to output the first switch controller 204 and the second switch controller 208. In addition, the first fixed selector 201 and the second fixed selector 209 output all clocks received by the clock generator to the first variable selector 202 and the second variable selector 210. The first variable selector 202 and the second variable selector 210 select and output a clock based on a clock control signal received from the first switch controller 204 and the second switch controller 208, respectively. The first switch controller 204 and the second switch controller 208 output the clock control signal under the control of the main controller 205.

As a result, when the clock is selected, the first variable selector 202 outputs the clock selected to the transmitting PEL side, and the second variable selector 210 outputs the selected clock to the receiving PEL side. In addition, the first switch controller 204 transmits the information on the clock selected to the transmission PEL side, and the second switch controller 208 transmits the information on the clock selected to the receiving PEL side. The control connection unit 206 interfaces data transmitted and received between the controller 100 and the main controller 205.

As described above, the reference signal selector and the controller are configured in the clock generator using programmable logic logic (FPGA), thereby minimizing modifications when external connection conditions change. In addition, there is an advantage that it is possible to facilitate the detection of the failure by having a control unit inside the clock generator to enable the transmission and reception of data with the system control unit of the transmission system. In addition, the use of FPGAs eliminates the need for commercially available devices, resulting in cost savings.

Claims (5)

A clock generator apparatus of a transmission system, A clock connection unit for receiving a clock from an external synchronization source and outputting an internally selected clock to other boards; A reference signal selector for receiving the clock received from the clock connection unit and the clocks received from the respective boards of the transmission system, selecting a clock having the best clock state, and outputting two different clocks; A transmission PEL for synchronizing and outputting one clock received from the reference signal selector; A reception PLL for phase-locking and outputting another clock received from the reference signal selector; It is composed of a clock branching unit for receiving a clock from the transmitting PEL and the receiving PEL, and outputs the clock required by each board of the transmission system so that the phase delay is the same. And a clock generator device. The method of claim 1, A control unit which collects state information of each unit of the clock generator and is connected to a system control unit which controls the overall operation of the transmission system and outputs the collected state information; And an oscillator for inputting a clock to the controller. The method of claim 1, And the reference signal selector (FPGA) is programmable logic. The method of claim 2, And the control unit is configured with programmable logic (FPGA). The method according to claim 2 or 4, And a memory for storing, by the control unit, information collected by each unit of the clock generator device.