JPH08163162A - Loop type data transmitter - Google Patents

Abstract

PURPOSE: To perform communication between the terminal of its own network and that of another network and to perform the communication while subordinately sychronizing with a normal clock when abnormality occurs in a clock. CONSTITUTION: The communication within its own network and that with another network can be performed by receiving the clock from another network by a clock input circuit 31 with one of node devices 101-104 of its own network as a synchronization control node, transmitting data from a transmission control circuit 20 based on the clock, and performing the synchronization control within its own network. When the abnormality is detected in the clock, the synchronization control node is operated as a subordinate synchronization node, and the subordinate synchronization node detecting the abnormality of the clock performs synchronization control within its own network by the clock from the clock input circuit 31, and it is operated as the synchronization control node so as to perform the communication within its own network and that with another network.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop type data transmission device for connecting a plurality of node devices to a loop transmission line and transmitting data between terminal devices connected to the respective node devices.

[0002]

2. Description of the Related Art Conventionally, a data transmission apparatus of this type is composed of one synchronization control node for controlling the synchronization of a loop-shaped transmission line and a plurality of subordinate synchronization nodes subordinately synchronized therewith. By bypassing the generated node, it does not affect other nodes. Furthermore, when a failure occurs in the essential synchronous control node and the synchronous control node is bypassed, all functions stop. Therefore, various measures are taken to prevent this.

FIG. 9 is a block diagram of a loop type data transmission apparatus provided with a spare synchronization control node disclosed in, for example, Japanese Patent Publication No. 6-16629. In the figure, 1 is a sync control node, 2 is a subordinate sync node, 3 is a backup sync control node that acts as a proxy for sync control when the sync control node 1 is bypassed due to a failure, etc. 4 is a sync control node 1 and a backup sync control node A backup synchronization control node that acts as a substitute for synchronization control when 3 is bypassed together, 5-8 are terminal devices connected to nodes 1-4 respectively, and 9-12 are bypass circuits for bypassing nodes 1-4 respectively. , 13 are loop transmission lines that connect the nodes 1 to 4 in a loop.

FIG. 10 shows the format of the frame data transmitted in FIG.
It consists of a data word, check bits and a supervisory information word. The flag bit in the monitoring information word is a bit used for the proxy switching control of the synchronization control in the synchronization control node 1 and the preliminary synchronization control nodes 3 and 4.

FIG. 11 is a block diagram showing the synchronization control node 1. In FIG. 11, reference numeral 14 is a reception control circuit, which receives a reception signal from the loop transmission line 13 and distributes the signal to each unit. Reference numeral 15 denotes a loop synchronization control circuit, which performs delay correction, generation of frame data shown in FIG. 10 and data replacement. 16 is a reception timing control circuit, 1
Reference numeral 7 is a terminal reception interface circuit, 18 is a transmission timing control circuit, 19 is a flag setting circuit, 20 is a transmission control circuit, and 21 is a terminal transmission interface circuit.

FIG. 12 is a block diagram showing the preliminary synchronization control node 3. In the preliminary synchronization control node 3, in addition to the configuration of the synchronization control node 1 of FIG. 11, a flag detection circuit 22, a frame synchronization detection circuit 23, a bit error detection circuit 24,
It is composed of an OR circuit 25, a switching control circuit 26, and a switch 27. The backup synchronization control node 4 is also configured in substantially the same manner as the backup synchronization control node 3, and the slave synchronization node 2
In the block diagram of the synchronization control node 1 shown in FIG. 11, the loop synchronization control circuit 15 and the flag setting circuit 19 do not exist, and the output of the reception control circuit 14 is directly connected to the transmission control circuit 20.

Next, the operation will be described. First, the synchronization control node 1 sends frame data whose flag bit is set to “00” by the flag setting circuit 19 to the subordinate synchronization node 2. The subordinate synchronization node 2 does not perform control such as setting of the flag bit but only relays and transmits to the preliminary synchronization control node 3.

When the synchronous control node 1 is bypassed due to some failure, it becomes impossible to send frame data. In the preliminary synchronization control node 3, the frame synchronization detection circuit 23 detects the presence / absence of a synchronization signal and the bit error detection circuit 24 detects the presence / absence of a data error, and a predetermined frame synchronization signal is lost or a data error is detected. In this case, it is determined that the synchronization control node 1 has been bypassed, and the switching control circuit 26 controls the switch 27 to input the output signal of the loop synchronization control circuit 15 to the transmission control circuit 20. Then, it operates as a synchronous control node, and the flag setting circuit 19 sets the flag bit to "01".
Set to to generate frame data and send it to lower nodes. In this way, loop synchronization is established.

Next, the operation when the bypass of the synchronous control node 1 is restored will be described. Since the frame data sent from the synchronization control node 1 becomes normal, the frame synchronization detection circuit 23 of the preliminary synchronization control node 3 detects a frame synchronization signal, and the bit error detection circuit 24 detects no data error. Further, the flag detection circuit 22 can detect the flag. Then, the flag "00" is detected in the state where the frame synchronization is normal and there is no bit error, so that the switching control circuit 2
6 controls the switch 27 to input the output signal of the reception control circuit 14 to the transmission control circuit 20, and operates as the original standby synchronization control node. Then, the flag setting circuit 19 sets the flag to "01" and sends it to the lower node.

The operation of the preliminary synchronization control node 4 is almost the same as the operation of the preliminary synchronization control node 3. That is, when the disappearance of the frame synchronization signal or the bit error is detected, the frame control signal itself becomes the synchronization control node, adds the flag bit “11”, and transfers it to the lower node. In addition, the frame synchronization is normal and there are no bit errors, and the flag is "00" or "01".
When it receives, it operates as a preliminary synchronization control node.

[0011]

This type of loop-type data transmission device receives a reference clock from another network, for example, the same type of loop-type data transmission device, operates in a subordinate synchronization with the clock, and operates in different loops. There is a strong demand for a device capable of communicating between terminals housed in a portable data transmission device. However, since the conventional loop type data transmission apparatus is configured as described above, there is no means for inputting the reference clock from another network, so that there is a problem that it cannot be slave-synchronized with another network. there were.

The present invention has been made to solve the above problems, and a first object of the present invention is to provide a different loop type data transmission apparatus by subordinately synchronizing the loop type data transmission apparatus with another network. A loop-type loop-type data transmission device that enables communication between the accommodated terminals, and is normal when a reference clock is supplied to multiple nodes from another network device and there is an abnormality in the clock. To obtain a highly reliable loop type data transmission device capable of performing communication in synchronization with another clock.

A second object of the present invention is to obtain a loop type data transmission device in which the proxy switching control of the synchronous control does not malfunction due to a transmission error. A third object of the present invention is to obtain a loop type data transmission device which can inexpensively configure a network system and can moderate the complexity of the network system. A fourth object of the present invention is to obtain a loop type data transmission device which can easily test a node device and is excellent in maintainability.

[0014]

[Means for Solving the Problems]

(1) A loop data transmission device according to the present invention forms its own network in which a plurality of node devices are connected via a transmission line on a loop, and the node device receives a clock from another network. Clock generating means for generating a reference clock based on the received clock;
When an abnormality of the reference clock is detected, the synchronous control node is switched to operate as a subordinate synchronous node, and the subordinate synchronous node is provided with switching means for switching to operate as a synchronous control node, and one of the node devices is set as a synchronous control node. , Controlling synchronization of the own network with the reference clock generated by the clock generation means, enabling data transmission within the own network and with other networks,
When the synchronization control node detects an abnormality in the reference clock, the switching means switches from the synchronization control node to the operation of the subordinate synchronization node, and the subordinate synchronization node receiving the abnormality in the reference clock switches to the synchronization control node and automatically The reference clock generated by the clock generation means of the node device controls the synchronization of the own network, and enables data transmission within the own network and with other networks.

(2) Further, the signal to be transmitted is frame data to which a flag bit and a node number are added, and when the synchronous control node detects an abnormality in the clock transmitted from another network, the flag bit corresponding to this abnormality As a result, the node device that receives the frame data corresponding to this abnormality switches to the synchronous control node and transmits the frame data to which the flag at the normal time and the node number of the own node device are added. Is.

(3) Further, the frame data is frame data having a check bit for checking the flag bit and the node number, and the node device is provided with an error checking means by the check bit, and the node device receives the data. The frame data is subjected to an error check by the error check means, and the presence or absence of an abnormality in the reference clock is detected using a flag bit having no error and a node number.

(4) Further, the clock input from the other network to the clock generation means is such that the clock from the terminal device of the other network is introduced.

(5) Further, two clock inputs to the clock generating means, that is, a clock from another network and a clock from a terminal device of another network different from the other network are introduced into the own network. The other clock is selectively used according to the abnormality of one clock.

(6) Further, the node device is provided with a bypass means, a test signal generating means, and a checking means, and at the time of testing, switching is performed so as to bypass the transmission line connected to the node device by the bypass means. At the same time, the test signal transmitted from the test signal generating means is switched to be directly received, and the checking means checks the content of the received test signal to detect an abnormality in the node device.

[0020]

The loop type data transmission apparatus of the present invention forms its own network in which a plurality of node apparatuses are connected via a transmission line on a loop, and one of the node apparatuses is used as a synchronous control node to generate clock generation means. Performs synchronous control of its own network with the reference clock generated in, enabling data transmission within its own network and with other networks,
When the synchronization control node detects an abnormality in the reference clock, the switching means switches the operation from the synchronization control node to the operation of the subordinate synchronization node, and the subordinate synchronization node receiving the abnormality in the reference clock switches to the synchronization control node to switch its own node device. The synchronization control of the own network is performed by the reference clock generated by the clock generation means, and data transmission within the own network and with other networks is enabled.

(2) Further, the signal to be transmitted is frame data to which a flag bit and a node number are added, and when the synchronous control node detects an abnormality in the clock transmitted from another network, the flag bit corresponding to this abnormality. As a result, the node device that has received the frame data corresponding to this abnormality switches to the synchronous control node and transmits the frame data to which the normal flag and the node number of its own node device are added.

(3) Further, the frame data is frame data provided with a check bit for checking the flag bit and the node number, and the node device carries out an error test of the frame data received by the error checking means, and there is no error. The presence or absence of abnormality of the reference clock is detected using the flag bit and the node number.

(4) Further, for inputting the clock from the other network to the clock generating means, the clock from the terminal device of the other network is introduced.

(5) Further, two clock inputs, that is, a clock from another network to the clock generating means and a clock from a terminal device of another network different from the above other network are introduced into the own network. , The other clock is selectively used according to the abnormality of one clock.

(6) When testing the node device,
The bypass means switches to bypass the transmission path connected to the node device, and switches to directly receive the test signal transmitted from the test signal generating means, and the checking means checks the content of the received test signal to check the node. Detect an abnormality in the device.

[0026]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a loop data transmission device according to the present invention. In FIG. 1, the same reference numerals as those in FIG. 9 are the same or equivalent, and the description thereof will be omitted. Reference numerals 101 to 104 denote node devices according to the present invention, and 110 denotes another network device that supplies a reference clock to the loop data transmission device. The loop data transmission device operates in synchronization with the clock. The reference clock from the other network device 110 may be supplied to any node device, and
It may be supplied in multiples for redundancy. FIG. 1 shows, as an example, a configuration in which the node devices 101 and 102 are supplied.

FIG. 2 shows the format of the frame data transmitted in FIG. 1, which is composed of a frame synchronization signal, a data word, a check bit and a supervisory information word. The flag bit in the monitoring information word is a bit used for proxy switching control of synchronization control performed between each node device, and the node number is a number given to each node device to identify the node device. .

FIG. 3 shows the node devices 101 to 101 according to the present invention.
4 is a block diagram of 104, 31 is a clock input circuit that receives a reference clock from another network device 110, 32 is a transmission timing control circuit that generates each timing by the clock output from the clock input circuit 31, and 33 is a reception A switch for switching the timing signal from the timing control circuit 16 and the timing signal from the transmission timing control circuit 32, and 34 from the flag detection circuit 22, the frame synchronization detection circuit 23, the bit error detection circuit 24 and the clock input circuit 31. It is a switching control circuit that controls the switch 27 and the switch 33 according to each signal state. 35 has a node number for identifying a plurality of node devices existing in one loop type transmission device, and based on this node number and the switching state signal from the switching control circuit 34, the flag bit and node number in the frame data are It is a flag setting circuit for setting.

Next, the operation will be described. Node device 1
01 is inputting a clock from another network device 110 to the clock input circuit 31, detects an anomaly such as the presence or absence of a signal loss of the clock and whether or not the frequency deviation of the clock is within the regulation, and detects the detection signal. Is output to the switching control circuit 34, and a clock having a predetermined frequency is reproduced from the input clock and output to the transmission timing control circuit 32.

First, the operation when the detection signal of the clock input circuit 31 of the node device 101 indicates a normal state will be described. The switching control circuit 34 switches the switching device 2 so that the output signal of the loop synchronization control circuit 15 is input to the transmission control circuit 20.
7 and controls the switch 33 to input the output signal of the transmission timing control circuit 32 to the transmission control circuit 20 and others.

The flag setting circuit 35 sends the frame data in which the flag bit is set to "0" and the node number is set to the node number of the node device 101, for example, "1", to the node device 102 which is a lower node device.

In the node device 102, the frame synchronization detection circuit 23 detects the presence / absence of a synchronization signal and the bit error detection circuit 24 detects the presence / absence of a data error. If the frame data is normal from the detection results, The switching control condition is determined from the flag bit and the node number in the received frame data.

That is, when the flag detection circuit 22 detects the flag bit "0", it determines that there is a node device for which synchronous control is already operating, and further determines the node number in the frame data and the node number of its own node device. Compare. If the node number of the frame data transmitted from the node device 101 is “1” and the node number of the node device 102 is “2”, the node number in the frame data is small. Controlled not to.

Here, the switching control circuit 3 of the node device 102
As the operation of No. 4, the switch 33 is arranged so that the output signal of the reception timing control circuit 16 is input to the transmission control circuit 20 and others.
The switch 27 is controlled so that the output signal of the reception control circuit 14 is input to the transmission control circuit 20. Further, the flag setting circuit 35 controls the transmission control circuit 20 to relay the flag bit and the node number in the received frame data as they are.

As described above, the node device 101 operates as a node device that performs a synchronization control operation, and the node device 102 operates as a subordinate synchronization node that does not perform a synchronization control operation. In addition, the lower node devices 103 and 104
Are given node numbers “3” and “4”, respectively, and since the node numbers are larger than the node device 101, they operate as subordinate synchronization nodes similarly to the node device 102.

Next, the operation when the detection signal of the clock input circuit 31 of the node device 101 indicates an abnormal state will be described. The switching control circuit 34 switches the output signal of the reception control circuit 14 to the transmission control circuit 20 so that the switching device 27
The switch 33 is controlled so that the output signal of the reception timing control circuit 16 is input to the transmission control circuit 20 and the like. In the flag setting circuit 35, the flag bit is set to "1",
The frame data in which the node number is set to the node number of the node device 101, for example, “1” is sent to the node device 102 which is a lower node device.

In the node device 102, as in the case where the clock from the other network device is normal, when the frame data is normal, the switching control condition is set from the flag bit in the received frame data and the node number. decide. The flag detection circuit 22 does not compare the node numbers by detecting the flag bit "1", and the node device 102 is controlled to perform the synchronous control operation.

Here, the switching control circuit 3 of the node device 102
As the operation of No. 4, the switch 33 is operated so that the output signal of the transmission timing control circuit 32 is input to the transmission control circuit 20 and others.
And the switch 27 is controlled so that the output signal of the loop synchronization control circuit 15 is input to the transmission control circuit 20.

Further, the flag setting circuit 35 controls the transmission control circuit so as to set the flag bit in the frame data to "0" and the node number to "2" which is the node number of the node device 102.

As described above, the node device 101 operates as a subordinate synchronization node, and the node device 102 operates as a synchronization control node which performs a synchronization control operation. Further, "3" and "4" are given to the lower node devices 103 and 104 as node numbers, respectively, and since the node numbers are larger than the node device 102, they operate as subordinate synchronization nodes.

As described above, the reference clock is supplied from another network device to a plurality of node devices, and even if any of the clocks becomes abnormal, the loop type data transmission device is switched to the normal reference clock by switching to the normal reference clock. It can be slave-synchronized with other network devices.

In the above embodiment, the flag bits are "0" or "1" and the node numbers are "1" to "4", but this is also simplified for the purpose of making the explanation easy to understand. Similar operations are possible even if these identification methods are set to other values. Further, the configuration has been shown in which the clock is supplied from another network device to the node devices 101 and 102, but it may be supplied to another node device.

Further, it is possible to supply two or more clocks to one node device, detect an abnormal state of the clock in the node device, and select a normal side. By doing so, redundancy can be provided, and the reliability of the system can be improved.

FIG. 4 shows an example of the structure having this redundancy. In the figure, two clocks are input from other network devices to clock input circuits 31-1, 3 in the node device.
Input each into 1-2. Clock input circuit 31-
In 1 and 31-2, the normality of the input clock is checked, and the check result and the clock are output to the selection circuit 36, respectively. In the selection circuit 36, the normal clock (if both are normal, either 1) is selected and led to the transmission timing control circuit 32.

Further, the selection circuit 36 outputs two input clock states (either one is normal or both are abnormal) to the switching control circuit 34, and the switching control circuit 34 performs a switching operation according to the state of the input clock. I do. In this way, the clock can be duplicated and the reliability of the system can be improved.

Example 2. FIG. 5 shows another configuration example of the frame data format, in which a dedicated check bit is provided in order to perform an error test of a flag bit and node number relating to proxy switching control of synchronous control.

As a check bit, for example, CRC (Cyclic Redundancy Check) which is a typical error checking method is used.
Method) is added by the setting circuit 35 together with the flag bit and the node number, and the node device side which has received the frame data carries out the CRC verification in the flag detection circuit 22 to detect the error of the flag bit and the node number. To detect. Then, the flag bit and node number in which an error is detected are discarded as meaningless, and only the information that has been received normally without error is used as a proxy switching factor for synchronous control. The other operations of the node device are the same as in the case of the first embodiment, and will be omitted.

As described above, according to the present embodiment, even if a data error occurs during transmission, the proxy switching control of the synchronous control can be normally performed without malfunctioning.

Embodiment 3 FIG. FIG. 6 is another block diagram of the node device, showing the configurations of the node devices 114 and 116. The same reference numerals as those in FIG. 3 represent the same or corresponding parts, and the description thereof will be omitted. In the figure, reference numeral 41 is a clock generation circuit for generating a reference clock of the loop type transmission device based on a reception signal from the terminal transmission interface 21.

FIG. 7 shows an example of the configuration of a network to which the loop type transmission device constructed by using the node devices 114 and 116 according to this embodiment is applied.
14 and 116 have the same configuration and are shown in FIG. 6, and the node devices 101 to 103, 105, 107 and 108 are the same as those in FIG.

The loop-type data transmission device # 1 and the loop-type data transmission device # 2 are respectively supplied with clocks from the other network device 110 to the node device 101 and the node device 105, and in the node device 114 and the node device 116. Communication between the terminal accommodated in each node device of the loop type data transmission apparatus # 1 and the terminal accommodated in each node device of the loop type data transmission apparatus # 2, which are connected via the relay line 120. Is possible.

The trunk line 120 in FIG. 7 is the terminal receiving interface 17 and the terminal transmitting interface 2 in FIG.
Connected to 1.

The operation when the clock supplied from the other network device 110 to the node device 101 on the loop type data transmission device # 1 side becomes abnormal will be described below. The node device 101 operates as a subordinate synchronization node as in the first embodiment due to the abnormal clock, and the node devices 102 and 103 also operate as subordinate synchronization nodes because no clock is supplied. Although the node device 114 does not receive a clock from the other network device 110, the node device 114 includes the clock generation circuit 41.
Generates a reference clock from a signal from the terminal device and operates as a synchronous control node.

Since the loop-type data transmission device # 1 and the loop-type data transmission device # 2 are kept in synchronism, even if the clock supplied from the network device 110 becomes abnormal, the loop-type data transmission device # 1 It becomes possible to communicate between the terminal accommodated in each node device on the side and the terminal accommodated in each node device on the side of the loop data transmission device # 2.

In the above embodiment, the node device 114 is used.
Although an example in which one relay line is provided between the node device 116 and the node device 116 is shown, the node device of the present embodiment may be provided in addition to provide a relay line. For example, a relay line is provided between the node devices 103 and 107 to make it redundant and improve the reliability.

Further, one node device may be provided with two or more relay lines and selected. Eg 2
When duplicating with a relay line of a book, the node device 114,
Two terminal reception interfaces 17 and two terminal transmission interfaces 21 are provided in each of the 116, and are connected by a trunk line. Normally, one of the two trunk lines is used, and when it becomes abnormal, it is switched to the other. .

Even if there is no other network device 110, transmission may be performed using the trunk line 120. In this case, in order to further improve the reliability, the node device 103
6 and 107 may be replaced with the same configurations as the node devices 114 and 116 of FIG. 6 and connected by another relay line 120 to achieve duplication.

Example 4. FIG. 8 is a block diagram of a node device that enables a test of the node device to be carried out at the time of start-up or maintenance / inspection of the loop data transmission device.

In the figure, 51 is a bypass circuit, 52 is a switching control between normal operation and test operation of the node device,
A test control circuit for controlling the test mode at the time of test operation, 53 is a bypass control circuit for controlling the bypass circuit 51 at the time of node device failure or test setting, and 54 is a test such as a pseudo random pattern at test setting. A test data generation circuit for generating data, 55 is a terminal transmission data switching circuit for switching transmission data to be output to the transmission control circuit 20 during normal operation and test operation, and 56 is a test data check circuit.

Next, the operation during the test operation will be described.
During the test operation, the bypass control circuit 53 controls the bypass circuit 51 according to an instruction from the test control circuit 52, and SW1, SW2, and SW3 in the bypass circuit 51 operate so as to be connected on the solid line side. That is, the signal from the upper node device is bypassed and guided to the lower node device, while the transmission signal output from the transmission control circuit 20 of the node device being bypassed is returned in the bypass circuit 51 and received. 14 Guided to others.

The test control circuit 52 also controls the terminal transmission data switching circuit 55 to output the transmission data from the test data generation circuit 54 to the transmission control circuit 20. Further, the test control circuit 52 controls the terminal receiving interface 7 so that the folded data is not output to the terminal device side, and based on the check result of the test data check circuit 56, the means such as display and alarm is used. Notify maintenance personnel.

By switching the test mode of the test control circuit 52, the abnormal signal detected by the clock input circuit 31 is prohibited regardless of whether the reference clock is supplied from another network device. The switching control circuit 34 is controlled, and the clock uses the clock built in the transmission timing control circuit 32. Since the transmission and reception of the signal from the outside is blocked in this way, it is possible to perform the test at various places of the node device.

Therefore, with the node device bypassed, the node device can be tested whether or not the reference clock is supplied from another network device. An excellent device can be obtained.

[0064]

Since the present invention is constructed as described above, it has the following effects.

(1) By synchronizing the loop-type data transmission device with another network, it becomes possible to communicate between terminals accommodated in different loop-type data transmission devices, and if the clock is abnormal, Since the synchronization control node is switched to another node device, there is an effect that a reliable loop type data transmission device can be formed.

(2) Further, the signal to be transmitted is frame data to which a flag bit and a node number are added, and the proxy switching control of the synchronous control is performed according to the contents of the flag bit and the node number. Can be easily switched to another node device.

(3) Further, since the flag bit concerning the proxy switching control of the synchronous control and the check bit for performing the error verification of the node number are provided, the proxy switching control of the synchronous control is performed even if a data error occurs during transmission. The effect is to obtain a loop-type data transmission device that does not malfunction.

(4) Further, since the clock from the other network is input to the clock generating means, the clock from the terminal device of the other network is introduced.
There is an effect that the network of the loop type data transmission device can be constructed at a low cost and that the network becomes complicated.

(5) Further, two clock inputs to the clock generating means, that is, a clock from another network and a clock from a terminal device of another network different from the other network are introduced into the own network. Since it is used selectively, there is an effect that a reliable loop data transmission device can be formed.

(6) Since the node device is bypassed, the node device can be tested whether or not the reference clock is supplied from another network device. This has the effect of obtaining a loop-type data transmission device with excellent maintainability.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a loop data transmission device according to a first embodiment of the present invention.

FIG. 2 is a diagram of a format of frame data used in the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a node device according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a loop data transmission device according to a first embodiment of the present invention.

FIG. 5 is a diagram of a frame data format according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a node device according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a network according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a node device according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional loop data transmission device.

FIG. 10 is a diagram of a frame data format of a conventional loop data transmission device.

FIG. 11 is a configuration diagram of a conventional synchronization control node.

FIG. 12 is a configuration diagram of a conventional backup synchronization control node.

[Description of Reference Signs] 1 synchronization control node, 2 subordinate synchronization nodes, 3, 4 preliminary synchronization control nodes 5-8 terminal device, 9-12 bypass circuit, 13 loop transmission line, 14 reception control circuit, 15 loop synchronization control circuit, 16 reception timing control circuit, 17 terminal reception interface, 18 transmission timing control circuit, 1
9 flag setting circuit, 20 transmission control circuit, 21 terminal transmission interface, 22 flag detection circuit, 23 frame synchronization detection circuit, 24 bit error detection circuit, 2
5 OR circuit, 26 switching control circuit, 27 switching circuit,
31, 31-1, 31-2 Clock input circuit, 32
Transmission timing control circuit, 33 switching circuit, 34 switching control circuit, 35 flag setting circuit, 36 selection circuit, 4
1 clock generation circuit, 51 bypass circuit, 52 test control circuit, 53 bypass circuit, 54 test data generation circuit, 55 terminal transmission data switching circuit, 56 test data check circuit, 101-108 node device, 11
4, 116 node equipment, 110 other network equipment, 120 trunk lines.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04L 12/28

Claims (6)

[Claims] 1. A plurality of node devices form a self-network connected via a transmission line on a loop, the node device receives a clock from another network, and a reference clock is generated based on the received clock. Provided is a clock generating means for generating and a switching means for switching the synchronous control node to operate as a subordinate synchronous node when the abnormality of the reference clock is detected, and the subordinate synchronous node for switching to operate as a synchronous control node. One of them is a synchronization control node, which controls the synchronization of its own network with the reference clock generated by the clock generation means, enables data transmission within the own network and with other networks, and the synchronization control node causes an abnormality of the reference clock. Is detected, the switching means switches from the synchronization control node to the subordinate synchronization node. When the slave synchronization node receives the above abnormality of the reference clock and switches to the synchronization control node, the subordinate synchronization node performs synchronization control of its own network with the reference clock generated by the clock generation means of its own node device, and Loop type data transmission device characterized by enabling data transmission with other networks. 2. The signal according to claim 1, wherein the signal to be transmitted is frame data to which a flag bit and a node number are added, and when the synchronous control node detects an abnormality of a clock transmitted from another network, this abnormality is dealt with. The frame data is transmitted as a flag bit, and the node device that receives the frame data corresponding to this abnormality switches to the synchronous control node and transmits the frame data to which the flag at the normal time and the node number of the own node device are added. A loop-type data transmission device characterized in that 3. The frame data according to claim 2, wherein the frame data is frame data provided with a check bit for checking a flag bit and a node number, and the node device is provided with an error checking means based on the check bit. A loop type data transmission device characterized in that the received frame data is subjected to an error check by the error check means, and whether or not there is an abnormality in the reference clock is detected using a flag bit having no error and a node number. . 4. The method according to claim 1, wherein
A loop data transmission device, characterized in that a clock from a terminal device of the other network is introduced into a clock input from the other network to the clock generating means. 5. The method according to any one of claims 1 to 4,
Two clock inputs to the clock generation means, a clock from another network and a clock from a terminal device of another network different from the above-mentioned other network, are introduced into the own network, and if one clock is abnormal, A loop data transmission device characterized in that the other clock is selectively used. 6. The method according to any one of claims 1 to 5,
The node device is provided with a bypass means, a test signal generating means, and a checking means, and at the time of testing, the bypass means switches the transmission path connected to the node device so as to bypass the test signal generating means. A loop data transmission device, characterized in that the transmitted test signal is switched to be directly received, and the contents of the received test signal are checked by the checking means to detect an abnormality in the node device.