KR20010001368A - method and apparatus for duplexing implementation in ATM switching system link board - Google Patents

Abstract

PURPOSE: A device/method for implementing duplexing of a link board in an asynchronous transfer mode(ATM) exchange, is provided to configure link boards with chips having low consumption power and small sizes, and to increase the number of ports to eight per link board so as to duplex the link boards, so that duplexing signals are output to standby boards to switch ports when errors are generated on links. CONSTITUTION: A transmitting buffer(210) receives data switched in a switching board(100), and transmits the data to a transmitter(220). The transmitter(220) converts 20 bits parallel data from the switching board(100) into 3 bits parallel data in order to transmit the parallel data to a subscriber board(300), and transmits the converted parallel data to the subscriber board(300) by 3 bits. And the transmitter(220) transmits a transmitting clock from a clock driver(250) to the subscriber board(300). A receiver(230) converts the parallel data transmitted by 3 bits into 20 bits parallel data, and restores a receiving clock in a phase locked loop(PLL) to output the receiving clock to the clock driver(250). A receiving buffer(240) delivers the parallel data from the receiver(230) to a switching board(100). The clock driver(250) amplifies the transmitting clock from the switching board(100) to transmit the transmitting clock to the transmitter(220), and amplifies the receiving clock from the receiver(230) to transmit the receiving clock to a clock bus(260). The clock bus(260) transmits the receiving clock from the clock driver(250) to the switching board(100). A link duplexing controller(270) implemented with a programmable logic device(PLD) controls outputs of the receiving buffer(240) and the clock bus(260) based on the restored state of an error control signal and received clock. A subscriber board(300) also has a receiver(310), receiving buffer9320), transmitter(330), transmitting buffer(340), clock driver(350), clock bus(360) and link duplexing controller(370).

Description

Method and apparatus for duplexing implementation in ATM switching system link board}

The present invention relates to an apparatus and method for redundancy of an ATM switch link board. In particular, the link board is composed of a chip having low power consumption and a small size, thereby increasing the number of accommodating ports per link board to at least eight. By implementing a link board redundancy using a link board, the present invention relates to an apparatus and a method for implementing a redundancy link board of an ATM exchanger that outputs a redundancy signal to a standby board to switch ports when a problem occurs on a link. .

In general, the switching unit of the Asynchronous Transfer Mode (hereinafter, referred to as ATM) exchanger as shown in FIG. 1, the switching board 10 responsible for data switching and the switched data to the subscriber board 30 It consists of a link board 20 to transmit, the conventional link board 20 is a reception buffer 26, a transmission buffer 21, a parallel / serial conversion unit (Hardpackard's HDMP-1022) 22, all / Optical conversion section 23, serial / parallel conversion section (Hardpackard's HDMP-1024) 25, optical / pre conversion section 24 and clock driver 27.

In the above-described configuration, the transmission buffer 21 receives the data switched by the switching board 10 and transmits the data to the parallel / serial conversion unit 22, and the parallel / serial conversion unit 22 transmits the transmission buffer 21. 20-bit parallel data received from the switching board 10 through the conversion to the serial data for transmission to the subscriber board 30, the pre / optical conversion unit 23 is transmitted from the parallel / serial conversion unit 22 The received serial data is converted into an optical signal for transmission to the subscriber board 30 using an optical cable. In addition, the optical / electric converter 24 converts the optical signal received from the subscriber board 30 through the optical cable into an electrical signal and transmits it to the serial / parallel converter 25, and the serial / parallel converter 25 ) Converts the serial data received from the optical / electric converter 24 into 20-bit parallel data, and the reception buffer 26 converts the parallel data received from the serial / parallel converter 25 into the switching board 10. To pass. Here, the serial / parallel converter 25 also performs a function of restoring the received clock received from the subscriber board 30. The received clock recovered by the serial / parallel converter 25 is transferred by the clock driver 27. After being amplified, it is transmitted to the switching board 10.

The conventional link board 20 having the above-described configuration has a problem of a chip used as a parallel / serial converter and a serial / parallel converter, for example, a large amount of power consumption, heat generated during operation, and chip placement based on the size of the chip. Due to problems, the maximum number of ports (# 1 to # 4) and (# 5 to # 8) can be arranged as ports for accessing the subscriber board 30. Therefore, two link boards 20 are required to connect the eight subscriber boards 30 to the switching board 10.

In order to accurately transmit and receive data between the switching board 10 and the subscriber board 30, redundancy should be implemented. In the case of implementing redundancy using the conventional link board 20, the eight subscriber boards 30 In order to connect) to the switching board 10 in duplicate, four link boards 20 are required. However, due to the configuration of the conventional ATM switch, only two of the link boards 20 may be mounted, and thus, duplication of the link board and the port may not be realized.

In addition, the parallel / serial converter 22 and the serial / parallel converter 25 exchange a sink signal, which is an error control signal, and use an internal phase locked loop (hereinafter referred to as a PLL). In synchronizing with the clock phase, when the phase synchronization is normally performed and it is determined that there is no abnormality in the link, the serial / parallel conversion unit 25 performs the normal operation by making the locking signal active and performs phase synchronization. If it is determined that the link is not properly made or the link is abnormal, the locking signal is disabled to stop the operation. As described above, the conventional link board is a parallel / serial converter and a serial / parallel converter. Due to the problem of the chip used, redundancy cannot be implemented. Therefore, even if the synchronous signal is disabled and the operation stops, the redundancy cannot be changed. There is a problem that causes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and uses a small number of link boards by increasing the number of accommodating ports per link board to at least eight by configuring a link board with low power consumption and a small chip size. By implementing redundancy of the link board, it is possible to apply redundancy even without changing the structure of the conventional ATM switch. When a problem occurs on the link between the switching board and the subscriber board, the ATM switch outputs a redundancy signal to the standby board. It is an object of the present invention to provide an apparatus and method for implementing a redundancy of an ATM switch link board that can be switched.

1 is a diagram showing a configuration of a switching unit of an ATM switch.

2 is a diagram showing the overall configuration of an apparatus for implementing redundancy of an ATM switch link board according to the present invention;

3 is a timing diagram illustrating a sync bit and a clock applied to the present invention.

4 is a flowchart for explaining a method for implementing redundancy of an ATM switch link board according to the present invention;

*** Explanation of symbols for the main parts of the drawing ***

100. Switching board, 200. Link board,

210. Send buffer 220. Transmitter,

230. Receiver, 240. Receive buffer,

250. Clock driver 260. Clock Bus Section,

270. Link redundancy control unit, 300. Subscriber board

In another aspect of the present invention, there is provided an apparatus for dualizing an ATM switch link board, wherein the link board transfers data between a switching board for data switching and a plurality of subscriber boards. At least eight ports for connecting the subscriber board and redundant to operate the link board as an active board and a standby board; Each port of the link board includes transmitting and receiving means for transmitting and receiving data and a clock input and output between the switching board and the subscriber board; Clock processing means for processing a clock transmitted and received through the transmission and reception means; Link redundancy control means for monitoring the connection state and the sync state with the subscriber board, controlling the output enable of the transmission / reception means and the clock processing means by receiving a redundancy signal with the redundant link board and controlling redundancy switching. It is done by Further, the transmission and reception means includes a transmission buffer for temporarily receiving the parallel data switched by the switching board; A transmitter for converting the parallel data received from the transmission buffer into predetermined parallel data and transmitting the parallel data to the subscriber board in parallel, and transmitting the transmission clock received from the clock processing means to the subscriber board; A receiving unit converting parallel data received in parallel in a predetermined bit string from the subscriber board into parallel data and restoring a reception clock received from the subscriber board; And a receiving buffer which operates according to an output enable signal applied from the link redundancy control means and transmits parallel data received from the receiving unit to the switching board, and the clock processing means transmits an input received from the switching board. A clock driver for amplifying a clock and transmitting the clock to the transmitting and receiving means, and amplifying a received clock received from the transmitting and receiving means; And a clock bus unit configured to operate according to a clock enable signal applied from the link redundancy control unit to receive a clock received from the clock driver and transmit the received clock to the switching board. The link redundancy control means monitors a connection state, a sink state, and a restored state of a reception clock to control the output enable of the transmission / reception means and the clock processing means when at least one of the abnormalities occurs. Port redundancy is output to the standby board to perform port redundancy switching, and is implemented as a programmable logic device.

On the other hand, the redundant implementation method of the ATM switch link board of the present invention includes an active / standby board setting process of setting its own board as an active / standby board according to the mounted slot; Monitors the connection status, sink status, and recovery status of the received clock with the subscriber board, and controls the output of the receive buffer and clock bus to prevent abnormal data and clock from being input to the switching board when at least one of the errors occurs. A link redundancy switching process for outputting a redundancy signal to the board is provided. Further, the active / standby board setting process may include: determining whether the active / standby board is mounted in the active slot when the power is reset and the counter board is released. If the board is mounted in the active slot as a result of the determination, if the board is mounted in the active slot, and if the board is not mounted in the active slot, checking whether the board is mounted in the active slot after a predetermined time elapses. Wow; Setting a board as a standby board when the board is mounted in the active slot as a result of the checking, and setting a board as the active board when the board is not mounted in the active slot; And setting each port provided in the board set as the active board as an active port first, and the redundant switching process determines whether the cable connecting the subscriber board and the link board is normally connected. Steps; If the cable is not normally connected as a result of the determination, disabling the outputs of the reception buffer and the clock bus unit and outputting a redundancy signal to the standby board to duplicate the port; Determining whether there is a problem on the link when the cable is normally connected; If there is a problem on the link as a result of the determination, disabling the outputs of the reception buffer and the clock bus unit and outputting a redundancy signal to the standby board to duplicate the port; Determining whether the restored received clock is normal when there is no problem on the link as a result of the determination; And if the restored reception clock is not normal, disabling the outputs of the reception buffer and the clock bus unit, and outputting a redundant signal to the standby board. In addition, it is determined whether the cable connection is normal based on a predetermined bit value connected to a pull-up resistor, and whether there is a problem on the link is determined by whether a bit transmitted every time the clock divided by the subscriber board is raised. It is determined based on the received clock restored from the input until the next bit is input, and whether or not the restored received clock is normal is determined based on a reference clock provided inside the link board.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the apparatus and method for implementing the redundancy of the ATM switch link board according to a preferred embodiment of the present invention.

2 is a diagram showing the overall configuration of an apparatus for implementing redundancy of an ATM switch link board according to the present invention.

Prior to the description, a chip used as a transmitter and a receiver applied to a dual device of an ATM exchange link board according to the present invention has a lower power consumption, a lower price, and a smaller chip size than a conventional chip. Easy to deploy Therefore, eight ports # 0 to # 7 may be arranged in one link board 200. For this reason, in the present invention, two link boards may be mounted to implement redundancy. An active / stand-by board having eight ports is link-connected so that ports match one-to-one with a counterpart board. That is, the input / output of the port # 0 of the active board and the input / output of the port # 0 of the standby board are connected to each other, and the rest of the ports # 1 through # 7 are connected in the same manner.

As shown in FIG. 2, the apparatus for implementing redundancy of an ATM switch link board according to the present invention includes two link boards 200, and each link board 200 has eight ports (# 0 to # 7). Each port # 0 to # 7 includes a transmit buffer 210, a transmit unit (DS90CR215 manufactured by National Semiconductor) 220, a receive unit (DS90CR216A manufactured by National Semiconductor) 230, a receive buffer 240, The clock driver 250, the clock bus unit 260, and the link redundancy control unit 270 are provided.

In the above-described configuration, the transmission buffer 210 receives the data switched by the switching board 100 and transmits the data to the transmitter 220.

The transmitter 220 converts 20-bit parallel data received from the switching board 100 through the transmission buffer 210 into 3-bit parallel data in order to transmit the parallel data of 3 bits to the subscriber board 300. In addition to the parallel transmission by bit, the transmission clock input from the clock driver 250 is also transmitted to the subscriber board 300.

Receiving unit 230 converts the parallel data received in parallel by 3 bits from the subscriber board 300 into 20 bits of parallel data, and restores the received clock received with 3 bits of parallel data from the subscriber board 300 to clock Output to the driver 250, the recovery of the reception clock is performed in the PLL provided in the receiver 230.

The reception buffer 240 transfers the parallel data received from the receiver 230 to the switching board 100.

The clock driver 250 amplifies the transmission clock received from the switching board 100 to the transmission unit 220, amplifies the reception clock received from the reception unit 230, and then transmits the received clock to the clock bus unit 260.

The clock bus unit 260 transmits the received clock received from the clock driver 250 to the switching board 100.

The link redundancy control unit 270 is implemented as a programmable logic device (PLD), and controls the output of the reception buffer 240 and the clock bus unit 260 based on the error control signal and the restored state of the received clock, If an error occurs, the redundancy signal is output to the standby board so that the standby port becomes the active port. Here, the error control signal is used to monitor the connection-monitor-bit and the restored clock used to monitor whether the cable between the subscriber board 300 and the link board 200 is physically connected normally. The link redundancy control unit 270 attaches a pull-up register to connect the connection monitoring bit. Therefore, when the cable is normally connected, a low level signal is input to the link redundancy control unit 270, and when the cable is not normally connected, the high level signal is supplied to the link redundancy control unit 270. The signal is input.

The subscriber board 300 also has a receiver 310, a reception buffer 320, a transmitter 330, a transmission buffer 340, a clock driver 350, and a clock bus unit 360 similarly to the link board 200. And a link redundancy control unit 370, the operation of each block is similar to that of the subscriber board 300, so a detailed description thereof will be omitted.

3 is a timing diagram illustrating sync bits and a clock applied to the present invention. As shown in FIG. 3, (a) receives a received clock transmitted from the subscriber board 300 and received by the link board 200, and (b) sink signals from the subscriber board 300 to the link board 200. (C) is a sync bit transmitted to the link board 200 whenever the clock divided by 32 is divided by the link redundancy control unit 370 of the subscriber board 300. Indicates.

4 is a flowchart illustrating a duplex implementation method of an ATM switch link board according to the present invention. When power is supplied with two redundant boards in an ATM switch, the board mounted in the right slot becomes the active board, and the board mounted in the left slot becomes the standby board. . When only one board is mounted, the board becomes an active board regardless of the position of the slot in which the board is mounted.

When the power is supplied and its power reset is released, check whether the power reset of the partner board is released (S10). Here, it is possible to know whether or not the power supply reset of the counterpart board has been released based on the reset signal input from the counterpart board. When the reset signal input from the counterpart board is a low level signal, the power reset of the counterpart board is not released. When the reset signal input from the partner board is a high level signal, the power of the partner board is reset. As a result of the check of step S10, when the power reset of the counterpart board is released, it is determined whether it is mounted in the active slot (S12). Here, it can be known whether it is mounted in the active slot based on a signal (not shown) input from the back plane. If the signal input from the back plan is a low level signal, it is mounted in the active slot. If the input signal is a high level signal, it is mounted in the standby slot.

If it is determined in step S12 that the board is mounted in the active slot as the active board (S14), and if the board is not mounted in the active slot, that is, if it is mounted in the standby slot After a certain time, it is checked whether the board is mounted in the active slot (S16). Here, it is possible to know whether a board is mounted in an active slot based on a signal input from a board mounted in an active slot. If a board is not mounted in an active slot, a high level signal is inputted and a low level if a board is mounted. The signal of the level is input. If the board is mounted in the active slot as a result of the check of step S16, the board is set as a standby board (S18). If the board is not mounted in the active slot, the board is mounted in the standby slot. Even if it is, it is set as an active board (S14).

After that, each port of the active board is first set as an active port to enable the outputs of the reception buffer 240 and the clock bus unit 260 and enable each port of the standby board as a standby port. The output of the reception buffer and the clock bus unit are set to a disabled state (S20).

As described above, after the redundancy of the link board and the port is implemented, the data switched by the switching board 100 is transmitted to the subscriber board 300, and the data received from the subscriber board 300 is transferred to the switching board 100. To perform the original function of the link board 200 to be transmitted to (S22), 20 bits of parallel data output from the switching board 100 is transmitted to the transmitter 220 through the transmission buffer 210, 50MHz clock Is amplified by the clock driver 250 and transmitted to the transmitter 220 and the link redundancy controller 270. As described above, the 20-bit parallel data transmitted to the transmitter 220 is converted into 3-bit parallel data and then transmitted in parallel by 3 bits to the subscriber board 300, and the clock is also transmitted to the subscriber board 300 together. do. Here, the operating frequency of the clock is between 20 MHz and 60 MHz, and the link board 200 operates at 50 MHz.

On the other hand, the parallel data transmitted in parallel by the three bits from the transmitter 330 of the subscriber board 300 is input to the receiver 230 of the link board 200 is converted into parallel data of 20 bits and then the receiving buffer 240 The received clock inputted to the receiver 230 together with the parallel data is restored by the PLL installed inside the receiver 230 and then transmitted to the clock driver 250. The parallel transmitted to the receive buffer 240 is obtained. The data is transmitted to the switching board 100, the clock transmitted to the clock driver 250 is amplified to a predetermined size and transmitted to the switching board 100 through the clock bus unit 260 and at the same time the link redundancy control unit 270 Is also sent.

As described above, when the link board 200 transmits the data received from the subscriber board 300 to the switching board 100, it is necessary to control the normal data and the clock to be transferred to the switching board 100. Check whether the cable connecting the subscriber board 300 and the link board 200 is normally connected (S24). Here, it is known whether the cable connecting the subscriber board 300 and the link board 200 is normally connected based on the value of the connection monitoring bit inputted by a rising resistor, and the cable is disconnected or the subscriber board ( When the power supply is disconnected due to the removal of the 300, the access monitoring bit is input to the link board 200 at a high level. If the cable connecting the subscriber board 300 and the link board 200 is not normally connected, that is, when the connection monitoring bit is input at a high level, the link redundancy control unit 270 checks that the process S24 is performed. Immediately disables the outputs of the reception buffer 240 and the clock bus unit 260 to prevent abnormal data and clock from being input to the switching board 100 and to output a redundant signal to the standby board side The port becomes an active port (S26). Therefore, it becomes a standby port.

On the other hand, if the cable is normally connected to determine whether the sync bit received from the link redundancy control unit 370 of the subscriber board 300 is normal (S28). Here, whether or not the sync bit is normal is a link board since the link redundancy control unit 370 of the subscriber board 300 divides the clock transmitted to the link board 200 and sends a sync bit every time the 32-minute divided clock is increased. In the link redundancy control unit 270 of 200, the received reception clock is counted from the time when the sync bit is input until the next sync bit is input to determine whether the reception clock has been counted 32 times. If the number is greater than or less than 32, this indicates a problem with the link. If the sync bit is not normal, that is, if the counted number is greater than or less than 32, the output of the reception buffer 240 and the clock bus unit 260 is disabled, thereby causing abnormal data. At the same time, the clock is prevented from being input to the switching board 100 and a redundant signal is output to the standby board so that the standby port becomes the active port (S30).

On the other hand, if the sync bit is normal, that is, if there is no problem on the link, it is determined whether the received clock restored by the receiver 230 is normal (S32). Here, whether the restored reception clock is normal may be known based on a 50 MHz reference clock provided in the link board 200. The link redundancy control unit 270 receives the restored signal from the reception unit 230. After 256 divisions of the clock, a 256 division clock is used to count a 50 MHz reference clock. In other words, the reference clock is counted until the next clock is increased after the 256 division clock is raised. Since the receive clock is divided by 256, the reference clock is 256 times until the next clock is raised after the division clock is raised. Should be counted. Accordingly, if the number counted in one period is more or less than 256, it means that the clock recovery is wrong in the receiver 230. Here, since the switching board 100 allows an error of 1%, the reception clock should be between 49.75 MHz and 50.25 MHz. Accordingly, when the link redundancy control unit 270 determines whether the recovered clock signal is normal, the clock signal between 49.75 MHz and 50.25 MHz is received. If the counted number is more than 1 or less than 256, it is normal. To judge. However, if the number counted more than or less than 256 continues for a predetermined number of times, it is determined that the clock recovery is wrong. As a result of the determination in step S32, when the received clock restored by the receiver 230 is not normal, the outputs of the reception buffer 240 and the clock bus unit 260 are disabled to cause abnormal data and clocks to be switched. At the same time, the standby port becomes an active port by preventing a signal from being input to the 100 and outputting a redundant signal to the standby board side (S34).

The apparatus and method for implementing redundancy of the ATM switch link board of the present invention are not limited to the above-described embodiments and can be implemented in various modifications within the scope of the technical idea of the present invention.

According to the apparatus and method for redundancy of an ATM switch link board according to the present invention as described above, the link board is configured with a chip having a small power consumption and a small size to increase the number of accommodating ports per link board to at least eight. By implementing the redundancy of the link board by using a small number of link boards, the redundancy can be applied even if the structure of the conventional ATM switch is not changed. When a problem occurs on the link, the redundancy signal is output to the standby board to switch ports It can work. In addition, when a problem occurs on the link, redundant transfer of boards and ports can prevent abnormal data and clock signals from being input to the switching board. For this reason, there is an effect that can increase the reliability of the ATM exchange.

Claims (11)

An ATM switch having a switching board for switching data and a link board for transferring data between a plurality of subscriber boards, The link board has at least eight ports for connecting a subscriber board and is redundant to operate the link board as an active board and a standby board; Each port of the link board includes transmitting and receiving means for transmitting and receiving data and a clock input and output between the switching board and the subscriber board; Clock processing means for processing a clock transmitted and received through the transmission and reception means; Link redundancy control means for monitoring the connection state and the sync state with the subscriber board, controlling the output enable of the transmission / reception means and the clock processing means by receiving a redundancy signal with the redundant link board and controlling redundancy switching. Device for redundancy of the ATM switch link board, characterized in that made. The method of claim 1, wherein the transmitting and receiving means A transmission buffer for receiving and temporarily storing the parallel data switched by the switching board; A transmitter for converting the parallel data received from the transmission buffer into predetermined parallel data and transmitting the parallel data to the subscriber board in parallel, and transmitting the transmission clock received from the clock processing means to the subscriber board; A receiving unit converting parallel data received in parallel in a predetermined bit string from the subscriber board into parallel data and restoring a reception clock received from the subscriber board; And a receiving buffer which operates according to an output enable signal received from the link redundancy control means and transmits parallel data received from the receiver to the switching board. The method of claim 1, wherein the clock processing means A clock driver which amplifies the transmission clock received from the switching board and transmits the transmission clock to the transmission and reception means, and amplifies the reception clock received from the transmission and reception means; And a clock bus unit configured to operate according to a clock enable signal applied from the link redundancy control unit to receive a received clock from the clock driver and transmit the received clock to the switching board. . The method of claim 1, wherein the link redundancy control means By monitoring the connection state, the sink state, and the restored state of the reception clock with the subscriber board, when an error occurs in at least one of them, the output enable of the transmission / reception means and the clock processing means is controlled and a redundant signal is output to the standby board side. An apparatus for implementing redundancy of an ATM switch link board, characterized by performing port duplication switching function. 5. The apparatus of claim 4, wherein said link redundancy control means is implemented with a programmable logic element. An active / standby board setting process of setting a board as an active / standby board according to the mounted slot; Monitors the connection status, sink status, and recovery status of the received clock with the subscriber board, and controls the output of the receive buffer and clock bus to prevent abnormal data and clock from being input to the switching board when at least one of the errors occurs. 12. A method for implementing an ATM switch link redundancy comprising a link redundancy switching process for outputting redundancy signals to a board. The method of claim 6, wherein the active / standby board setup process is Determining whether it is mounted in the active slot when the power is reset and the power of the counter board is released; If the board is mounted in the active slot as a result of the determination, if the board is mounted in the active slot, and if the board is not mounted in the active slot, checking whether the board is mounted in the active slot after a predetermined time elapses. Wow; Setting the board as a standby board when the board is mounted in the active slot as a result of the checking, and setting the board as the active board when the board is not mounted in the active slot; And setting each port provided in the board set as the active board as an active port first. The method of claim 6, wherein the redundant transfer process Determining whether a cable connecting the subscriber board and the link board is normally connected; If the cable is not normally connected as a result of the determination, disabling the outputs of the reception buffer and the clock bus unit and outputting a redundancy signal to the standby board to duplicate the port; Determining whether there is a problem on the link when the cable is normally connected; If there is a problem on the link as a result of the determination, disabling the outputs of the reception buffer and the clock bus unit and outputting a redundancy signal to the standby board to duplicate the port; Determining whether the restored received clock is normal when there is no problem on the link as a result of the determination; And disabling the outputs of the reception buffer and clock bus unit and outputting a redundant signal to the standby board if the restored clock is not normal as a result of the determination. How to implement redundancy. 10. The method of claim 8, wherein the cable connection is determined based on a predetermined bit value connected to a pull-up resistor. 10. The method of claim 8, wherein whether or not there is a problem on the link is determined based on the received clock recovered from the input of the transmitted bit every time the divided clock is increased from the subscriber board until the next bit is input. Redundancy implementation method of the ATM switch link board, characterized in that. 10. The method of claim 8, wherein whether the recovered received clock is normal is determined based on a reference clock provided inside the link board.