KR100921597B1 - Apparatus and method for duplexing of serdes by using link chipset - Google Patents

Abstract

The present invention provides a sustained duplex apparatus and method using a link chipset, comprising: a link chipset configured to be duplexed to transmit and receive signals to and from the switching fabric; A transition detector which determines whether a transition between a primary and a redundancy occurs in the data received by the link chipset; When the transition detection unit detects a transition, the idle cell is configured to include a WSEN granting unit to the idle cell, so that the word synchronization for the efficient use of the link in the use of the sustain link for the transmission of ultra-high speed data idle cell By inserting in time, you can implement stabilization of the standby server.

Description

SUDES redundancy device using link chipset and its method {Apparatus and method for duplexing of serdes by using link chipset}

1 is a block diagram of a Sudden duplexing device using a conventional link chipset,

2 is a detailed block diagram of the VSC7216 chip in FIG.

3 is a timing diagram of FIG. 2,

4 is a flowchart showing a method for subduing a death using a conventional link chipset.

5 is a block diagram of a sustained duplexing device using a link chipset according to the present invention;

6 is a timing diagram of FIG. 5,

7 is a block diagram of a sustained duplication method using a link chipset according to the present invention.

Explanation of symbols on the main parts of the drawings

10: port card 20: A side switching fabric

30: B side switching fabric 40: link chipset (VSC7216)

41: K character output unit 42: selection unit

43: word alignment unit 50: network processor

60: switching chip 70: transition detector                 

80: idle cell WSEN accreditation part

The present invention relates to a serializer and deserializer (SERDES) redundancy apparatus using a link chipset, and a method thereof, and more particularly, to a word for efficient use of a link in the use of a sustained link for transmission of ultra-high speed data. The present invention relates to a sustained duplex apparatus and a method using a link chipset in which synchronization is inserted into idle cell time so as to be suitable for implementing stabilization of a standby sustain.

In general, sudes refers to a combination of a serializer / deserializer, which converts a parallel signal into a serial signal and also converts a serial signal into a parallel signal.

1 is a block diagram of a Sudden duplexing device using a conventional link chipset.

Where reference numeral 10 is a port card, 20 is a switch fabric on the A side, and 30 is a B side switching fabric.

Reference numeral 40 in the port card 10 is a link chipset composed of VSC7216 chips, and 50 is a network processor (NP).

In addition, reference numeral 60 in the switching fabric 20 and 30 on the A / B side is a switching chip performing an interface of 4 Gbps.                         

2 is a detailed block diagram of the VSC7216 chip in FIG. 1, and FIG. 3 is a timing diagram of FIG.

Reference numeral 41 is a K character output section, 42 is a selection section, and 43 is a word alignment section.

Therefore, the VSC7216 chip constituting the link chipset 40 will be described first.

In the VSC7216 chip, one port of 2.5G consists of four sustain signals, and each signal consists of +/- operating at 1.25GHz. Thus, the actual VSC7216 chip has four lines composed of the K character output unit 41, the selection unit 42, and the word alignment unit 43 in FIG.

The K character output unit 41 receives a data signal T [7: 0], a carrier detection signal C / D, and a word synchronization enable signal WSEN.

As shown in the timing diagram of FIG. 3, primary transmission data (PTX) and redundant transmission data (RTX) are output. These PTX and RTX is included in the K character is output. In the TX signal of FIG. 3, D1.0, D2.0, D3.0, and D4.0 denote general data, and K28.5 denotes a K character signal. The K character signal is a signal defined by international standards and means a specific bit value used for word synchronization.

The selector 42 receives the PTX and RTX signals from the K character output unit 41, selects one from the select signal (SEL), and outputs the received signal (Receive Data, RX).

Here, in the VSC7216 chip, the receiver has two sources of primary and redundant, and one of them is selected and processed internally.

In switch fabric 20, 30, the A side functions as a primary and the B side functions as a redundant. In addition, one of the receiving end of the VSC7216 chip in the A / B side switch fabric 20 and 30 functions as a primary and the other function as a redundancy and the VSC7216 in the A / B side switch fabric 20 and 30. One of the transmit ends of the chip functions as a primary and the other as a redundant.

In addition, the VSC7216 chip 40 in the port card 10 receives a signal from the A side switch fabric 20 among the receiving end functions as a primary, and a receiving end receiving a signal from the B side switch fabric 30 is redundant. Function as. The transmitting end transmitting a signal from the VSC7216 chip 40 in the port card 10 to the A side switch fabric 20 among the transmitting end functions as a primary, and the transmitting end transmitting the signal to the B side switch fabric 30 is redundant. Function.

Then, the word aligner 43 receives a signal of one of the PTX signal and the RTX signal selected by the selector 42 and performs word alignment to receive the data R [7: 0] and the idle cell IDLE and K. Character signals (K Character, KCH) and error signals (Error, ERR) are output.

Therefore, the word sync signal is a signal for word rearrangement of one port (2.5G) consisting of four sources, which rearranges the same when performing rearrangement due to transmission delay of each source. Will be That is, when the data enters the link chipset 40 of the VSC7216, the data starting point may not match, and the word alignment unit 43 performs word rearrangement by the WSEN signal.

When the word sync signal is applied outside the VSC7216 link chipset 40 by more than one clock of the reference clock, the word sync signal is generated within the link chipset 40 with a size of 16 clocks.

When the word sync signal is applied, K28.5 (special K character) is applied to the sustain signal.

At the receiving end, the word aligning unit 43 receives 16 K28.5 characters in each sudes to perform rearrangement.

Word sync is applied when a bit interleaved parity (BIP) error or a start of cell (SOC) error occurs on the sused.

4 is a flowchart illustrating a sustained duplication method using a conventional link chipset.

As shown therein, steps (ST11) (ST12) for determining whether a transition between the primary and the redundancy occurs during signal transmission and reception; When the transition occurs, applying WSEN to only the active side 20 of the switching fabric (ST13); A signal transceiving process is performed in the active side 20 of the switching fabric (ST14).

Referring to the operation of the prior art in detail as follows.                         

First, the port card receives 2.5G ports in A / B side switching fabric 20 and 30, respectively, and selects one of the two.

For example, assume that the A side switching fabric 20 is selected and operated in primary, and the B side switching fabric 30 is operated in redundant.

At this time, if the SOC error is detected by the C / D signal in the A side switching fabric 20 operating as the primary, WSEN (Word Sync Enable) is applied to two TX sustains, and the sustain word rearrangement is performed. The execution clears the SOC error.

The SOC error means that the position of the SOC is different due to the different transmission delays of the four sustain signals that constitute the 2.5G 1 port. In addition, WSEN realigns the SOC positions so that they have different SOC positions.

While the word sync of WSEN is applied, all of the user cells, which are T [7: 0] transmission data of FIG. 3, are ignored and lost.

However, this conventional technology has the following problems.

1) When an SOC error occurs in a receiving source port, user cell loss occurs because word synchronization is applied at two TX sources.

2) If the primary A side switching fabric 20 is selected in the port card 10, the port card 10 is fry when the B side switching fabric 30 acting as a redundant is mounted and then mounted. Since only looking at the head does not cause word synchronization to the redundant side B side switching fabric 30, this has caused a problem that the B side switching fabric 30 remains in an abnormal link state.

3) In the state of the above problem 2), if the redundancy of the B side switching fabric 30 in the port card 10 by hernia of the A side switching fabric 20 as the primary, the word again after port switching There is also a disadvantage in that a large amount of cell loss occurs due to the need to be motivated and rearranged.

4) Because port cards only rearrange with the switching fabric set as primary, there is a problem that SOC error continuously occurs on all links when mounting after mounting of switching fabric.

Accordingly, the present invention has been proposed to solve the above-mentioned general problems, and an object of the present invention is to provide word synchronization for efficient use of a link in idle cell time in the use of a sustain link for transmission of ultra-high speed data. The present invention provides a sudred duplexing device and a method using a link chipset capable of implementing stabilization of a standby sude.

In order to achieve the above object, the Sudden duplexing device using the link chipset according to an embodiment of the present invention,

A link chipset configured to be redundant to transmit and receive signals to and from the switching fabric; A transition detector determining whether a transition between a primary and a redundancy occurs in the data received by the link chipset; When the transition detection unit detects the transition is characterized in that the technical configuration consisting of the idle cell WSEN authorization unit for applying the WSEN to the idle cell.

In order to achieve the above object, the sustained duplication method using the link chipset according to an embodiment of the present invention,

A first step of determining whether a transition between the primary and the redundancy occurs during signal transmission and reception; If the transition occurs, adding a WSEN to an idle cell and applying it to a switching fabric; And a third step of performing transmission and reception processing at the primary / redundant side of the switching fabric after the second step.

Hereinafter, an embodiment according to the present invention as described above, a SUDES redundant device using a link chipset, and a method thereof will be described with reference to the accompanying drawings.

FIG. 5 is a block diagram of a sustained duplication apparatus using a link chipset according to the present invention, and FIG. 6 is a timing diagram of FIG.

As shown here, the link chipset 40 is configured with redundancy and transmits and receives signals to and from the switching fabric 20 and 30; A transition detecting unit (70) for determining whether a transition between a primary and a redundancy occurs in the data received by the link chipset (40); The transition detection unit 70 is configured to include an idle cell WSEN application unit 80 for applying a WSEN to the idle cell.                     

7 is a block diagram of a sustained duplication method using a link chipset according to the present invention.

As shown therein, a first step (ST21) (ST22) for determining whether a transition between the primary and the redundancy occurs during signal transmission and reception; A second step (ST23) of adding the WSEN to the idle cell and applying it to the switching fabric (20) (30) when the transition occurs; After the second step, a third step (ST24) of performing a transmission / reception process on the primary / redundant side of the switching fabrics 20 and 30 is performed.

Referring to the accompanying drawings, the operation of the sustained duplex apparatus and method using the link chipset according to the present invention configured as described in detail as follows.

First of all, in order to use the sustain link to efficiently use the link in the use of the sustain link for the transmission of ultra-high speed data.

Thus, the transition detector 70 detects a valid signal of the switching fabric so as to generate a word sync signal.

In order to make the primary / redundant selection, the status information of the switching fabrics 20 and 30 is sent to the port card 10, and the port card 10 is valid in the invalid state. By detecting a transition to a valid state, it is possible to apply word synchronization toward the switching fabric 20 and 30 at idle cell time.

In addition, the idle cell WSEN applier 80 generates and adds a word sync enable signal at idle cell time to allow the word sync signal to go to the switching fabric 20 and 30. That is, the word sync signal is not randomly applied when an SOC error occurs, but is sent at idle cell time.

Referring to the operation of the present invention in more detail as follows.

First, the configurations of the A side switching fabric 20 and the B side switch fabric 30 are the same as in the related art. However, the network processor portion of the port card 10 is greatly changed by adding the transition detector 70 and the idle cell WSEN authorization unit 80.

Thus, when the SOC error is detected at the receiving end of the link chipset 40, which can be configured as a VSC7216 chip in the port card 10, the word sync enable signal is randomly detected in the A / B side switch fabric 20. It applies only to the idle cell time, not the method of applying to the transmission data TX to be transmitted to (30).

Thus, the WSEN signal detects the fabric valid signal at the primary and redundant switching fabrics 20 and 30 and applies it at idle cell time when transitioned from invalid to valid.

The bandwidth of the Sustains link is 4 Gbps, the dual user cell is 3.125 Gbps including the additional header and 2.5G payload between the switching fabric 20 and 30 and the port card 30, and the rest is filled with idle cells.

Therefore, as shown in the timing diagram of FIG. 6, loss of user data can be prevented by applying word synchronization (16 clock cycles) to the idle cell time (18 clock cycles).

In FIG. 6, (a) time point shows that the fabric valid signal transitions from an invalid state to a valid state, (b) time point is a time point for generating a WSEN signal due to a transition of the fabric valid signal, and (c) time point The WSEN will run for 16 clock cycles. Therefore, the K character is applied to the idle cell for 16 clock cycles from time point (b) to time point (c).

In addition, assuming that primary port is selected in the port card 10, when the redundant is mounted after mounting, the port card 10 detects that the fabric valid signal outputted from the redundant transition from the invalid to the valid state. In this case, the word synchronization enable signal is applied to the transmission data at the idle cell time.

As such, the present invention implements stabilization of the standby mode by inserting word synchronization for efficient use of the link at idle cell time.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the sustained duplication apparatus and method using the link chipset according to the present invention has the following effects.

1) When an SOC error occurs in the reception source part, since word synchronization is applied at idle cell time in two transmission sources, user cell loss does not occur.

2) If the primary card is selected on the port card, after mounting the B side switching fabric and mounting, the port card looks only at the primary, but detects a valid signal that indicates the status of the redundancy and idle cell time. Since word sync is applied to the redundant side, the redundant side also has an effect of being in a link state in a normal state.

3) When redundancy is selected on a port card by primary hernia in the same state as in 2) of the effect, cell loss does not occur at all because there is no need to apply word sync again after port switching. do.

4) When mounting after switching the switching fabric, all sudes of the fabric mounted later will normally wait, and cell loss does not occur at all even when the standby fabric is unmounted. In the case of dual-active fabrics, the redundant fabrics must always be able to process the same data at the same time, and the port card must be able to transmit data normally, regardless of which of the two fabrics is selected.

Claims (2)

A link chipset configured to be redundant to transmit and receive signals to and from the switching fabric; A transition detector which determines whether a transition between a primary and a redundancy occurs in the data received by the link chipset; Sudes redundancy device using a link chipset, characterized in that configured to include a idle cell WSEN authorization unit for applying a WSEN to the idle cell when the transition is detected by the transition detector. A first step of determining whether a transition between the primary and the redundancy occurs during signal transmission and reception; If the transition occurs, adding a WSEN to an idle cell and applying it to a switching fabric; And a third step of performing a transmission / reception process at the primary / redundant side of the switching fabric after the second step.

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