KR20030047189A - Signal detection apparatus using PLD logic of loopback mode in ethernet linecard - Google Patents

Abstract

PURPOSE: An apparatus for detecting signals by a PLD(Program Logic Device) in a Loopback mode of an Ethernet line card is provided to perform the Loopback mode in an SERDES(Serialize/Deserialize) unit by performing a signal detecting function in the PLD when testing the Loopback mode between a network processor and the SERDES unit. CONSTITUTION: A network management processor(201) manages an OSI3(Open Systems Interconnection 3) layer. An SERDES unit(202) mutually changes a serial stream and a parallel stream. An optic module(203) interchanges an electric signal of the serial stream with an external optical signal. A CPU(204) outputs information for designating a Loopback mode assigned in a memory. A PLD(205) stores Loopback mode information by the CPU(204), and outputs a Loopback mode operating signal to the SERDES unit(202) so that the SERDES unit(202) performs a self looping test.

Description

Signal detection apparatus using PLD logic of loopback mode in ethernet linecard}

In the high-speed router system, in particular, when performing a loop back mode test between the network processor and the SERDES unit for system initialization or system verification of a Gigabit Ethernet Linecard, the signal detection function is applied to the PLD logic. The present invention relates to a signal detection apparatus using PLD logic in loopback mode in an Ethernet line card.

1 is a configuration of a gigabit Ethernet line card in the normal mode, Figure 2 is a configuration of a gigabit Ethernet line card in the loopback mode.

Referring to FIG. 1, a SERDES unit, which is a Gigabit Ethernet transceiver connecting a network processor 101 managing an OSI layer 3, an electrical serial interface of an optical module 101 and 10 bits of a physical layer, 102, an optical module 103 that exchanges internal and external optical signals, and manages each device of a line card, operates high level software, and exchanges data with a main processor card. It consists of a central processing unit (CPU) (104).

Referring to FIG. 2, the loop-up mode includes a pull-up resistor 105 for applying a high voltage to the signal detection pin of the network processor 101 for system initialization or system verification.

Referring to the accompanying drawings for the operation of the gigabit Ethernet line card as described above are as follows.

Referring to FIG. 1, the configuration of a Gigabit Ethernet Linecard includes a network processor 101, a serialize / deserlrize (SERDES) 102, an optical module 103, and a central processing unit 104. The network processor 101 manages three layers of open systems interconnection (OSI), and the SERDES unit 102 converts one gigabit serial stream and a 1.25 gigabit 10-bit stream to each other. That is, it is a gigabit Ethernet transceiver that connects the electrical serial interface of the optical module 103 with 10 bits of the physical layer.

The SERDES unit 102 converts the parallel stream transmitted from the network processor 101 into a serial stream and transmits the serial stream to the optical module 103. The serial stream transmitted from the optical module 103 is converted into a parallel stream and converted into a network. Transfer to processor 101.

The optical module 103 exchanges an internal electrical signal with an external optical signal, and a line card is connected to the outside through the optical module 103. The optical module 103 transmits an electrical signal transmitted through a serial stream as an optical signal through a line card connected to the outside, and transmits the optical signal transmitted through the line card as an electrical serial stream to the SERDES unit 102. Do it.

At this time, the optical module 103 informs the network processor 101 by setting a signal detect signal high ("1") when data is being transmitted from the transmission medium in the normal mode, and not during data transmission. At this time, the signal detection signal is set low (" 0 ") to inform the network processor 101.

The central processing unit 104 manages each device of the line card, operates high level software and exchanges data with the main processor card.

Most network physical layer chips include a loopback mode in which they receive parallel data sent for initialization or system verification. This is a function of allowing the serialized signal of the transmitter to be directly applied to the serially received data of the receiver by the EWRAP signal (that is, the signal that causes the loopback function to be driven) without passing through the driving circuit. Therefore, a function of looping back data between the network processor 101 and the SERDES section 102 is required.

To this end, when testing between the network processor 101 and the SERDES unit 102 in the loopback mode, the signal detection signal is driven high in the optical module 103 to indicate that data is being transmitted. At this time, since the external network is not connected, the signal detection signal of the optical module 103 cannot be driven “high”. Therefore, the pull-up resistor 105 is applied to the signal detection pin of the network processor 101 as shown in FIG. 2. Give and bind it "high."

However, since the network processor 101 of the conventional Gigabit Ethernet line card has to be self-tested without an external network connection between the SERDES unit 102 and the optical module 103 when testing in a loopback mode for system initialization or system verification. The signal detection signal cannot be driven "high" in the optical module 103.

To this end, when testing in the loopback mode, it is cumbersome to attach a pullup resistor 105 to the signal detection pin of the network processor 101.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and implements a signal detection function as a program logic device when testing a loopback mode between a network processor and a SERDES unit for system initialization or system verification of a Gigabit Ethernet line card. The purpose of the present invention is to provide a signal detection apparatus using the PLD logic in the loopback mode in an Ethernet line card that drives the E-lap signal required for loopback mode setting to enable the loopback mode in the SERDES section. have.

1 is a block diagram showing a signal detection apparatus of a normal mode in a conventional Ethernet line card.

Figure 2 is a block diagram showing a signal detection device of the loopback mode in a conventional Ethernet line card.

3 is a block diagram showing a signal detection apparatus using the PLD logic in the loop back mode in the Ethernet line card according to an embodiment of the present invention.

4 is a detailed configuration diagram of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

101,201 ... Network processor 102,202 ... SERDES part

103,203 ... optical module 104,204 ... CPU

105 ... Pull-up resistor 205 ... PLD section

In order to achieve the above object, in the Ethernet line card according to the present invention the signal detection apparatus using the PLD logic in the loopback mode,

A network management processor managing an OSI 3 layer;

A SERDES unit for converting serial streams and parallel streams;

An optical module for exchanging electrical signals of the serial stream and external optical signals;

A central processing unit which communicates with each of the units, manages and outputs information for designating a loopback mode allocated to a memory;

And a program logic device configured to store loopback mode information therein by the central processing unit, output a signal for driving the loopback mode to the SERDES unit, and perform the self-looping test in the SERDES unit.

Preferably, the network processor recognizes that the optical module is transmitting data by the high signal of the signal detection signal when operating in the normal mode, and detects the high level signal together with driving the loopback function signal of the program logic device in the loopback mode. The loopback function is performed by the signal.

Hereinafter, with reference to the accompanying drawings as follows.

3 is a configuration diagram of a signal detection apparatus using PLD logic in a loopback mode in an Ethernet line card, and FIG. 4 is a detailed configuration diagram of FIG. 3.

3 and 4, a network processor 201 that processes an OSI layer 3 and interfaces with an upper switching card, and a SERDES unit 202 converting a 1 gigabit serial stream and a 1.25 gigabit 10-bit parallel stream to each other. And an optical module 203 which is responsible for data transmission through a transmission medium and informs the network processor 201 whether data is to be transmitted, and information for communicating with, managing, and designating a loopback mode allocated to a memory. A central processing unit 204 for outputting a signal and storing the loopback mode information in a latch 215 therein and then outputting a signal for driving the loopback mode to the SERDES unit 202. And a program logic device (PLD) 205.

The signal detection apparatus using the PLD logic in the loopback mode in the Ethernet line card according to the embodiment of the present invention as described above with reference to the accompanying drawings as follows.

3 and 4, the configuration of the Gigabit Ethernet line card of the high speed router system includes a network processor 201, a SERDES unit 202, an optical module 203, a central processing unit 204, and a program logic device ( 205). The network processor 201 functions to process the OSI 3 layer and interfaces with the upper switching card.

The SERDES unit 202 is responsible for converting a serial stream of 1 Gigabit and a 10-bit parallel stream of 1.25 Gigabyte to each other. That is, the Gigabit Ethernet transceiver connects the electrical interface of the optical module 203 and 10 bits of the physical layer of the network processor 201.

The optical module 203 exchanges an electrical signal transmitted from the SERDES unit 202 and an external optical signal.

This line card is connected to the outside through the optical module 203.

The central processing unit 204 manages communication and each device between the line cards and exchanges data with the main processor card.

As shown in FIG. 4, the central processing unit 204 outputs data to a program logic device (PLD) 205 to designate a loopback mode stored in an internal memory. The central processing unit 204 Place the address on the address bus and the data on the data bus. The write signal is then activated and the chip select signal is output to the program logic device 205.

The program logic device 205 decodes the address, stores the data from the data bus in the internal latch 215, and inputs an escape signal to the SERDES unit 202.

Here, the E Lab signal is configured to operate in an initial normal mode simultaneously with the reset of the Gigabit Ethernet line card, and the SERDES unit 202 can perform the self looping test according to the set value when the E Lab signal is received from the program logic device 205. .

That is, the program logic device 205 enables the loopback mode to the SERDES unit 202, so that 10-bit data input under external control can be self-tested without going through an external network.

Further, when the test signal in the loopback mode is driven high, the program logic device 205 drives the signal detection signal high with the network processor 201, so that the network processor 201 transmits the optical module 203. Recognize that data is being sent through).

Meanwhile, when operating in the normal mode, the network processor 201 detects that the signal detection signal is driven high in the optical module 203 so that the transmission medium is sending data.

As such, in order to implement a loopback function that receives parallel data sent between the network processor 201 and the SERDES unit 202 for initialization or system verification of the line card in the Gigabit Ethernet line card, the program logic device 205 The multiplexer is implemented in the receiving section of the SERDES section 202 so that the Elab signal implemented in the SERDES section 202 is applied to the SERDES section 202 so that the serialized signal of the transmitting section is directly applied to the serial reception data of the receiving section without passing through the driving circuit. The loopback mode is enabled by the wrap signal of the logic device 205.

As described above, according to the signal detection apparatus using the PLD logic in the loopback mode in the Ethernet line card according to the present invention, the program logic device is provided with a loopback function required for initialization and device verification in the line card of the high-speed router system. By using it, the external processor can be connected without external connection for the verification of the network processor and the SERDES part during the self-test of the line card. When testing in the loopback mode, the signal logic of the optical module is implemented by the program logic device. There is no need to use a pullup resistor.

Claims (2)

A network management processor managing an OSI 3 layer; A SERDES unit for converting serial streams and parallel streams; An optical module for exchanging electrical signals of the serial stream and external optical signals; A central processing unit which communicates with each of the units, manages and outputs information for designating a loopback mode allocated to a memory; And a program logic device for storing loopback mode information therein by the central processing unit and outputting a signal for driving the loopback mode to the SERDES unit to perform a self-looping test in the SERDES unit. Signal detection device using PLD logic in loopback mode on the card. The method of claim 1, The network processor recognizes that the optical module is transmitting data by the high signal of the signal detection signal when operating in the normal mode, and operates the loopback function signal of the program logic device in response to the high level signal detection signal in the loopback mode. A signal detection apparatus using PLD logic in loopback mode in an Ethernet line card, characterized by performing a loopback function.