KR100440572B1 - A system for clock synchronization between switch boards with redundancy and line boards - Google Patents

Abstract

The present invention relates to a system for clock synchronization between a redundant switch board and a plurality of line connection boards.

In the system for clock synchronization of the present invention, two redundant switch boards are provided with a clock circuit unit for generating a synchronous clock, and a plurality of line connection boards are provided with a synchronous clock selector to control signal output from the switch board. Accordingly, the synchronization clock of the switch board in the active state is selected in each of the line connection boards, so that clock synchronization between the redundant switch board and each line connection board can be implemented. In addition, in the system for clock synchronization according to the present invention, by including the board for generating the clock in a switch board, the clock can be stably generated and the manufacturing cost of the system can be lowered.

Description

A SYSTEM FOR CLOCK SYNCHRONIZATION BETWEEN SWITCH BOARDS WITH REDUNDANCY AND LINE BOARDS}

The present invention relates to a clock synchronization device, and more particularly, to a system for clock synchronization between a switch board and a line connection board of a redundant structure.

In a system having a redundant switch board and a line connection board, for example, an Asynchronous Transfer Mode (ATM) switching system, clock synchronization between the switch board and the line connection board is required.

Conventionally, in order to provide a synchronous clock in a system, a clock generation and distribution board is separately provided to supply a synchronous clock to a switch board and a line connection board, and the clock generation board and the clock distribution board are connected to a cable or a wiring pattern in the board. The connection method is used. This known technology has been published in Korean Patent Publication No. 2000-41887 (published date: July 15, 2000). Hereinafter, the known technology will be described with reference to FIG. 1.

1 shows a circuit configuration of a conventional clock synchronizer.

As shown in FIG. 1, the conventional clock synchronizing apparatus includes a clock generation board 101 and two clock generation and distribution boards 102 and 103. The clock generation and distribution boards 102 and 103 may be integrated into one board or may be configured as separate boards connected to each other by a cable or a wiring pattern. In FIG. 1, the case of being integrated into one board is illustrated.

The clock generation board 101 generates a synchronization reference clock as an external synchronization reference clock input from the outside, and supplies the synchronization reference clock to the clock generation and distribution boards 102 and 103. The clock generation board 101 may include a clock generator therein to generate a synchronous reference clock using its own clock. The clock generation and distribution boards 102 and 103 generate a synchronous clock by using the synchronous reference clock and supply them to each switch board and the line connection board in common to achieve clock synchronization between the switch board and the line connection board. To help.

However, the conventional clock synchronizing apparatus described above has a problem in that the clock is not supplied to the switch board and the line connection board when a failure occurs in the clock generation block by being installed in a separate board form in the system. In addition, in the case of duplexing the switch board and the like, since a separate board for clock synchronization must be manufactured, there is a problem that the manufacturing cost of the system increases.

On the other hand, by configuring a clock generator on each board having a redundant structure, and by detecting the board when mounting or mounting the board, a method has been proposed to stably supply the clock even if the redundant board is mounted or mounted. . The prior art was disclosed in Korean Patent Publication No. 2000-32961 (published date: June 15, 2000). However, the above method has a problem in that only the hermetic or mounting of the board is focused, and the state of the board or an external command cannot be detected.

The present invention has been made under the technical background as described above, and in the system having a switch board having a redundant structure and a plurality of line connection boards connected to the switch board, the clock synchronization between the switch board and the line connection board can be implemented. It is an object to provide a system.

1 is a circuit diagram of a conventional clock synchronizer.

2 is a circuit diagram of a clock synchronizing apparatus according to the present invention;

3 is a detailed block diagram of the clock circuit shown in FIG. 2;

4 is a detailed configuration diagram of a synchronous clock selection unit shown in FIG. 2;

5 is a waveform diagram of the signals shown in FIG. 4;

(Explanation of symbols for the main parts of the drawing)

210, 220: switch board 230, 240: line connection board

211 and 221: switching unit 212 and 222: clock circuit unit

231, 241: Sync clock selector 232, 242: Matching function

The present invention for achieving the above object,

A system consisting of two redundant switch boards and a plurality of line connection boards for switching according to a switching signal,

Each switch board,

A switching unit which performs switching according to a switching signal, generates a control signal indicating a redundancy state by exchanging redundancy control signals between the switch boards, and outputs the generated control signals to the plurality of line connection boards; And

A clock circuit unit generating a synchronous clock corresponding to the number of the line connection boards by using a predetermined reference clock, and outputting the generated synchronous clocks to the plurality of line connection boards,

Each said line connection board,

A synchronous clock selection unit which receives a control signal and a synchronous clock from each of the two redundant switch boards, determines a control signal of each switch board, and selects a synchronous clock output from an active switch board; And

And a matching function unit performing line matching using the sync clock selected by the sync clock selecting unit.

According to the present invention described above, the control signal and the synchronous clock generated in the two redundant switch boards are respectively input to the plurality of line connection boards, the synchronous clock generated in the switch board active in accordance with the state of the control signal line By being used in the matching function of the connection board, clock synchronization between the switch board and the line connection board can be achieved. In addition, since a circuit having such a clock generation function is embedded in each of the redundant switch boards, the problem that the clock supply is stopped at the switch board and the line connection board due to the failure of the clock generation circuit can be solved. In addition, since a separate clock generation circuit does not need to be provided in the system, the manufacturing cost of the system can be lowered.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 shows a circuit configuration of the clock synchronizing apparatus according to the present invention.

As shown in FIG. 2, the clock synchronizing apparatus according to the present invention includes two switch boards 210 and 220 and N line connection boards 230 and 240. Each of the switch boards 210 and 220 includes a switching unit 211 and 221 and a clock circuit unit 212 and 222. Each of the line connection boards 230 and 240 may include a synchronous clock selector 231 and 241. Matching function units 232 and 242 are provided.

The external switching signal and the internal switching signal are input to each of the switching units 211 and 221, and a unique switching function is performed according to these signals. Although not shown in the drawings, each of the switching units 211 and 221 includes a circuit for controlling switching. The switch boards 210 and 220 exchange redundancy control signals with each other, and determine whether their board is an active board or a standby board according to the redundancy control signal. Also, when the external transfer signal and the internal transfer signal are input, the board state is determined according to a predetermined duplication algorithm. As the external switching signal, a switching signal input to an external processor may be used. As the internal transfer signal, a signal generated from a transfer switch (not shown) existing in the switch board may be used.

The clock circuits 212 and 222 provided in the switch boards 210 and 220 generate their own clocks required by the switch boards to which they belong and the synchronization clocks for the N line connection boards 230 and 240. In order to generate the various clocks as described above, the clock circuits 212 and 222 may receive a synchronization reference clock from the outside or may include an oscillator to generate a reference clock.

That is, in a system environment in which a synchronous reference clock is not input from the outside, an oscillator is provided in the clock circuit units 212 and 222 to generate a reference clock, and in a system environment in which the synchronous reference clock is input from the outside. Next, the reference clock is generated using the input external synchronization reference clock. In this embodiment, it is assumed that an external synchronization reference clock is input to each of the clock circuit units 212 and 222.

Each of the clock circuits 212 and 222 generates its own clock using the external synchronization reference clock and supplies it to the switching units 211 and 221 of the switch board to which it belongs. In addition, the clock circuits 212 and 222 generate synchronous clocks for the N line connection boards 230 and 240 by using the external synchronization reference clock, and generate the generated synchronous clocks to the line connection boards 230. , 240). The control signals and the synchronous clocks generated by the switching units 211 and 221 and the clock circuits 212 and 222 of the switch boards 210 and 220, respectively, are synchronized with the synchronous clock selector within the N line connection boards 230 and 240. 231, 241). Each of the synchronization clock selectors 231 and 241 determines an input control signal, selects an input synchronization clock from an active switch board, and supplies the selected synchronization clock to the matching function unit 232 or 242. do. By the structure as described above, it is possible to realize clock synchronization between each switch board and the line connection board without configuring a separate clock board in the system.

3 shows a detailed configuration of the clock circuits 212 and 222 shown in FIG. As shown in FIG. 3, the clock circuits 212 and 222 include a clock generator 301 and a clock distributor 302. As outlined above, the clock generator 301 generates a reference clock using an external synchronization reference clock inputted to synchronize from the outside or a clock generated through oscillation in itself. The reference clock generated by the clock generator 301 is provided to the clock distributor 302, and the clock distributor 302 generates its own clock using the reference clock, and generates the same self clock. Supply to the switch in the board. At the same time, the clock distributor 302 generates N sync clocks using the reference clock, and supplies the generated N sync clocks to the N line connection boards 230 and 240, respectively. The number of sync clocks output from the clock distributor 302 is equal to the number of matching devices (not shown) connected to the line connection board. That is, when the number of matching cards corresponding to the matching device is N, the number of sync clocks must be N.

4 illustrates a detailed configuration of the synchronous clock selectors 231 and 241 shown in FIG. As shown in FIG. 4, the synchronous clock selector includes a controller 401 and a selector 402. The control signal A and the control signal B are input to the controller 401, and the synchronization clock A and the synchronization clock B are input to the selector 402. The control signal A and the synchronous clock A are input from the switch board 210, and the control signal B and the synchronous clock B are input from the switch board 220. The control signal A and the control signal B indicate the state of each switch board. For example, a value of the control signal '1' indicates that the switch board outputting the control signal is active, and a value of the control signal '0' indicates that the switch board outputting the control signal is in a standby state. In this embodiment, since a structure in which two switch boards are dualized is used, when one of the control signal A and the control signal B is '1', the other becomes '0'. The control unit 401 determines the values of these signals and sends a synchronization clock selection signal to the selection unit 402. The synchronization clock selection signal is a synchronization clock output from the switch board in the active state. To be selected by. The selector 402 selects a corresponding one of the two synchronization clocks A and B according to the value of the input synchronization clock selection signal, and the selected synchronization clock is transmitted to the matching function unit in the line connection board.

5 shows a waveform of a signal applied to the circuit of FIG. 4.

More specifically, FIG. 5 shows control signals A and B input to the control unit 401 of FIG. 4, synchronous clocks A and B input to the selecting unit 402, and outputs from the selecting unit 402. The waveform of the sync clock is shown. As described above, since the switch board applied in the present invention has a redundant structure, each switch board has an active or standby state. At the same time, the redundancy algorithm does not allow both switchboards to be active or standby at the same time. If the control signal A is in an active state, it means that the switch board 210 is in an active state. In this case, it can be seen that the phase of the synchronous clock A and the phase of the synchronous clock coincide. Reference numeral 501 in FIG. 5 indicates this. In addition, when the control signal B is in an active state, it means that the switch board 220 is in an active state. In this case, it can be seen that the phase of the synchronous clock B coincides with the phase of the synchronous clock. Reference numeral 502 in FIG. 5 indicates this. Therefore, in either case, clock synchronization is performed between the switch board in the active state and each line connection board.

As described above, in the system of the present invention, two redundant switch boards include a clock circuit unit for generating a synchronous clock, and a plurality of line connection boards include a synchronous clock selector to control the output from the switch board. By synchronizing the synchronous clock of the switch board which is active according to the signal to each of the line connection boards, clock synchronization between the redundant switch board and each line connection board can be realized. In addition, in the system of the present invention, by including the switch board without a separate board for generating the clock, it is possible to stably generate the clock as well as to lower the manufacturing cost of the system.

Claims (6)

In a system composed of two redundant switch boards and a plurality of line connection boards for switching according to a switching signal, Each switch board, A switching unit which performs switching according to a switching signal, generates a control signal indicating a redundancy state by exchanging redundancy control signals between the switch boards, and outputs the generated control signals to the plurality of line connection boards; And A clock circuit unit generating a synchronous clock corresponding to the number of the line connection boards by using a predetermined external synchronization reference clock and outputting the generated synchronous clocks to the plurality of line connection boards, Each said line connection board, A synchronous clock selection unit which receives a control signal and a synchronous clock from each of the two redundant switch boards, determines a control signal of each switch board, and selects a synchronous clock output from an active switch board; And And a matching function for performing line matching using the synchronous clock selected by the synchronous clock selector. The method of claim 1, And said two redundant switch boards are in a standby state when one is active and the other is in a standby state. The method of claim 1, And the control signal indicates whether its switch board is active or in a standby state. The method of claim 1, The clock circuit unit A clock generator for generating and outputting a reference clock for generating a synchronous clock using the predetermined external synchronization reference clock or a clock oscillated by itself; And And a clock divider configured to generate a synchronous clock equal to the number of the line connection boards using the reference clock, and output the same number of synchronous clocks to each line connection board. The method according to claim 1 or 4, The sync clock selector A control unit for receiving a control signal and a synchronous clock from the two redundant switch boards and outputting a synchronous clock selection signal for selecting a synchronous clock output from an active switch board among the two switch boards from the state of the control signal; ; And And a selection unit for receiving a synchronous clock from the two redundant switch boards and selecting and outputting a corresponding synchronous clock according to the synchronous clock selection signal. System. The method of claim 5, A control signal output from each of the two redundant switch boards is configured such that when one indicates an active state and the other indicates a standby state, the clock synchronization between the redundant switch board and the line connection board is performed. System.