KR100257253B1 - Apparatus of network synchronization of pbx - Google Patents

Abstract

PURPOSE: A network synchronization apparatus of an exchanger is provided to be capable of generating system clock synchronized to a reference clock by adding only two kinds of circuit packs to one self. CONSTITUTION: A reference clock obtained from a relay device is provided to a system clock generator(200). A reference clock receipt and system clock distributer(100) distributes system clocks obtained from the system clock generator(200) into another devices of the exchanger. The system clock generator(200) generates the system clocks using the reference clock obtained from the reference clock receipt and system clock distributer(100) to feedback the reference clock to the reference clock receipt and system clock distributer(100).

Description

Switchgear device of exchanger

The present invention relates to a network synchronizer of a TDX-10 switch, and in particular, to minimize slip caused by a mismatch of clock frequencies during an exchange, a reference clock of an upper station exchange using a PAMS (Preassigned Alternate Master Slave) synchronization scheme. A network synchronizer device providing a system clock synchronized with the present invention is directed to a network synchronizer device having only two circuit packs in one shelf and enabling generation of a system clock synchronized with a reference clock.

As shown in FIG. 1, about 10 types of circuit packs are added to two shelves.

That is, the two-layer network synchronization reference clock board assembly 10 (NRCA) receives a reference clock obtained from two self-relay relay devices. The network synchronization control processor board assembly 20 (NCPA) performs a network synchronization control function. The master clock control board assembly 30 (MCCA) controls the master clock, and the local master clock generation board unit 40 (LMGU) controls the local master clock. Occurs. The master clock buffer board assembly 50 (MCBA) buffers the generated master clock, and the photoelectric conversion board 60 (electric to optic conversion daughter board (EOCD)) performs a photoelectric conversion function. do.

In addition, the optical clock distribution unit 70 (Optic Clock Distribution Unit: OCDU) serves to distribute the optical clock, the time of day clock & maintenance board unit (TDMU) Performs generation and maintenance of time and date clocks.

In addition to the circuit pack, a circuit pack as described below is further provided to form a single synchronizer device.

That is, a master clock generation back board (MGBB) in which three NCPA, MCCA, and LMGUs are mounted, and a master clock distribution back board in which two NRCA, MCBA, and EOCD are mounted, and one TDMU is mounted ( A Master clock Distribution Back Board (MDBB), a Time and Clock Daughter board (TDCD) included in the TDMU, a Synchronization Status Indication Daughter board (SSID) included in the LMGU, It is included in the LMGU and further includes a digital to analog conversion daughter board (DACD).

Therefore, since the network device of the conventional exchanger as described above is provided with more than 10 types of circuit packs in two shelves, the circuit configuration is complicated and the size of the device is relatively large.

Accordingly, the present invention has been proposed to solve the above problems of the conventional network synchronizer device, and an object of the present invention is to minimize the slip caused by a mismatch of clock frequencies during an exchange period. In a network synchronizer which provides a system clock synchronized with a reference clock of an upper station exchange using a synchronous method, only two circuit packs are provided in one shelf so that a system clock synchronized with the reference clock can be generated. It is to provide a network device.

In order to achieve the above object, the present invention receives a reference clock obtained from a relay line device and provides it to a system clock generator, and receives a reference clock for distributing the system clock obtained from the system clock generator and supplying it to another device of an exchange. And a system clock distributor; And a system clock generator for generating a system clock synchronized with the reference clock obtained by the reference clock receiver and the system clock distributor.

1 is a block diagram showing an embodiment of a network device of a conventional TDX-10 switch.

2 is a schematic configuration diagram showing an embodiment of a network synchronizer device of an exchange according to the present invention.

FIG. 3 is a block diagram illustrating an embodiment of a reference clock receiving and system clock distributor of FIG.

4 is a block diagram illustrating an embodiment of the system clock selector of FIG. 3.

FIG. 5 is a block diagram showing an embodiment of the fine phase difference detector of FIG.

FIG. 6 is a block diagram illustrating an embodiment of the system clock selection controller of FIG.

7 is a block diagram illustrating an embodiment of the system clock generator of FIG. 2.

* Explanation of symbols for main parts of the drawings

100, 100 ', 100 ": reference clock receiving and system clock distribution

110: reference clock receiver 120: system clock distribution unit

200, 200 ', 200 ": system clock generator

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above in detail.

2 is a block diagram showing an embodiment of a network synchronizer device of the exchanger according to the present invention.

As shown in the drawing, a reference clock obtained from the relay line device is received and provided to the system clock generator 200, and the system clock generators respectively distributed from the system clock generator 200 distribute the system clocks and supply them to other devices of the exchange. A system clock that generates a system clock as a reference clock obtained by the reception and system clock distribution unit 100 and the reference clock reception and system clock distribution unit 100 and feeds it back to the reference clock reception and system clock distribution unit 100. It is composed of a generator 200.

In this configuration, the network synchronizer includes two additional reference clock reception and system clock distribution units (100 ', 100 ") for triplexing, and two additional system clock generators (200', 200"). To implement a network device.

In the above, the reference clock receiving and system clock distribution unit 100, as shown in Figure 3, and receives the reference clock obtained from the relay line apparatus and provides the reference clock receiving unit 110 to the system clock generator 200 and ; It is composed of a system clock distribution unit 120 for distributing the system clock obtained from the system clock generator 200 to supply to other devices of the exchange.

The reference clock receiver 110 includes a reference clock monitor 111 that monitors a state of a reference clock of up to three lines received from the relay line device, and a reference clock state obtained by the reference clock monitor 111. A reference clock selector 112 for selecting one reference clock from among the three reference lines received and a slip detection reference clock selector for selecting a slip detection reference clock among the three reference lines. 113), the reference clock tripler 114 for controlling the triplet of the reference clock, and the reference clock selected by the reference clock selector 112 according to a control signal obtained from the reference clock triplet 114 A slip is detected from a reference clock buffer unit 115 to be transmitted to the system clock generator 200 and a reference clock selected by the slip detection reference clock selector 13 to be transferred to a higher processor. It consists chulbu 116.

In addition, the system clock distribution unit 120, the system clock monitoring unit 121 for monitoring the state of the three system clocks respectively obtained by the system clock generation unit 200, and the system clock monitoring unit 121 A system clock selector 122 for selecting one system clock among the three system clocks according to the generated state monitoring control signal, a fine phase difference detector 123 for detecting a fine phase difference between the three system clocks, and A system clock selection control unit 124 for generating a control signal for the system clock selection unit 122 to select one system clock, and a system clock distribution control unit 125 for controlling system clock distribution through communication with the upper processor; And buffers and outputs the system clock selected by the system clock selector 122 according to the distribution control signal generated by the system clock distribution controller 125. Consists of a system clock buffer unit 126, the system clock buffer unit 126, a system clock supply section (127) that the clock distribution in which a buffered system clock to the other of the exchanger is required in the device.

In addition, the system clock generator 200 selects one of a reference clock obtained from the reference clock receiving and system clock generator 100 and a reference clock obtained from another system clock generator, and selects the selected clock and the internal oscillation clock. A phase difference detection unit 201 for detecting a phase difference of the control unit; a control unit 202 for processing the phase difference detected by the phase difference detection unit 201 and controlling the overall operation of the system clock generator; and a system under control of the control unit 202 An interprocessor communication matching unit 203 providing an interprocessor communication path of the clock generation unit and a system clock generator 204 generating a system clock synchronized with the received reference clock according to the phase difference processing value obtained by the control unit 202. It consists of.

In addition, the system clock selector 122, as shown in FIG. 4, is a three-line ELC (Emitter Coupled Logic) obtained from three system clock generators 200, 200 ', and 200 " ECL / TTL converter 221 for converting a system clock into a TTL signal, and a control signal to select one system clock among three system clocks by receiving system clock status information from the system clock monitor 121. Selects one of a system clock obtained from the ECL / TTL converter 221 according to a system clock selection signal generated by the 3/1 selector 222 and a 3/1 selector 222 generating The clock selector 223 transfers the clock buffer unit 126.

In addition, as illustrated in FIG. 5, the fine phase difference detector 123 may include a phase difference between the first and second system clocks among the three system clocks obtained from the three system clock generators 200, 200 ′, and 200 ″. The first flip-flop 231 and the first exclusive logical sum device 234 to detect the first flip-flop 231 and the second exclusive logic sum device (234) and the second flip-flop 232 and the second exclusive logic sum device (detecting the phase difference between the first system clock and the third system clock) 235, and a third flip-flop 233 and a third exclusive logic element 236 for detecting a phase difference between the second system clock and the third system clock.

In addition, the system clock selection control unit 240 is configured to obtain a master code value (binary value indicating which system clock generation unit is the main system clock generation unit) respectively obtained from three system clock generation units 200, 200 ', and 200 ". First to third latches 241 to 243 for latching, first to third monitors 247 to 249 for monitoring whether the master code is transmitted, and first to third monitors 247 to 249. First to third registers 244 to 246 which output master code values obtained by the first to third latches 241 to 243 or output previous master code values according to signals obtained by And first and second address decoders 251 and 252 for generating a system clock selection signal by two or more matching signals among master code values obtained in the first to third registers 244 to 246, respectively.

Referring to the operation of the network device according to the invention configured as described above are as follows.

First, the network synchronizer according to the present invention includes three reference clock receiving and system clock distribution units 100, 100 ', 100 " and three system clock generators 200, 200', 200 " It consists of a self (backboard) for mounting the pack, wherein the reference clock receiving and system clock distribution unit (100, 100 ', 100 ") and the system clock generator (200, 200', 200") each composed of three Is to implement tripleization.

In the above, triplet means that there are three circuits or circuit packs that operate in the same manner and have the same physical structure. Compared with the redundant structure, the control method is somewhat difficult and complicated, but it is used to increase the reliability and safety. In particular, triplexing is one of the characteristics of the network synchronizer device and exists in devices requiring high reliability.

In other words, the three reference clock receiving and system clock distributors 100, 100 ', and 100 " monitor each other's status so that one of the preferred circuit packs becomes the main circuit pack according to the priority, and the other two The circuit pack becomes a sub-circuit pack, and the three system clock generators 200, 200 ', and 200 "also determine one main circuit pack and two sub-circuit packs through communication with each other.

Hereinafter, the operation of the reference clock receiving and system clock distribution unit 100 and the system clock generator 200 which are one main circuit pack selected above will be described.

First, the reference clock receiving unit 110 in the reference clock receiving and system clock distribution unit 100, as shown in FIG. The reference clock selection control signal is generated to the reference clock selector 112 so as to monitor the state of the received three-line reference clock and select the best reference clock as a result of the monitoring.

In the above, the best meaning is as follows.

The reference clock transmitted from the upper exchange is masked by the operator and is operated on the priority basis. If an abnormality occurs in the highest reference clock during operation, the highest reference clock is determined to be the lowest in the priority for a predetermined time (software designated, for example, 10 or 30 minutes). By this principle, the best means the clock having the highest priority by combining the priority determination by the operator and the clock state by the monitoring element (clock monitoring element).

Herein, the operation of the reference clock monitor 111 will be described in more detail.

In a state where the reference clocks of the three lines received through the relay apparatus are named REF0, REF1, and REF2, respectively, the reference clock may be set by the operator according to the priority of the upper switching station. That is, assuming that the good state of the input reference clock is determined first in the order of REF0, REF1, and REF2, the system is operated by first selecting the reference clock as REF0 according to the priority and operating the system. Although not shown, if a clock monitoring device (for example, TTL741s123), a capacitor, and a resistor in the reference clock monitoring unit 111 monitors the clock state of the highest priority, and is not satisfactory (2.048Mhz, 1.544Mhz clock 1). The clock error signal is transmitted to the reference clock triplexer 114 and the reference clock selector 112. Thereafter, the clock monitoring device of the reference clock monitoring unit 111 continuously performs clock monitoring, and when the state of the reference clock in which the failure occurs is good, the reference clock is changed again to the highest clock after the predetermined time. The clock change signal is transmitted to the triplexer 114 and the reference clock selector 112.

Then, the reference clock selector 112 selects one of the three-line reference clocks received from the relay device according to the reference clock monitoring result signal obtained from the reference clock monitoring unit 111 and transmits it to the reference clock buffer unit 115. do.

In addition, the reference clock triplexer 114 controls the tripleization of the reference clock through data communication with other reference clock receiving and system clock distribution units 100 'and 100 ", and the reference clock buffer 115 The reference clock (4 kHz) selected by the reference clock selector 112 is buffered and transmitted to the system clock generator 200 according to the triple control signal.

On the other hand, the sleep detection reference clock selector 113 selects one of the reference clocks of up to three lines received from the relay line device and transmits it to the sleep detector 116 for slip detection. In this case, the selected reference clock may be the same as or different from the reference clock selected by the reference clock selector 120. The two reference clocks may be the same or may be different on the other hand because they are commanded to set the reference clock for sleep detection from the upper processor.

The slip detection unit 116 detects a slip between the transferred slip detection reference clock and the system clock obtained from the system clock generator 200 and transfers the slip to the higher processor.

That is, the sleep detection unit 116 divides the reference clock selected for the sleep detection into an 8Khz reference clock, a comparison clock 8Khz which is divided into 12 system clocks in synchronization with the reference clock, and 4.096Mhz which divides the system clock 3 times. In comparison, slip is detected.

In more detail, sleep detection refers to a series of processes of counting the number of bits of the 4.096Mhz during the period from the falling edge of the 8Khz reference clock to the rising edge of the 8Khz comparison clock. In the sleep detection operation, when the upper processor transmits a sleep detection start command, a comparison clock of 8Khz obtained by synchronizing the reference clock once with the reference clock 8Khz as a synchronization signal is generated, and then at the falling edge of the 8Khz reference clock. It begins to count the comparison clock 4.096Mhz, and this counting operation continues to the rising edge of the comparison clock 8Khz. The sleep value is 8-bit data, and the initial value can be set to one of F8H to FDH according to the phase of the reference clock. If 512 bits are changed from this value, one sleep is generated and transferred to the upper processor. The comparison clock frequencies of 8Khz and 4.096Mhz are clocks divided by the system clock. In other words, the system clock is 32.768Mhz clock. If you divide it 3 times, it becomes 4.096Mhz, and if you divide this 4.096Mhz 9 times again, you can get the comparison clock 8Khz.

Next, the reference clock tripler 114 controls the tripleization of the reference clock through mutual monitoring with other reference clock receiving and system clock distribution units 100 'and 100 ", and the reference clock buffer unit 115. ) Buffers the reference clock (8Khz) selected by the reference clock selector 112 and transmits the buffered reference clock to the system clock generator 200. The system clock generator 200 is then transmitted. The reference clock generates a synchronized 32.768Mhz system clock through a phase locked loop (PLL).

That is, as shown in FIG. 7, the system clock generator 200 is obtained from a system clock generator that is different from the synchronization reference clock obtained by the phase difference detector 201 and the synchronization clock obtained by the system clock generator 100. One of the phase difference comparison clocks is selected, and the phase difference between the selected clock and the internal oscillation clock is detected and transmitted to the controller 202.

The control unit 202 generates a system clock generation control signal according to the detected phase difference and transmits it to the system clock generator 204. Accordingly, the system clock generator 204 generates a 32.768 MHz signal based on the system clock generation control signal. The system clock is generated and fed back to the reference clock receiving and system clock distribution unit 100. Here, the interprocessor synchronization matching unit 203 of FIG. 7 provides an interprocessor communication path of the triplexed system clock generator.

When the system clock is provided as described above, the system clock distribution unit 120 in the reference clock reception and system clock distribution unit 100 distributes the input system clock and provides the system clock to another device in the exchange.

That is, the system clock monitoring unit 121 in the system clock distribution unit 120 monitors the state of the three-line system clock generated at each system clock generation unit, and the monitoring result is monitored by the system clock selection unit 122. And the system clock distribution control unit 125. Here, the operation of the system clock monitor 121 is the same as the configuration and operation of the above-described reference clock monitor 111, and only whether the input clock is a reference clock (reference clock monitor) or a system clock (system clock monitor) Since only the difference of) is used, detailed description thereof will be omitted to avoid duplicate explanation.

Next, as illustrated in FIG. 6, the system clock selection control unit 124 periodically generates three system clock generators 200, 200 ′, and 200 ″ from the first to third latches 241 to 243. Latches and outputs the master code values sent to the first and third monitoring units 247 to 249 and monitors the three master codes and transmits the result values to the first to third registers 244 to 246. Maintain the previously latched master code value or store the changed master code value, that is, the first to third registers 244 to 246 are signals obtained by the first to third monitoring units 247 to 249, respectively. As a result, the master code values obtained from the first to third latches 241 to 243 are output or the previously stored master code values are output. Masks respectively obtained from the first to third registers 244 to 246 It generates a system clock signal selected by the at least two signal matching of the code values provided to the system clock selector (122).

The system clock selector 122 may select one of the three system clocks according to a state monitoring result value of the system clock obtained by the system clock monitor 121 and a system clock control signal obtained by the system clock select controller 124. The system clock is selected and transferred to the system clock buffer unit 126.

That is, as shown in FIG. 4, the system clock selector 122 selects three ECL system clocks obtained from the respective system clock generators 200, 200 ′, and 200 ″ by the ECL / TTL converter 221. The system clock monitor 121 monitors the three system clocks and transfers the corresponding control signals to the 3/1 selector 222 so that the best system clock is selected. Then, the 3/1 selector 222 transmits a system clock selection signal to the clock selector 223 so as to select a system clock corresponding to the control signal, and the clock selector 223 is connected to the system clock selection signal. Accordingly, the system clock corresponding to the system clock selection signal is selected from the three system clocks obtained by the ECL / TTL converter 221 and then worn out in the system clock buffer unit 126.

Then, the system clock buffer unit 126 buffers the transferred system clock to the system clock supply unit 127, and the system clock supply unit 127 supplies the buffered system clock to each device required by the exchange. Done.

Next, as illustrated in FIG. 5, the fine phase difference detection unit 230 generates system clocks generated by three system clock generators 200, 200 ′, and 200 ″ in the first flip-flop 231. Among clock 0, system clock 1, and system clock 2, the phase between system clock 0 and system clock 1 is detected quickly and late (PD1, PD2), and the first exclusive logical sum element 234 detects the system clock 0 and system clock. By exclusively ORing 1, it is detected whether a phase difference occurs (PD3).

In addition, the second flip-flop 232 detects the fast and late phases PD4 and PD5 of the phase between the system clock 0 and the system clock 2, and the system clock 0 and the system clock 2 are detected by the second exclusive logic element 235. The exclusive OR is used to detect whether the phase difference is generated PD6.

In addition, the third flip-flop 233 detects the fast and late phases PD7 and PD8 of the phase between the system clock 1 and the system clock 2, and the system clock 1 and the system clock 2 are detected by the third exclusive logic element 236. The exclusive OR is used to detect the occurrence of the phase difference PD9.

The detected fine phase difference is fed back to the system clock generator to control the constant voltage controlled oscillator (not shown) in the system clock generator to adjust the fast and slow phase of the system clocks. Let the phase difference adjustment function be performed.

This fine phase difference adjustment has a good duty cycle even when the clock of the same speed is input, even though the rising and polling times of the two clocks are different, even when the main clock is changed due to an error of one clock. Logic level "0" and logic level "1" are 50 to 50).

Here, the fine phase difference is a concept different from the general phase difference. In general, the phase difference refers to a difference in frequency, and the fine phase difference indicates leading and falling within the same frequency. For example, when two 10 MHz clocks are input identically, the logic level is "1" at the same time, and when the logic level is "0" at the same time, there is no phase difference and there is no fine phase difference. However, even if the same 10Mhz clock is input, when one clock such as 1ns or 10ns has a logic level of "1" or a logic level of "0" first, it can be seen that there is no phase difference but a fine phase difference occurs.

As described in detail above, the present invention can perform the same role as the conventional network synchronizer even in the state provided with only two circuit packs in one shelf, the existing 10 circuit packs in the two shelf Compared with the conventional manipulator device, which is constructed, the circuit configuration is easy, as well as the cost, and the device has a small volume, thereby making it compact.

Claims (8)

A network synchronizer that generates a system clock synchronized with a reference clock of an upper station exchange and distributes it to other devices of the exchange, wherein the reference clock obtained from the relay line device is provided in one circuit pack. A reference clock reception and system clock distribution unit for receiving and providing the system clock generation unit at a later stage, distributing the system clock obtained from the system clock generation unit and supplying the system clock to another device of the exchange; It is provided in the one circuit pack and the other circuit pack and is composed of three for triplet, including a system clock generator for generating a system clock synchronized with the reference clock obtained from the reference clock receiving and system clock distribution unit A network device of the exchanger, characterized in that configured. 2. The apparatus of claim 1, wherein the reference clock receiving and system clock distributing unit comprises: a reference clock receiving unit receiving a three-line reference clock obtained from the relay line device and providing the three-phase reference clock to the system clock generator; And a system clock distributor for distributing a system clock obtained from the system clock generator and supplying the system clock to another device of the exchange. The clock generator of claim 1, wherein the system clock generator selects one of a reference clock obtained from the reference clock receiver and a system clock generator and a reference clock obtained from another system clock generator and sets a phase difference between the selected clock and an internal oscillation clock. A phase difference detection unit for detecting a signal, a control unit for processing the phase difference detected by the phase difference detection unit, and controlling the overall operation of the system clock generator, and inter-processor communication matching for providing a communication path between processors under the control of the control unit. And a system clock generator for generating a system clock synchronized with the received reference clock according to the phase difference processing value obtained from the control unit. The apparatus of claim 3, wherein the reference clock receiving unit comprises: a reference clock monitoring unit for monitoring a state of a reference clock of up to three lines received from the relay line device, and three lines received according to the reference clock state obtained by the reference clock monitoring unit; A reference clock selector for selecting one of the reference clocks of the reference clock, a slip detection reference clock selector for selecting a slip detection reference clock among the received three-line reference clocks, and a tripled reference clock A reference clock buffer unit for buffering the reference clock selected by the reference clock selector according to a control signal obtained from the reference clock triplexer, and transmitting the buffered reference clock to the system clock generator; and the slip detection reference clock selector Slip detection unit for detecting the slip from the reference clock selected in the transfer to the upper processor characterized in that Is the exchanger device of the exchanger. 4. The system clock distribution unit of claim 3, wherein the system clock distribution unit comprises: a system clock monitoring unit for monitoring the states of three system clocks respectively obtained by the system clock generation unit; and the system clock distribution unit according to the state monitoring control signal generated by the system clock monitoring unit. A system clock selector for selecting one system clock among three system clocks, a fine phase difference detector for detecting a fine phase difference between the three system clocks, and a system clock selector for generating a control signal to select one system clock Buffers a system clock selection control unit, a system clock distribution control unit for controlling system clock distribution through communication with the upper processor, and a system clock selected by the system clock selection unit according to a distribution control signal generated by the system clock distribution control unit. And a system clock buffer section for outputting the Network system clock synchronization device of the exchange of another buffered system clock from the exchange apparatus, characterized in that the buffer unit is configured to supply the system clock which distributes the clock as needed. The ECL / TTL converter of claim 5, wherein the system clock selector comprises: an ECL / TTL converter converting a three-line ECL (Emitter Coupled Logic) system clock obtained from three system clock generators constituting a network synchronizer into a TTL signal; A 3/1 selector for generating a control signal to receive a system clock state information from the system clock monitor and to select one system clock among three line system clocks, and a system clock selected from the 3/1 selector And a clock selector configured to select one of the system clocks obtained from the ECL / TTL converter according to the signal and transmit the selected system clock to the system clock buffer. 6. The apparatus of claim 5, wherein the fine phase difference detector comprises: a first flip-flop and a first exclusive logical sum device for detecting a phase difference between first and second system clocks among three system clocks obtained from three system clock generators; A second flip-flop and a second exclusive logic sum to detect a phase difference between the first system clock and a third system clock, and a third flip-flop and a third exclusive logic sum to detect a phase difference between the second system clock and the third system clock. An exchanger device of an exchanger, comprising: an element. 6. The system of claim 5, wherein the system clock selection control section comprises: first to third latches for latching master code values respectively obtained from three system clock generation sections, and first to third monitoring whether the master code is transmitted. A first to third registers outputting master code values obtained from the first to third latches or outputting previous master code values according to a monitoring unit and signals obtained from the first to third monitoring units, respectively; And first and second address decoders for generating a system clock selection signal by two or more identical signals among master code values obtained in the first to third registers, respectively.

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