KR0180669B1 - Full electronic switching system network synchronization apparatus - Google Patents

Abstract

The present invention relates to an electro-exchanger network synchronizer device, in the construction of the electro-exchanger network synchronizer device, firstly, the phase difference control of the auxiliary clock generator uses the phase difference data of the main clock and the self-oscillating clock. The problem of the auxiliary clock part that occurred at the same time is that if the auxiliary clock generator uses the phase difference between the phase difference comparison clock and the self-oscillating clock received from the main clock generator as the phase difference control data, the auxiliary clock generator is used. It is solved because it is not affected by the main clock generator. Secondly, the system becomes unstable when the main clock is bad because the clock divider supplies the system using only the main clock of the clock generator. Take the basic clock from the generator of the clock, multiply and divide the system By the supply would one ever solved.

Description

Electronic switchgear device

1 is a functional block diagram of a conventional electronic switching device network device.

2 is a functional block diagram of a phase difference measuring unit of a conventional clock generation unit.

3 is a functional block diagram of a phase difference measuring unit of the clock generation unit of the present invention.

4 is a basic clock selection function block diagram of the clock distribution unit of the present invention.

5 is a functional block diagram of a redundant control unit of the clock distribution unit of the present invention.

* Explanation of symbols for main parts of the drawings

10A, 10B: clock receiver 20A, 20B, 20C: clock generator

30A, 30B: Clock divider 40A, 40B: All / optical divider

50A, 50B: central data link unit 60: space switch

21,22: phase difference comparison clock 23: self-oscillating clock

24, 25: phase difference measuring unit 26: common memory

27: microprocessor 31A, 31B: clock state monitoring unit

32A, 32B: basic clock generator 33A, 33B: redundant controller

34A, 34B: Basic clock selector 35: Back board

The present invention relates to an all-electronic switch network device, and in particular, when the main clock is bad due to a failure of the main clock device of the device, the method of using a phase difference comparison clock for improving the reliability of the auxiliary clock generator for improving the reliability and clocking An electro-exchanger network synchronizer device for improving the basic clock selection of the distribution part.

The functional block of the commonly used all-electronic exchanger synchronizer device is a clock receiver 10A which receives a synchronization reference clock (2.048 MHz) from outside and generates a phase difference comparison clock (4KHz) as shown in FIG. , 10B); Clock generators 20A, 20B, and 20C which generate a basic clock (32.768 MHz) by synchronizing the clock of the self-oscillator with the phase difference comparison clocks of the clock receivers 10A and 10B; The best one of the three clocks received from the clock generators 20A, 20B, and 20C is selected, multiplied by 65.536 MHz, and then divided and converted to light by the pre / optical converters 40A and 40B. It is composed of a clock distribution unit 30A, 30B, which is supplied to the central data link unit 50A, 50B in the exchanger, multiplied by 16.384 MHz, and then redundantly provided as a block for supplying the required clock to the space switches 60A, 60B. .

Here, the clock generators 20A, 20B, and 20C are tripled and operated in a main-auxiliary manner. The main clock generator 20A synchronizes its oscillation clock (32.768 MHz) with the phase difference comparison clock (4KHz) received from the clock receiver 10A, divides it, and compares the phase difference to the auxiliary clock generators 20B and 20C. Supply the clock. On the other hand, as shown in FIG. 2, the auxiliary clock generators 20B and 20C perform a phase difference between the phase difference comparison clocks (4KHz, 21) and the self-oscillating clocks (32.768MHz, 23) received from the main clock generator 20A for every 250usec. The part which measures and stores in the common memory 26, 512 phase difference data is read from the common memory 26 by the microprocessor 27 every 128 msec, and monitors the state of a main clock, and utilizes the data for phase control, and a clock receiver. The phase difference between the phase difference comparison clocks (4KHz, 22) and the self-oscillating clocks (32.768MHz, 23) received from 10A is read by the microprocessor 27 every 1.024 sec, and used as phase control data. On the other hand, if the state of the main clock is bad, one of the two auxiliary clock generators becomes the main clock generator 20A, and the previous main clock generator 20A becomes the auxiliary clock generators 20B and 20C, and the clock divider 30A, 30B) is redundant, multiplies the clock (32.768MHz) of the main clock generator 20A to make 65.536MHz, and divides it and supplies it to the central data link 50A, 50B and the space switch 60A, 60B. do.

However, in the conventional all-electronic exchanger synchronizer device configured as described above, the phase difference comparison clock (4KHz) and the self-oscillation clock (32.768) of the main clock generator 20A when the phase difference control of the auxiliary clock generators 20B and 20C are performed. Since the phase difference from the (MHz) is used, when the clock state of the main clock generator 20A is bad or an abnormality occurs in the main clock generator 20A, the auxiliary clock generators 20B and 20C are affected. Therefore, the system basic clock becomes worse until another auxiliary clock generator becomes the main clock generator by the triple operation, and the system becomes unstable.

In addition, the clock dividers 30A and 30B supply the system using only the main clocks of the clock generators 20A, 20B, and 20C. When the main clock is in a bad state, the clock dividers 30A and 30B are duplicated. Even when the central data links 50A and 50B and the space switches 60A and 60B are clocked in redundancy, the system becomes unstable.

The present invention is to solve the above problems, firstly, since the phase difference control of the auxiliary clock generator using the phase difference data of the main clock and the self-oscillating clock, the problem of the auxiliary clock portion that occurred at the same time when the main clock generator is abnormal, If the sub-clock generator uses the phase difference comparison clock received from the main clock generator and the phase difference between the self-oscillating clock as the phase difference control data and the main clock status monitoring, the sub-clock generator is not affected by the main clock generator. Second, the system becomes unstable when the main clock is bad due to the system using only the main clock of the clock generator in the clock divider. The problem is that the redundant clock dividers receive the basic clocks from different clock generators and multiply them. This is solved by dispensing and supplying the system.

Hereinafter, with reference to the drawings in detail, the same function as the same reference numerals used the same symbols.

3 is a functional block diagram of the phase difference measuring unit of the improved clock generators 20A, 20B, and 20C. The phase difference comparison clocks (4KHz, 21) and the self-oscillating clock (32.768MHz) provided by the main clock generator 20A are shown in FIG. A first phase difference measuring unit 24 measuring the phase difference of 23; A second phase difference measuring unit 25 for measuring a phase difference between the phase difference comparison clocks 4KHz and 22 provided by the synchronous clock receiving unit 10A and the self-oscillating clock (32.768MHz); The microprocessor 27 is configured to monitor the state of the main clock generator 20A by directly reading the phase difference data from the phase difference measuring unit 25 without passing through the common memory.

In the phase difference measurer of the improved clock generators 20A, 20B, and 20C configured as described above, the microprocessor 27 reads phase difference data directly from the first phase difference measurer 24 every 256 msec without passing through the common memory. Monitor the status of the main clock. If an error occurs in the clock receivers 10A and 10B, the phase difference between the phase difference comparison clock (4KHz) and the self-oscillating clock (32.768MHz) received by the auxiliary clock generators 20B and 20C from the main clock generator 20A. Is used as the main clock generator monitoring data and phase difference control data. In addition, the phase difference is read from the second phase difference measuring unit 25 every 1.024 sec and used as data for phase difference control.

4 is a basic clock selection function block diagram of the clock dividers 30A and 30B. The three basic clocks provided by the clock generators 20A, 20B and 20C are monitored and the state is monitored. Output clock state monitoring units 31A and 31B; Basic clock selection address generators 32A and 32B for selecting and outputting two basic clock addresses that are normal among clocks output from the clock state monitoring units 31A and 31B; A redundancy control unit (33A, 33B) for selecting only one of the two addresses output from the basic clock selection address generator (31A, 31B) and outputting it to the basic clock selection unit (34A, 34B); Of the three basic clocks provided by the clock generators 20A, 20B, and 20C, the clocks of the addresses output from the redundant control units 33A and 33B are output, multiplied, divided and supplied to the central data and the space switch. It consists of sections 34A and 34B.

The logical structures of the basic clock selection address generators 32A and 32B are shown in the truth table of Table 1.

As you can see from the table, if all three basic clocks are normal, the clock selection outputs the address that keeps the past clock selection.If only one of the three basic clocks is in a bad state, the bad clock among the previous clocks is changed to normal. The address is changed to the clock.If all the selected clocks are normal, the clock is kept. If two of the three clocks are bad, only the normal clock is output. If all clocks are bad, output any of three clock addresses.

In the table above, (a) Basic clock status: Good-1, Bad-0

(B) Base address of address: A-00, B-01, C-10

(C) x: any value between 1 and 0

(D) Outputs X1 (t + 1), for conditions other than those of inputs A, B, C, X1 (t), X2 (t), Y1 (t), and Y2 (t) shown in the truth table above. The values of X2 (t + 1), Y1 (t + 1), and Y2 (t + 1) are arbitrary values.

5 is a functional block diagram of the redundancy control units 33A and 33B of the clock divider, and inputs two clock addresses X1, X2; Y1 and Y2 output from the basic clock selection address generator 32A, respectively. First three-phase buffer sections 33-1A and 33-2A for always selecting one clock address X1, X2 as the address of the basic clock selection section by a connected enable terminal; Input two clock addresses (X1, X2; Y1, Y2) output from the basic clock selection address generator 32B, respectively, and always enable one clock address (Y1, Y2) by the enable terminal connected low. The second three-phase buffer sections 33-1B and 33-2B are selected to be selected by the address of the basic clock selection section.

In the redundant control units 33A and 33B configured as described above, the clock distribution unit 30A always drives X1 and X2 because the enable terminal connected to the high drives the first three-phase buffer 33-1A having the non-invert enable terminal. The clock selector 34A is selected to be the address of the clock selector 34A, whereas the clock divider 30B has a second three-phase having an enable enable terminal because the enable terminal is connected to the low side of the clock divider 30B through the back board. Since the buffer 33-2B is driven, Y1 and Y2 are always selected as the address of the clock selector 34B. In addition, since the enable terminal is connected through the back board 35, the shapes of the clock distribution units 30A and 30B are the same, and the function thereof is only changed according to the position on the back board.

As described in detail above, the present invention first uses the phase difference data of the main clock and the self-oscillating clock to control the phase difference of the auxiliary clock generator. If the phase difference between the phase difference comparison clock and the self-oscillating clock received from the additional main clock generator is used as the phase difference control data and the main clock status monitoring is used, the secondary clock generator is not affected by the main clock generator and is solved. The system becomes unstable when the main clock is bad because the distribution unit supplies the system using only the main clock of the clock generator. The problem is that the redundant clock distribution unit multiplies and divides the base clock from the generators of different clocks. Solved by supplying

Claims (3)

Clock receivers 10A and 10B which receive a synchronization reference clock (2.048 MHz) from the outside and generate a phase difference comparison clock (4 KHz); Clock generators 20A, 20B, and 20C which generate a basic clock (32.768 MHz) by synchronizing the clock of the self-oscillator with the phase difference comparison clocks of the clock receivers 10A and 10B; The best one of the three clocks received from the clock generators 20A, 20B, and 20C is selected, multiplied by 65.536 MHz, and then divided and converted to light by the pre / optical converters 40A and 40B. It is composed of clock dividers 30A and 30B which are supplied to the central data link units 50A and 50B in the exchanger, multiplied by 16.384 MHz, and then redundantly provided as blocks for supplying the required clocks to the space switches 60A and 60B. In the network synchronizer, the clock generator includes a first phase difference measurer for measuring a phase difference between the phase difference comparison clocks (4KHz, 21) and the self-oscillating clocks (32.768MHz, 23) provided from the main clock generator (20A). 24); A second phase difference measuring unit 25 for measuring a phase difference between the phase difference comparison clocks 4KHz and 22 provided by the synchronous clock receiving unit 10A and the self-oscillating clock (32.768MHz); Electro-exchanger network synchronizer device comprising a microprocessor (27) for monitoring the state of the main clock generator 20A by directly reading the phase difference data from the phase difference measurement unit 25 without passing through the common memory. . The method of claim 1. The clock distribution unit monitors three basic clocks provided by the clock generators 20A, 20B, and 20C and outputs the state to the basic clock selection address generation unit; Basic clock selection address generators 32A and 32B for selecting and outputting two basic clock addresses that are normal among clocks output from the clock state monitoring units 31A and 31B; A redundancy control unit (33A, 33B) for selecting only one of the two addresses output from the basic clock selection address generator (31A, 31B) and outputting it to the basic clock selection unit (34A, 34B); Of the three basic clocks provided by the clock generators 20A, 20B, and 20C, the clocks of the addresses output from the redundant control units 33A and 33B are output, multiplied, divided and supplied to the central data and the space switch. Electro-exchanger network synchronizer device characterized in that it comprises a portion (34A, 34B). 3. The redundancy control unit of claim 2, wherein the redundancy control unit inputs two clock addresses (X1, X2; Y1, Y2) output from the basic clock selection address generation unit 32A, and is always 1 by an enable terminal connected high. First three-phase buffer units 33-1A and 33-2A for selecting two clock addresses X1 and X2 as addresses of the basic clock selection unit; Input two clock addresses (X1, X2; Y1, Y2) output from the basic clock selection address generator 32B, respectively, and always enable one clock address (Y1, Y2) by the enable terminal connected to low. And a second three-phase buffer unit (33-1B, 33-2B) to be selected as the address of the basic clock selection unit.