JPH05153096A - Synchronizing circuit in supervisory and controlling device - Google Patents

Abstract

PURPOSE:To reduce the deviation of a pannel selecting signal by obtaining the synchronization of counters where a clock pulse is generated concerning a synchronizing circuit where the synchronization of pannel monitoring boards is obtained in a supervisory and controlling device where the pannel monitoring board has duplexed structure. CONSTITUTION:The pannel monitoring boards of a current system and a stand-by system are provided in the supervisory and controlling device which is provided with second clock generators 14a and 14b which generates the clock pulse of a frequency being higher than in a conventional practice as the clock generator, frequency-dividing circuits 15a and 15b and control means 16a and 16b. The frequency-dividing circuits 15a and 15b frequency-divide the output clock pulses of the clock generators 14a and 14b. The control means 16a and 16b execute sampling to the output pulses of the frequency-dividing circuits 15b and 15a of another system by the output clock pulses of the clock generators 14a and 14b of the own system so as to set a prescribed value in the frequency-dividing circuits 15a and 15b based on the sampling output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit in a supervisory controller, and more particularly to a synchronizing circuit for synchronizing a panel supervisory panel in a supervisory controller having a dual panel supervisory panel.

In a supervisory control device in which a panel monitor panel has a dual structure of an active system and a standby system, when a failure occurs in the panel monitor panel of the active system, switching to the panel monitor panel of the standby system is continued without delay and monitoring is continued. However, it is necessary to synchronize the panel monitoring boards of the active system and the standby system so that the panel selection signals do not shift when switching.

[0003]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of a synchronizing circuit in a conventional supervisory control device. In the figure, the clock generator 3
1a, the selector 32a, the counter 33a and the NAND circuit 34a constitute a working circuit. Further, the clock generator 31b, the selector 32b, the counter 33b, and the NAND circuit 34b constitute a standby system circuit, and have the same circuit configuration as the working system circuit.

One output terminal of each of the NAND circuits 34a and 34b is connected to the other input terminal, and one output terminal of the NAND circuit 34b is connected to each select terminal of the selectors 32a and 32b. The clock generators 31a and 31b each have the same repetition frequency (for example, 1
This is an oscillator that generates and outputs (MHz). Counter 33
Each of a and 33b outputs the count value as a panel selection signal.

In the conventional synchronous circuit having such a configuration, a signal indicating the presence / absence of a failure in the active panel monitor board is input to one input terminal of the NAND circuit 34a via the terminal 35a, and similarly the NAND circuit is supplied via the terminal 35b. A signal indicating the presence / absence of a failure in the standby panel monitor is input to one input terminal of the circuit 34b. The signal indicating the presence / absence of the above-mentioned fault is, for example, at the high level in the normal state and at the low level when the fault occurs.

Therefore, when the active and standby panel monitor boards are normal, the output of the NAND circuit 34a is set to the low level and the output of the NAND circuit 34b is set to the high level, and the selectors 32a and 32b are respectively set. Selects and outputs the input signal of the terminal "0". As a result, the output clock pulse of the clock generator 31a is transmitted to the selector 32a.
Through the selector 32b to the clock terminal of the counter 33b, and the carry signal of the counter 33a is applied to the load terminal of the counter 33a through the selector 32a and the counter 33b through the selector 32b. Applied to the load terminal of.

Therefore, in the normal state, the panel selection signal obtained by counting the clock pulses from the same clock generator 31a is synchronously output from both the counters 33a and 33b at the same time.

In this state, when a failure occurs in the active panel monitor board and a low-level failure occurrence signal (alarm signal) is input to the terminal 35a, the NAND circuit 34
The output of a changes to high level, and NAND
The output of the circuit 34b changes to low level. As a result, the selectors 32a and 32b respectively select and output the input signal of the terminal "1".

Therefore, when a failure occurs, the clock generator 3
The clock pulse from 1b is applied to the clock terminal of the counter 33b through the selector 32b, and the counter 33b
The carry signal of b is transmitted to the counter 3 through the selector 32b.
It switches so that it may be supplied to the load terminal of 3b. That is, the active system is switched to the standby system panel monitoring panel.
Therefore, the panel selection signal used is switched from the output panel selection signal of the counter 33a to the output panel selection signal of the counter 33b.

[0010]

However, in the conventional synchronous circuit, the clock generators 31a and 31b, which are the generation sources of the clock pulses counted by the counters 33a and 33b, respectively.
However, since the clock generators 31a and 31b themselves do not operate in synchronization with each other, when switching from the active system to the standby system, the value of the panel selection signal immediately before the switching and the value immediately after the switching are switched. The value of the panel selection signal may not be transmitted continuously in a predetermined cycle (in the worst case, it may be shifted by one clock). Therefore, in the above-mentioned conventional synchronous circuit, when the panel monitoring panel is switched from the active system to the standby system, the panel selection signal may malfunction due to the deviation of the panel selection signal.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a synchronizing circuit in a supervisory control device that solves the above problems by synchronizing a counter that generates a clock pulse.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in the figure, the present invention is a counter 11a that counts clock pulses and outputs a panel selection signal,
11b, a first clock generator that generates the clock pulse, and clock pulse counters 11a and 11b.
To the load terminals of the counters 11a and 11b, and the selectors 12a and 12b for selectively inputting the output from the predetermined terminals of the counters to the load terminals of the counters 11a and 11b, respectively. Selector for commonly using the output clock pulse of the first clock generator of the panel monitoring panel and using the output clock pulse of the clock generator of the standby panel monitoring panel when a failure occurs in the active panel monitoring panel In the supervisory control device configured to switch between 12a and 12b, each of the active system and standby system panel monitoring boards generates second clock generators 14a and 14b which generate and output a clock pulse having a higher frequency than the clock pulse. Is provided in place of the first clock generator, and further the frequency dividing circuits 15a and 15b and the control means 16a and 16 are provided. It is obtained by a structure having and.

The frequency dividing circuits 15a and 15b frequency-divide the output clock pulses of the second clock generators 14a and 14b to generate a pulse having the same frequency as the output clock pulse of the first clock generator to generate its own system. Selectors 12a, 12 of
b as a clock pulse.

The control means 16a, 16b sample the output pulses of the frequency dividing circuits 15a, 15b of the other system with the output clock pulses of the second clock generators 14a, 14b, and based on the sampled output, A predetermined value is set in the frequency dividing circuits 15a and 15b.

[0015]

In the present invention, the clock pulses counted by the counters 11a and 11b which output the panel selection signal are the output pulses of the frequency dividing circuit 15a or 15b. The frequency dividing circuits 15a and 15b are used for the second clock generator 14 of the own system.
Control means 16a, 1 with clock pulses from a, 14b
6b loads a predetermined value based on the signal obtained by sampling the output pulses of the frequency dividing circuits 15a and 15b of the other system.

Therefore, in the present invention, the output pulse of the frequency dividing circuit 15a is synchronized with the output pulse of the frequency dividing circuit 15b of the other system, so that the delay of the clocks exchanged can be minimized.

[0017]

2 is a circuit diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals.
In FIG. 2, the switching means 13 is a 2-input NAND circuit 21.
a and 21b, and NAND circuits 21a and 21b
One output terminal is connected to the other input terminal, and
A fault detection signal (alarm signal) is input to the other input terminals of the NAND circuits 21a and 21b via terminals 22a and 22b.
Is entered.

The counters 23a and 23b constitute the frequency dividing circuits 15a and 15b, respectively. The D-type flip-flops 24a and 25a and the NAND circuit 26a constitute the control means 16a, and similarly the D-type flip-flops 24b and 25b and the NAND circuit 26b constitute the control means 16b.

The Q output terminals of the flip-flops 24a and 24b are connected to the data input terminals of the flip-flops 25a and 25b, and the data input terminals of the flip-flops 24a and 24b are connected to the output terminals Q _B of the counters 23b and 23a of the other system. It is connected. Flip-flop 24a,
The clock pulse from the clock generator 14a of its own system is input to the clock terminal 25a of the flip-flop 25a.
In b and 25b, the clock pulse from the clock generator 14b of its own system is input to the clock terminal.

Further, the NAND circuit 26a has its input terminal connected to the XQ output terminal of the flip-flop 24a and the Q output terminal of the flip-flop 25a, and its output terminal connected to the load terminal of the counter 23a. Similarly, NAN
The input terminal of the D circuit 26b is X of the flip-flop 24b.
The Q output terminal is connected to the Q output terminal of the flip-flop 25b, and the output terminal is connected to the load terminal of the counter 23b.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. First, when the active and standby panel monitors are operating normally, the NAND
The output of the circuit 21a is set to low level and the output of the NAND circuit 21b is set to high level, and the selectors 12a and 12b are controlled by the output signal of the NAND circuit 21b so as to selectively output the input signal of the terminal "0". It Therefore, the output pulses of the counter 23a are applied to the clock terminals of the counters 11a and 11b through the selectors 12a and 12b, respectively, and the carry signals of the counter 23a are applied to the load terminals of the counters 11a and 11b through the selectors 12a and 12b, respectively. To be done.

On the other hand, the clock generator 14a oscillates and outputs a clock pulse having a higher frequency than that of the conventional clock pulse, for example, 10 MHz as shown in FIG.
The clock generator 14b is the clock generator 14a.
3D, which has the same frequency as the output clock pulse (that is, 10 MHz in this case), is oscillated and output. As in the conventional case, the clock generators 14a and 14b oscillate and output the clock pulse independently of each other.

The counters 23a and 23b respectively divide the above-mentioned input clock pulse, and output from the output terminal Q _{B the} pulses shown in FIGS. 3B and 3I having the same frequency as the conventional clock pulse (for example, 1 MHz). Output. Counter 11
a and 11b count the clocks shown in FIG.
Panel selection signals whose values change as shown in FIG. 3C are output in synchronization with each other.

In this state, if a failure occurs in the active panel monitor board and a low level alarm signal is input to the terminal 22a, the output of the NAND circuit 21b changes to low level, and the selectors 12a and 12b operate. The input signal of the terminal "1" is selectively output.

Therefore, when a failure occurs, the clock generator 1
A pulse as shown in FIG. 3 (I) obtained by dividing the output clock pulse of 4b by the counter 23b is the selector 12a, 1
It is applied to the counters 11a and 11b through 2b and counted here. On the other hand, the D-type flip-flop 24b is applied to the data terminal of the counter 23 shown in FIG.
A signal obtained by sampling the output pulse of a with the clock pulse (FIG. 3D) from the clock generator 14b is output from its Q output terminal.

Therefore, the Q of the D-type flip-flop 24b
The output signal is the clock generator 14b as shown in FIG.
Pulse having a frequency of 1 MHz which is phase-synchronized with the output clock pulse of the D-type flip-flop 24b.
As shown in FIG. 3 (F), a 1 MHz pulse having a phase opposite to that of the pulse in FIG. 3 (E) is taken out from the output terminal.

The D-type flip-flop 25b is shown in FIG.
The pulse shown in (E) is sampled with the clock pulse shown in FIG. 3 (D) from the clock generator 14b, and the frequency of 1 MHz as shown in FIG.
And the Q output signal of the flip-flop 24b (see FIG.
A pulse delayed by one clock pulse cycle from (E)) is generated and output.

The NAND circuit 26b outputs both Q output signals of the above two flip-flops 24b and 25b (see FIG. 3).
The NAND of (E) and (G) is calculated, and the signal shown in FIG. 3H is output and applied to the load terminal of the counter 23b. As shown in FIG. 3H, the output signal of the NAND circuit 26b falls in synchronization with the falling edge of the output pulse of the flip-flop 24b, and the clock generator 14
This is an edge detection signal having a width corresponding to one cycle of the output clock pulse of b. For example, the counter 23b is loaded with a predetermined value at the falling edge thereof.

As a result, the counter 23b outputs from the predetermined output terminal a signal as shown in FIG. 3 (I) which becomes high level when the output clock of the clock generator 14b is counted by a predetermined number from the loaded predetermined value. This counter 23
The output pulse of b is passed through the selector 12b to the counter 11
It is supplied to the clock terminal of b and is counted here. As a result, the counter 11b generates and outputs a panel selection signal whose value changes as shown in FIG.

Therefore, according to this embodiment, the counter 23
Since the load timings of a and 23b are generated by using the output pulses (clocks) of the counters 23b and 23a received from other systems, as shown in FIGS. 3C and 3J, from the active system to the standby system. At the maximum, the pulse selection signal requires an error of one cycle (1/10 ⁷ seconds) of the output clock pulse of the clock generator 14b.
The error can be greatly reduced compared with 10 ⁶ seconds). As a result, the normal polling operation by the panel selection signal becomes possible even after the switching.

[0031]

As described above, according to the present invention, since the delay of the clock pulse can be minimized, the shift of the panel selection signal when the panel monitoring panel is switched from the active system to the standby system is compared to the conventional one. It has a feature that it can be remarkably small and that a normal polling operation can be performed by the panel selection signal even after the above switching.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of FIG.

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

11a, 11b, 23a, 23b Counter 12a, 12b Selector 13 Switching means 14a, 14b Second clock generator 15a, 15b Dividing circuit 16a, 16b Control means 24a, 24b, 25a, 25b D-type flip-flop

Claims (1)

[Claims] 1. A counter (11a, 11b) for counting clock pulses and outputting a panel selection signal, and a first clock generator (31a, 31a, 31b) for generating the clock pulse.
31b) and the clock pulse to the counter (11a,
11b), and a panel monitor panel for the active system and a standby system, each of which has a selector (12a, 12b) for selectively inputting an output from a predetermined terminal of the counter to a load terminal of the counter (11a, 11b), Switching means (13)
Therefore, normally, the output clock pulse of the first clock generator (31a) of the active panel monitor is commonly used, and when a failure occurs in the active panel monitor, the first panel monitor panel of the standby system is Of the selector (12a, 1) to use the output clock pulse of the clock generator (31b) of
2b), wherein each of the active and standby panel monitoring boards includes a second clock generator (14a, 14b) for generating and outputting a clock pulse having a higher frequency than the clock pulse. ) Is provided in place of the first clock generator (31a, 31b), and the output clock pulse of the second clock generator (14a, 14b) is divided to divide the first clock generator (31a, 31b).
a, 31b) a frequency divider circuit (15a, 15) that generates a pulse having the same frequency as the output clock pulse and supplies it as a clock pulse to the selector (12a, 12b) of its own system.
b), the output clock pulse of the second clock generator (14a, 14b) is used to sample the output pulse of the frequency dividing circuit (15a, 15b) of the other system, and the output pulse of the own system is used based on the sampling output. A synchronizing circuit in a supervisory control device, comprising: control means (16a, 16b) for setting a predetermined value in the frequency dividing circuits (15a, 15b).