JP2000172366A - Clock distribution circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock distribution circuit where abnormality in a clock generation on a master clock generation system and a reset signal of a master side clock generation system does not affect a slave clock generation system. SOLUTION: When a count value N of a clock A1 by a counter 104 reaches a prescribed value X, a decoder 105 outputs an output clock D and a reset signal R1. When the count value of the counter 104 is X-ΔX<=N<=X+ΔX, a window generator 106 makes a window signal W on. A phase comparator 108 compares the signal W with the phase of a clock B1. A phase comparator 109 compares a reset signal r2 with the phase of the clock B1. A frequency divider 110 and a differentiator 111 generate a reset signal R3. A selection signal generator 114 switches the reset signals R1, r2 and R3 based on comparison results of the comparator 108 and 109 and switches the master/slave of the clock generation systems 100 and 200 whenever necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit used for, for example, a digital communication device, and more particularly to a clock distribution circuit having a redundant configuration.

[0002]

2. Description of the Related Art Conventionally, a redundant circuit having a redundant configuration is known as a clock distribution circuit used in a digital communication device or the like.

Such a clock distribution circuit has, for example, two clock generation systems of the same configuration, and causes these clock generation systems to generate exactly the same clock. Then, a clock generated by one of the clock generation systems is selected and supplied to a subsequent circuit. When an abnormality occurs in the selected clock generation system, the selection is immediately switched, and the clock generated by the other clock generation system is supplied to a subsequent circuit.

As described above, in the clock distribution circuit having the redundant configuration, the system for supplying the clock (master-side clock generation system) and the system for not supplying the clock (slave-side clock generation system) are appropriately switched so that the latter stage is provided. To improve the reliability of the clock supplied from the circuit.

[0005]

In such a clock distribution circuit, the phase of the clock generated by the master-side clock generation system and the phase of the clock generated by the slave-side clock generation system can be matched. desirable. If the phases of the clocks generated by these clock generation systems do not match, when the selection of the system is switched, a phase shift of the clock supplied to the subsequent circuit occurs.

As a method of preventing such a phase shift, for example, it is conceivable to configure a clock distribution circuit so that the master-side clock generation system resets the slave-side clock generation system.

However, in the clock distribution circuit having such a configuration, when the generated clock is disturbed (clock disconnection, loss of phase synchronization, etc.) in the master-side clock generation system, or the reset signal transmitted from the master-side clock generation system. When the disturbance occurs, there is a disadvantage that these disturbances propagate to the slave-side clock generation system and are disturbed even to the slave-side generated clock.

Therefore, in the conventional clock distribution circuit,
The reliability of the clock supplied from the subsequent circuit is not sufficiently ensured.

For these reasons, there has been a demand for a clock distribution circuit in which an abnormality generated in a clock generated by the master clock generation system or a reset signal does not propagate to the slave clock generation system.

[0010]

The present invention relates to a clock distribution circuit that generates an output clock by each of a master-side clock generation unit and a slave-side clock generation unit.

Then, each clock generating means is
A counter for counting the number of pulses of the first input clock;
A signal generation unit that generates a first reset signal and an output clock when the count value of the counter reaches a predetermined value, and whether a phase difference between the second input clock and the first reset signal is within a normal range. A first phase detector for detecting whether or not
A second phase detector for detecting whether a phase difference between the second reset signal supplied from the other clock generator and the second input clock is within a normal range, and a first phase detector. And the first based on the detection result of the second phase detector.
Select the reset signal or the second reset signal of
A signal selection unit that supplies the clock signal to the counter and supplies the other clock generation unit as a second clock signal.

According to such a configuration, the first reset signal (that is, the internally generated reset signal) and the second reset signal (the reset generated by the other clock generating means) are generated by using the second input clock. Signal) is within the normal range.
Then, a reset signal used for resetting the counter can be selected based on the detection result.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement of each component are only schematically shown to an extent that the present invention can be understood, and numerical conditions described below are merely examples. Please understand that.

FIG. 1 is a block diagram showing a configuration of a clock distribution circuit according to this embodiment.

As shown in FIG. 1, the clock distribution circuit includes two clock generation systems 100 and 200. The configurations of these clock generation systems 100 and 200 are exactly the same.

In the clock generation systems 100 and 200,
A PLL (Phase Locked Loop) 101 fetches an input clock A0 (for example, 64 kHz) from a preceding circuit, locks the phase, and outputs the input clock A1.
This input clock A1 is output as it is as the output clock C.

The flip-flop 102 receives an input clock B0 (for example, 8 kHz) from a signal input terminal,
In addition, the input clock A1 is input from a clock input terminal. Then, a signal in which the input clock B0 is synchronized with the input clock A1 is output as the input clock B1.

The flip-flop 103 receives a reset signal R2 generated by the other clock generation system from a signal input terminal, and receives an input clock A1 from a clock input terminal. Then, a signal obtained by synchronizing the reset signal R2 with the clock A1 is output as a reset signal r2.

The counter 104 counts the number of pulses of the input clock A1.

The decoder 105 inputs the count value N of the counter 104. Then, when the count value N reaches a predetermined value X, a reset signal R1 and a clock D are generated and output. The decoder 105 corresponds to the “signal generator” of the present invention, and the clock D corresponds to the “output clock” of the present invention.

The window generator 106 includes a counter 104
From the decoder 105. When X−ΔX ≦ N ≦ X + ΔX, the window signal W is set to the on level (here, the high level).
To ΔX is a value that determines the detection accuracy when detecting the disturbance of the phase of the reset signal R1 (described later), and can be set arbitrarily.

The differentiator 107 includes a flip-flop 102
Is differentiated and output as a differentiated signal I.

The phase comparator 108 compares the phase of the differential signal I with the phase of the window signal W, and compares the result of this comparison with the signal O.
Output as k / NG signal P1.

FIG. 2A is a block diagram showing an example of the internal configuration of the phase comparator 108. In the figure, an SR latch 108a inputs a window signal W from a set input terminal S and inputs a differential signal I from a reset input terminal R. The inversion gate 108b receives the window signal W and outputs an inversion signal. The flip-flop 10
8c is the timing of the inverted signal,
8a is fetched and output as an Ok / NG signal P1.

The phase comparator 108, together with the window generator 106 and the differentiator 107, constitutes a first phase comparator of the present invention.

In FIG. 1, a phase comparator 109 is provided with a reset signal r2 input from the flip-flop 103.
Is the clock B input from the flip-flop 102
1 and outputs the result of this comparison as an Ok / NG signal P2.

FIG. 2B is a block diagram showing an example of the internal configuration of the phase comparator 109. In the figure, an AND gate 109a inputs a reset signal r2 from one input terminal, and inputs a clock B1 from the other input terminal. The inverting gate 109b receives the clock B1 and
Output inverted clock. The counter 109c inputs the inverted clock from the clock input terminal, and inputs the output of the AND gate 109a from the reset input terminal. The upper limit comparator 109d compares the output value n of the counter 109c with a predetermined value x, and when n ≦ x, sets the low level to n> x
In this case, the high level is output as the upper limit comparison signal Sd. The lower limit comparator 109e compares the output value n of the counter 109c with the above-described predetermined value x, and when n <x, the high level, when n ≧ x, the low level, and the lower limit comparison signal Se
Output as The flip-flop 109f is AND
The signal Se is taken in at the timing of the output signal of the gate 109a and output as a signal Sf. OR gate 109g
Outputs the logical sum of the signals Sd and Sf as an Ok / NG signal P2.

This phase comparator 109 is the second comparator of the present invention.
Are constituted.

In FIG. 1, a frequency divider 110 divides an input clock B1 by 1 / n and outputs the result. This divider 1
10 is reset by a reset signal r2 or R1 selected by a selector 112 (described later). The differentiator 111 differentiates the output of the frequency divider 110 and outputs the result as a reset signal R3. Divider 110 and differentiator 1
11 constitutes the frequency-divided reset signal generating section of the present invention.

The selector 112 includes a selection signal generator 114
Under the control described later, one of the reset signal R1 and the reset signal r2 is selected. Also, the selector 113
Is controlled by the selection signal generator 114,
2 is selected or the reset signal R3 output by the differentiator 111 is selected. The selection signal generator 114 includes signals P1 and P2 indicating the comparison results of the phase comparators 108 and 109 and master / slave signals MS1 and M
The selectors 112 and 113 are controlled based on S2 (described later). Here, the master / slave signal MS1 is a signal indicating whether the clock generation system 100 is a master or a slave, and the master / slave signal MS2 is a signal indicating whether the clock generation system 200 is a master or a slave. These signals MS1 and MS2 are respectively transmitted and received between, for example, an external control device (not shown). The selectors 112 and 113 and the selection signal generator 114
The signal selector of the present invention is configured.

Next, the operation of the clock distribution circuit according to this embodiment will be described in detail.

First, the operation of the phase comparator 108 (see FIG. 2A) will be described with reference to FIG.

In the phase comparator 108, the SR latch 108a is set at the rising timing of the window signal W and reset at the rising timing of the differential signal I. The flip-flop 108c is
At the timing of the window signal W, a signal is fetched. Therefore, as shown in FIG. 3A, when the differential signal I is input when the window signal W is at the high level,
The RS latch 108a is reset when the signal is taken in by the flip-flop 108c.
The G signal P1 becomes low level. As can be seen from FIG. 3C, this is because the phase shift of the reset signal R1 is ± ΔX (ΔX is the window generator 1) with respect to the clock B1.
06 (set value of 06), that is, within the allowable range. On the other hand, as shown in FIG. 3B, when the window signal W is at a high level, the differential signal I
Is not input, the flip-flop 108
When the signal c is received, the RS latch 108a is set, so that the output signal P1 of the phase comparator 108 goes high. This indicates that the phase shift of the reset signal R1 was out of the allowable range.

Next, the operation of the phase comparator 109 (see FIG. 2B) will be described with reference to FIG.

In the phase comparator 109, after the counter 109c is reset by the initial setting (FIG. 4)
(See T1 in (A)), the count value is increased at the timing of clock B1. At this time, the upper limit comparison signal Sd is at a low level, and the lower limit comparison signal Se is at a high level. afterwards,
When the count value n of the counter 109c increases and reaches x (here, x = 8 for simplicity of explanation),
The lower limit comparison signal Se becomes a low level (see T2 in the figure). Further, when the clock signal r2 is input within the pulse width of the eighth clock B1, the low level is latched by the flip-flop 109f and the counter 109c is reset. Thereby, the signal S
Since both d and Se are maintained at the low level, Ok / N
The G signal P2 becomes low level (normal state). On the other hand, 8
When the clock signal r2 is input later than the first clock B1 (see T3 in FIG. 4B), the counter 109
Since the next clock B1 is input without resetting c, the upper limit comparison signal Sd goes high, and the Ok / NG signal P2 goes high (abnormal state). When the clock signal r2 is input before the eighth clock B1 (see T4 in FIG. 3D), the high level is latched in the flip-flop 109f, so that the Ok / NG signal P2 is High level (abnormal state).

Next, the operation of the selection signal generator 114 will be described with reference to FIG.

When the power is turned on, the clock generation system 100 is set to the master-side clock generation system. When determining that the selection signal generator 114 of the clock generation system 100 is set to the master side, the selection signal generator 114 subsequently fetches the Ok / NG signal P1 from the phase comparator 108 and outputs the reset signal R1
It is checked whether the phase shift is within the allowable range. When the phase shift of the reset signal R1 is within the allowable range, the selector 11 selects the reset signal R1 regardless of the detection result of the phase shift of the reset signal r2.
2 and 113 are controlled. In this case, neither the clock generation systems 100, 200 change the master / slave. FIG. 5A shows a pattern example of each of the clocks A0, B0, C, and D when the clock distribution circuit is operating normally as shown in FIG. 5A, and FIG. ).

On the other hand, when the phase shift of the reset signal R1 is out of the allowable range, the selection signal generator 114 of the clock generation system 100 selects the reset signal R3 regardless of the detection result of the phase shift of the reset signal r2. The selector 113 is controlled so that the Then, the clock generation system 10
0 selection signal generator 114 changes the master / slave discrimination to slave and changes this change to signal MS1.
, For example, to an external control device (not shown).
The external control device or the like changes the clock generation system 200 to the master according to the signal MS2.

When the power is turned on, the clock generation system 200 is set to the slave clock generation system. When the selection signal generator 114 of the clock generation system 200 determines that it is set to the slave side,
9 and fetches the Ok / NG signal P2, and checks whether or not the phase shift of the reset signal r2 is within an allowable range. When the phase shift of the reset signal r2 is within the allowable range, the selector 1 selects the reset signal r2 regardless of the detection result of the phase shift of the reset signal R1.
12 and 113 are controlled. In this case, the clock generation systems 100 and 200 do not change the master / slave.

On the other hand, when the phase shift of the reset signal r2 is out of the allowable range, the selection signal generator 114 of the clock generation system 200 subsequently outputs the signal P1 from the phase comparator 108.
And checks whether the phase shift of the reset signal R1 is within an allowable range. If the phase shift of the reset signal R1 is within the allowable range, the selectors 112 and 113 are controlled so that the reset signal R1 is selected, and the master / slave distinction is changed to master. This change is transmitted to an external control device or the like by a signal MS2. In this case, an external control device or the like may change the clock generation system 100 to a slave or maintain the clock generation system 100 as a master according to the signal MS1. When the clock generation system 100 is maintained as a master, after the phase shift is corrected, an external control device or the like operates the clock generation systems 100 and 200.
Reset master / slave for If the phase shift of the reset signal r2 is out of the allowable range and the phase shift of the reset signal R1 is out of the allowable range, the selection signal generator 114 of the clock generation system 200 selects the reset signal R3. The selector 113 is controlled as described above, and the master / slave distinction is changed to master, and this change is transmitted to, for example, an external control device or the like by the signal MS2. In this case as well, the external control device or the like may change the clock generation system 100 to a slave or maintain it as a master. If the clock generation system 100 is maintained as a master, the clock generation system 100, The master / slave for 200 is reset.

As described above, in the clock distribution circuit according to this embodiment, the phase shift between the reset signal R1 and the reset signal r2 (substantially, the reset signal R2) is within the normal range using the input clock B1. Or not, and based on the detection result, reset signals used for the counter 104 are set to R1, R2, R
3 and switching the master / slave discrimination as necessary. Therefore, when an abnormality occurs in the reset signal R2 (and therefore, the signal r2) (for example, when the generated clock C is disturbed in the master-side clock generation system and affects the reset signal, or when the master-side clock generation system and the slave-side clock generation Even if the reset signal R2 is disturbed on the signal line between the slave and the system, the generated clock on the slave side is not affected.

That is, according to this embodiment, it is possible to provide a clock distribution circuit in which an abnormality generated in a generated clock or a reset signal of one clock generation system does not propagate to the other clock generation system.

[0043]

As described above in detail, according to the clock distribution circuit of the present invention, the reliability of the clock supplied from the subsequent circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock distribution circuit according to an embodiment;

FIGS. 2A and 2B are block diagrams each showing an internal configuration example of a phase comparator according to the embodiment; FIG.

FIG. 3 is a timing chart for explaining an operation of the phase comparator according to the embodiment;

FIG. 4 is a timing chart for explaining an operation of the phase comparator according to the embodiment;

FIG. 5 is a timing chart for explaining the operation of the signal selection unit.

[Explanation of symbols]

 100, 200 clock generation system 101 PLL 102, 103 flip-flop 104 counter 105 decoder 106 window generator 107 differentiator 108, 109 phase comparator 110 frequency divider 111 differentiator 112, 113 selector 114 selection signal generator

Claims (4)

[Claims] 1. A clock distribution circuit that generates an output clock by each of a master-side clock generation unit and a slave-side clock generation unit, wherein each of the clock generation units includes a counter that counts the number of pulses of a first input clock. A signal generation unit that generates a first reset signal and the output clock when a count value of the counter reaches a predetermined value; and a phase difference between a second input clock and the first reset signal is within a normal range. A first phase detector for detecting whether or not the phase difference is within the range, and a phase difference between a second reset signal supplied from the other clock generation means and the second input clock is within a normal range. A second phase detector for detecting whether or not the first reset signal or the first reset signal based on detection results of the first phase detector and the second phase detector. And a signal selecting unit that selects the second reset signal, supplies the selected signal to the counter, and supplies the second reset signal to the other clock generating unit as the second clock signal. circuit. 2. The method according to claim 1, wherein the second input clock is divided to generate a third
And a frequency-divided reset signal generation unit that generates a reset signal of the first and second reset signals based on detection results of the first phase detection unit and the second phase detection unit. The clock distribution according to claim 1, wherein one of the third reset signals is selected, supplied to the counter, and supplied to the other clock generation unit as the second clock signal. circuit. 3. The signal selecting section of the master-side clock generating means selects the first reset signal when a phase difference detected by the first phase detecting section is within a normal range. When the phase difference detected by the first phase detection unit is not within the normal range, the clock generation unit is changed to a slave side and the third reset signal is selected. Item 3. The clock distribution circuit according to Item 2. 4. The signal selecting section of the slave-side clock generating means selects the second reset signal when the phase difference detected by the second phase detecting section is within a normal range, If the phase difference detected by the second phase detector is not within the normal range, the clock generator is changed to the master side, and the phase difference detected by the first phase detector is within the normal range. If so, the first reset signal is selected, and if the phase difference detected by the first phase detector is not within a normal range, the third reset signal is selected. Or the clock distribution circuit according to any one of 3.