JP3536780B2 - Sync source signal switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference frame signal used in a device by selecting / switching one of signals input from a plurality of transmission lines of a communication network (hereinafter referred to as a device frame signal). More particularly, the present invention relates to a synchronization source signal switching circuit with improved phase error at the time of selection / switching.

[0002]

2. Description of the Related Art In a synchronous network digital communication system, a plurality of transmission paths (synchronization sources) input to a communication station or a communication device are established in order to establish synchronization of the entire network (network).
, A certain transmission path is selected, and a reference frame signal (for performing signal processing in a corresponding station (apparatus) in synchronization with a frame signal extracted from a signal such as data or clock input from the transmission path) is selected. Hereinafter, an in-device frame signal) is generated. In this case, the frame phase of the generated intra-device frame signal often differs from each other due to a difference in the propagation distance of each input transmission line, and synchronization is often established only for the frame period of the intra-device frame signal. When the input transmission line of the synchronization source signal or the like breaks down, for example, to cope with a disconnection of the clock signal,
The signal state such as the clock signal input from each transmission line at that time is examined, and another one of the clock signals obtained from the plurality of transmission lines is selected and switched again, and the frame signal in the device is changed. Has been generated. One of the synchronization source signal switching circuits of a communication station or a communication device having such a function is disclosed in FIGS. 4 and 5 of JP-A-08-204689 (title of the invention: frame pulse switching circuit).

[0003] Hereinafter, using a block diagram of the synchronization source signal switching circuit shown in FIG. 3 and its signal diagram shown in FIG. 4, a synchronization source having a similar configuration to the technique disclosed in Japanese Patent Application Laid-Open No. 08-204689 will be described. The signal switching circuit will be described.

[0004] The synchronization source signal switching circuit shown in FIG. 3 transmits N clock signals 201, 202,... From N (1, 2,..., N: N is a natural number) transmission lines of a communication network.
Each of 20N is (1 / m1), (1 / m2),
, (1 / mN) are input to frequency dividing circuits 131, 132,. However, m1, m2, ..., mN are natural numbers, and m1, m
, MN are frequency dividing circuits 131, 132,.
This is the number of divisions for each of 3N. Note that the frequency dividing circuits 131 and 1
The division number of 32,..., 13N must be appropriately determined according to the device specifications. Further, the frequency dividing circuits 131, 132,
, 13N can use a counter or the like as is well known.
Each of the frame signals 231, 232,..., 23N is sent to the frame signal selection circuit 120A and the corresponding frame signal abnormality detection circuits 111, 112,.

[0005] Frame signal abnormality detection circuits 111, 11
, 11N are supplied with the supplied frame signal 23.
, 23N detect a signal abnormality (generally due to an abnormality of a transmission line or a communication device) in which a signal break or frequency abnormality occurs, the frame signals 231 and 23N are detected.
, 23N are sent to the frame signal selection control circuit 110A. If the abnormally detected frame signal is a signal for a current in-apparatus frame signal, the frame signal selection control circuit 110A outputs an in-apparatus frame signal 2 (described later) to one of normal frame signals from another transmission path.
The frame signal selection circuit 120A is controlled by the selection control signal 200A so as to switch 40A. That is,
The frame signal selection circuit 120A receives the selection control signal 210
The frame signal (one of 241 to 24N) designated by A is output to the phase comparison circuit 140 as the synchronization source frame signal 230A.

Referring to FIG. 4, the clock signals 201 and 202 have the same frequency, and the frequency dividing circuit 13
For 1 and 132, the frequency division numbers m1 and m2 are set to the same 5, respectively. Accordingly, the frequency dividers 131 and 132 generate frame signals 231 and 232 having a period five times that of the clock signals 201 and 202, respectively.

Now, when the frame signal 231 generated from the clock signal 201 is used as the synchronization source frame signal 230A for the in-device frame signal, when the frame signal abnormality detecting circuit 111 detects a signal abnormality of the frame signal 231, The frame signal selection control circuit 110A sends a selection control signal 210A to the frame signal selection circuit 120A so that a normal frame signal, for example, the frame signal 232 becomes a new synchronization source frame signal 230A. As a result, the frame signal selection circuit 120A outputs the frame signal 232 instead of the frame signal 231 as a new synchronization source frame signal 230A for the internal device frame signal. In this example, the phase of the clock signal 201 and the phase of the newly switched clock signal 202 are shifted by about 2 clocks.
Note that OA is about 2 clocks ahead of the phase without switching (see FIG. 4).

[0008] The phase comparison circuit 140 controls the oscillation frequency of the voltage controlled oscillation (VCO) circuit 150 based on the comparison output. The oscillation signal output from the VCO circuit 150 is a device internal clock signal 250A used as a reference clock in the device. The frequency dividing circuit 160 has an internal clock signal 250A.
Is divided by mv (mv is a natural number) to generate an in-device frame signal 240A having a period of (1 / mv). Phase comparison circuit 14
0 performs a phase comparison between the synchronization source frame signal 230A and the in-device frame signal 240A to generate the comparison output. That is, the phase comparison circuit 140, the VCO circuit 150, and the frequency division circuit 160 constitute a phase-locked oscillator, and the in-device frame signal 2 that is phase-locked to the synchronization source frame signal 230
40A and the internal clock signal 250A. Note that the frequency division number mv of the frequency divider 160 is such that the pulse interval of the internal frame signal 240A and the pulse interval of the internal clock signal 250A are an integer ratio, and the internal frame signal 240A is in phase with the synchronization source frame signal 230. Choose an appropriate value that can be synchronized.

[0009]

As described above, the synchronization source signal switching circuit according to the prior art shown in FIG. 3 synchronizes a clock signal or the like from a plurality of transmission paths input from a network to a communication station or a communication device. Since the source signals have different frame phases depending on the propagation distance of each transmission path,
When the transmission path of the synchronization source signal is switched due to a signal abnormality of the current synchronization source signal or the like, the phase of the synchronization source frame signal input to the phase comparison circuit of the phase locked oscillator may greatly fluctuate. The frame signal in the apparatus also has a disadvantage that the phase greatly fluctuates, which is a major cause of occurrence of errors in input data.

[0010]

A synchronization source signal switching circuit according to the present invention selects a normal clock signal from signals supplied from each of a plurality of transmission paths of a communication network.
In a synchronization source signal switching circuit for switching to generate an in-device frame signal, a frequency difference between the plurality of clock signals is provided.
A clock signal that generates a clock abnormal signal when detecting normal
The abnormality detection circuit and the clock signal abnormality detection circuit are currently in use.
When a frequency abnormality of the clock signal is detected,
Clock to select the correct one of the clock signals.
A clock signal selection control circuit for generating a clock selection signal;
A clock signal selecting circuit that selects one of the clock signals to generate a selected clock signal under control of a clock selection signal, a first frequency dividing circuit that divides the selected clock signal to generate a synchronization source frame signal, A phase-locked oscillation circuit that synchronizes with the synchronization source frame signal and generates an in-device frame signal obtained by dividing the frequency of the synchronization source frame signal.

[0011]

[0012] The synchronization source signal switching circuit, when the frequency of the current clock signal is abnormal, when the frequency of the newly selected clock selection signal is different from the frequency of the current clock signal, the clock signal selection circuit The control circuit is configured to change the frequency division number of the second frequency division circuit to the frequency division number at which the in-device frame signal can be synchronized with the synchronization source frame signal at the same time as the transmission of the clock abnormality signal, and A configuration for supplying the signal to the second frequency dividing circuit can be employed.

Another one of the synchronization source signal switching circuits is a phase comparison circuit in which the phase synchronization oscillation circuit compares the phase of the synchronization source frame signal with the phase of the frame signal in the device to generate a comparison output. A voltage controlled oscillation circuit that is controlled by the comparison output to generate an internal clock signal; and a second frequency divider that divides the internal clock signal to generate the internal frame signal. be able to.

[Operation] The synchronization source signal switching circuit according to the present invention selects one transmission path from a plurality of transmission paths of a network and inputs a clock signal in order to establish synchronization of the entire network in a communication system or the like. Then, signal processing is performed in the communication device in synchronization with a frame signal (synchronization source frame signal) serving as a synchronization source extracted from the clock signal. In this synchronization source signal switching circuit, a clock signal selection circuit for selecting a clock signal from one transmission line from a plurality of transmission lines is provided before a frequency dividing circuit for generating a synchronization source frame signal. By controlling the frequency division number of the frequency division circuit included in the circuit by the frequency division number control signal from the clock signal selection control circuit,
A signal at the stage of selecting one transmission path from a plurality of transmission paths is used as a clock signal extracted from each transmission path. It is characterized in that signal processing can be performed without greatly changing the phase of a reference frame signal (frame signal in the apparatus), and that input signals of various transmission rates can be flexibly handled.

[0015]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a synchronization source signal switching circuit according to the present invention. FIG. 2 is a diagram showing main signals in the embodiment of FIG.

The synchronization source signal switching circuit according to the embodiment of FIG. 1 also has N clock signals 201, 202,..., 20N from N transmission lines of the communication network, similarly to the synchronization source signal switching circuit according to the prior art. Are supplied respectively. Each of the clock signals 201, 202,..., 20N is a corresponding clock signal abnormality detection circuit 101, 102,.
0N, and the clock signal selection circuit 120.

Clock signal abnormality detection circuits 101 and 10
,..., 10N are supplied with the supplied clock signal 20.
, 20N detect signal abnormalities such as signal breaks and frequency abnormalities caused by transmission line and communication device failures, respectively. When the input clock signal 201 or the like is in an abnormal state, the corresponding clock signal abnormality detection circuits 101, 102,.
And the like, and sends a clock abnormality signal indicating the detection of a signal abnormality to the clock selection control circuit 110.

The clock selection control circuit 110 converts the clock abnormal signal into the clock signal abnormality detecting circuits 101 and 10.
, 20N, the clock signals to be selected and output by the clock signal selection control circuit 110 according to which of the clock signals 201, 202,.
Is determined. Then, the clock signal selection control circuit 110 controls the clock selection signal 200 indicating the clock signal determined by the clock signal selection control circuit 110 to control the selection clock signal 220 used as a synchronization source of the in-device frame signal 240 described later. Select and output. Further, the clock selection control circuit 110 outputs the frequency division number selection control signal 210 indicating the frequency division number corresponding to the frequency of the selected clock signal 220 to the frequency division circuit 130 for the reason described later.

The frequency dividing circuit 130 selects the selected clock signal 22
0 is the division number m0 indicated by the division number selection control signal 210
(M0 is a natural number) and is divided by the synchronization source frame signal 230.
Is generated, and the synchronization source frame signal 230 is
Output to 40. The value of the frequency division number m0 is such that the pulse interval of the in-device frame signal 240 and the pulse interval of the in-device clock signal 250 output from the frequency dividing circuit 160 described later are an integer ratio, and the in-device frame signal 240A is the synchronization source frame. An appropriate value that can be phase-synchronized with the signal 230 is selected.
For example, when the frequencies of the clock signals 201, 202,...
10 outputs a frequency division number control signal 210 for setting the frequency division number m0 of the frequency division circuit 130 in accordance with the frequency of the clock signal selected by the clock signal selection circuit 120, together with the clock selection signal 200. Note that the frequency division number control signal 21
0 and the clock selection signal 200 can be shared by considering a combination of digital control signals.

The phase comparison circuit 140 and the voltage controlled oscillation (VC
O) The circuit 150 and the frequency dividing circuit 160 constitute a phase locked oscillator as in the conventional example of FIG. That is, the VCO circuit 150 outputs the in-device clock signal 250 phase-locked to the synchronization source frame signal 230, and the frequency divider 160 generates the in-device frame signal 240 phase-locked to the synchronization source frame signal 230. Here, the frequency dividing circuit 160 variably divides the internal clock signal 250 by mv (mv is a natural number) to generate an internal frame signal 240 having substantially the same cycle (synchronized) as the synchronization source frame signal 230. The phase comparison circuit 140 compares the phase of the in-device frame signal 240 with the phase of the synchronization source frame signal 230, and uses this phase comparison output as the frequency (phase) control output of the VCO circuit 150. Therefore, the dividing number m0 of the dividing circuit 160 and the dividing circuit 1
The division number mv of 60 is interrelated. Conversely, the clock signal selection control circuit 110 can appropriately specify the frequency division number m0 of the frequency dividing circuit 130 when selecting the clock signal, so that the clock signals 201, 202,... , Synchronization source frame signal 25
An in-device frame signal 240 that can be phase-synchronized with 0 can be generated.

Next, an example of the operation of the synchronization source signal switching circuit will be described with reference to FIGS.

Now, the number of clock signals input to the synchronization source signal switching circuit is N = 2, the frequency of clock signal 201 is f1, the frequency of clock signal 202 is f2, and VCO
The frequency of the internal clock signal 250 output from the circuit 150 is defined as fv. In addition, the ratio of each frequency is f1: f
It is assumed that 2: fv = 1: 1: 3. That is, the periods of the clock signals 201 and 202 are the same, and the frequency of the internal clock signal 250 is three times that of the clock signals 201 and 202. Therefore, the dividing number mv of the dividing circuit 160 is 1
5 and the frequency ratio between the clock signals 201 and 202 and the synchronization source frame signal 230 is 1: (１ ／) (see FIG. 2).

First, two clock signals 201 and 20
2 is normal, and the clock selection signal 200 from the clock selection control circuit 110 selects the clock signal 201. At this time, the selected clock signal 220 is the clock signal 101, and the frequency dividing circuit 130 generates the synchronization source frame signal 230 obtained by dividing the frequency of the selected clock signal 220 by five. Phase comparison circuit 140
, The synchronization source frame signal 230 and the in-device frame signal 240 generated by the frequency dividing circuit 160 are input. Here, between the synchronization source frame signal 230 and the in-device frame signal 240, f1 / m1 = f2 / m2 = f
v / mv (m1 and m2 are clock signals 201,
202 represents the frequency division number of the frequency dividing circuit 130 when it is selected). Therefore, the two frame signals 230 and 240 have the same frequency, and the two clock signals 201 and 202 are configured by the phase comparison circuit 140, the VCO circuit 150, and the frequency dividing circuit 160 so as to have a certain unique phase. Is controlled by the phase locked loop.

Next, when the clock signal abnormality detection circuit 101 detects a signal abnormality of the clock signal 201 in the above state, the clock signal abnormality detection circuit 101 sends a clock abnormality signal to the clock signal selection control circuit 110. Then, the clock signal selection control circuit 110 determines that the clock signal 201 is inappropriate as the synchronization source clock, and sends a clock selection signal 200 for switching the clock signal 202 to the selected clock signal to the clock signal selection circuit 120. With this control, the clock signal selection circuit 120 changes the selected clock signal 220 to the clock signal 2
01 to the clock signal 202, and the clock signal selection control circuit 110 simultaneously (clock selection signal 210
(Synchronously with) the dividing number control signal 210 is sent to the dividing circuit 130 to switch the dividing number of the dividing circuit 130 from m1 to m2. In this state, the frequency of the clock signal 201 and the frequency of the clock signal 202 are the same.
The division number of 0 does not change. However, the selected clock signal 2
20 indicates that the phase changes by only the phase difference between the clock signal 201 and the clock signal 202, that is, by a maximum of one clock, as compared with the case where the switching has not occurred. However, this fluctuation amount can be limited to at most one clock cycle.

As described above, even if a signal abnormality occurs in the current clock signal 201, the phase fluctuation of the synchronization source frame signal 230 is minimized by switching the selected clock signal 220 to the clock signal 202 at the clock signal stage. And the phase fluctuation of the in-device frame signal 240 can be reduced. As a result, it is possible to eliminate an error occurrence factor in each signal processing unit processed using the in-device frame signal 240.

Next, in the embodiment of FIG.
Frequency f1 of clock signal 201 and clock signal 202
The operation when the frequency is different from f2 will be described.
In this case, the clock signal selection control circuit 110 synchronizes the frequency division number control signal 210 to the frequency division circuit 130 when the count value of the frequency division circuit 130 including a counter or the like is “0”, and supplies the clock selection signal 200 Is supplied to the clock signal selection circuit 120.

Here, information of the count value "0" of the frequency dividing circuit 130 is transmitted to the frequency dividing circuit 13 by a signal line (not shown).
Since the clock signal is sent from 0 to the clock signal selection control circuit 110, it is possible to switch from the clock signal 201 to the clock signal 202 and to simultaneously switch the frequency dividing circuit 130 to the frequency division number suitable for the clock signal 202.

The clock signal abnormality detecting circuit 101,
, 10N are clock signals 201,
Since the frequency of the corresponding clock signal and its permissible error among 02,..., 20N are stored, it is possible to detect a signal abnormality of the input clock signal. Further, the clock signal selection control circuit 110 controls the clock signals 201 and 20
Since all frequencies 2, 2,..., 20N are stored, it is possible to instruct the frequency dividing circuit 130 on a frequency division number suitable for these frequencies for each clock signal.

In the synchronization source signal switching circuit described later, the switching from the clock signal 201 to the clock signal 202 and the simultaneous switching of the frequency division circuit 130 to the frequency division number suitable for the clock signal 202 start counting the synchronization source frame signal 230. In this case, the phase fluctuation of the synchronization source frame signal 230 can be suppressed as much as possible, and the in-device frame signal 240
Can be suppressed as much as possible. Further, even if the frequency of the input clock signal is different, this synchronization source signal switching circuit does not need to prepare a large number of frequency dividing circuits, and changes the frequency division number of the frequency dividing circuit of the phase synchronous oscillation circuit. Therefore, there is an effect that the circuit configuration is simplified.

[0030]

As described above, the present invention selects and switches one of the normal clock signals among the signals supplied from each of the plurality of transmission paths to generate a frame signal in the apparatus. In the source signal switching circuit, a clock signal selection circuit that selects one of the clock signals to generate a selected clock signal; a first frequency divider that divides the selected clock signal to generate a synchronization source frame signal; A phase-locked oscillation circuit that synchronizes with the synchronization source frame signal and generates an in-device frame signal obtained by dividing the synchronization source frame signal, so that the clock signal can be switched before the synchronization source frame signal is generated. And can be
The phase change at the time of switching occurrence is one cycle of the maximum clock,
There is an effect that the amount of phase change can be reduced as compared with the case where the frame signal itself obtained by dividing the clock signal is to be switched.

Further, even when the frequencies of the clock signals, which are the basis of the synchronization source frame signal, are different from each other, it is possible to cope with the above by changing the frequency division number of the frequency dividing circuit of the phase locked oscillation circuit. This has the effect of being simple.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a synchronization source signal switching circuit according to the present invention.

FIG. 2 is a diagram showing main signals in the embodiment of FIG.

FIG. 3 is a configuration diagram illustrating an example of a synchronization source signal switching circuit according to the related art.

FIG. 4 is a diagram showing main signals in the synchronization source signal switching circuit of FIG. 3;

[Explanation of symbols]

101, 102,..., 10N clock signal abnormality detection circuit 110 clock signal selection control circuit 120 clock signal selection circuit 130 frequency divider 140 phase comparator 150 voltage controlled oscillation (VCO) circuit 160 frequency divider

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-9-93237 (JP, A) JP-A-11-127064 (JP, A) JP-A-2000-286829 (JP, A) JP-A-11-298460 (JP, A) JP-A-63-299543 (JP, A) JP-A-62-138914 (JP, A) JP-A-7-336202 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ H04L 7/00 G06F 1/04 303 H03K 5/00 H04L 7/033

Claims (4)

(57) [Claims] 1. A synchronization source signal switching circuit for selecting and switching a normal clock signal from signals supplied from each of a plurality of transmission paths of a communication network to generate an in-device frame signal , wherein: When an abnormal frequency of the clock signal is detected,
Clock signal abnormality detection circuit that generates a clock abnormality signal
The clock signal abnormality detection circuit is used for the clock signal that is currently in use.
When a frequency abnormality is detected, a plurality of clock signals
Generate a clock select signal that selects the correct one
A clock signal selection control circuit;
A clock signal selecting circuit for selecting one of the clock signals to generate a selected clock signal under control, and a first signal generating a synchronization source frame signal by dividing the frequency of the selected clock signal.
And a phase-locked oscillation circuit that synchronizes with the synchronization source frame signal and generates an in-device frame signal obtained by dividing the synchronization source frame signal. 2. A phase comparison circuit for comparing a phase of the synchronization source frame signal with a phase of the frame signal in the device to generate a comparison output. a voltage controlled oscillator produces a clock signal, the synchronization source signal switching of claim 1, wherein the device clock signal by dividing, characterized in that it comprises a second frequency divider to produce the internal frame signal circuit. 3. When the frequency of the clock signal currently used is abnormal, and the frequency of the newly selected clock selection signal is different from the frequency of the currently used clock signal, the clock signal selection control circuit controls the clock signal. A frequency division number control signal for changing a frequency division number of the second frequency division circuit to a frequency division number at which the in-device frame signal can be synchronized with the synchronization source frame signal at the same time as the transmission of the abnormal signal. 2. The synchronization source signal switching circuit according to claim 1, wherein the signal is supplied to the synchronization source signal. Wherein said clock signal selection control circuit, the synchronization source signal switching circuit according to claim 1, characterized in that stores all the frequencies of a plurality of said clock signal.