JP5742461B2 - Signal transmission device - Google Patents

Description

  The present invention relates to a signal transmission device. In particular, the present invention relates to a TDM signal transmission apparatus that transmits N (N is an integer of 3 or more) channel signals.

  A known E1 signal transmission apparatus in an E1 signal transmission system using PWE3 includes a jitter suppression clock generation circuit for suppressing clock jitter. As many jitter suppression clock generation circuits as the number of E1 signal channels to be transmitted are required.

JP 2000-049841 A JP 2010-035003 A JP 2010-0662703 A

  As described above, the known signal transmission apparatus needs to prepare as many jitter suppression clock generation circuits as the number of channels of the E1 signal to be transmitted, which increases the circuit scale.

  In addition, in order to reduce the circuit scale, when the jitter suppression clock generation circuit is used in common by grouping in units of E1 signals that share the clock source, other causes may occur due to packet failure of the channel used as the reference clock of the jitter suppression generation circuit. The signal also has a problem that affects the E1 signal reproduction.

In order to solve the above-described problem, according to the first aspect of the present invention, a signal transmission apparatus for transmitting a signal of N (N is an integer of 3 or more) channel, the common group information set by the administrator. A common clock selection unit that selects a common channel among the channels, and a normal clock that is synchronized with the clock source from the channels selected by the common clock selection unit. There are provided M (M is an integer greater than or equal to 1 and less than N) clock selection units and M jitter suppression units that suppress the jitter of the clock selected by the clock selection unit.

  In addition, as described above, the summary of the invention does not enumerate all necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  As is apparent from the above description, the present invention can reduce the number of jitter suppression clock generation circuits as compared with known signal transmission apparatuses.

It is a figure showing an example of transmission system 1 concerning one embodiment. It is a figure which shows an example of the block configuration of the E1 signal transmission apparatus. It is a figure which shows an example of the common group information set in a table format. It is a figure which shows an example of the operation | movement flow of the determination process of the normality of an extraction clock. It is a figure which shows an example of the operation | movement flow which selects the grouped clock by "failure information".

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and are combinations of features described in the embodiments. Not all are essential to the solution of the invention.

  FIG. 1 shows an example of a transmission system 1 according to an embodiment. The transmission system 1 is a system that transmits an E1 signal of one channel by PWE3. The transmission system 1 includes an E1 signal transmission device 100 and an E1 signal reception device 200. The E1 signal transmitting apparatus 100 is connected to the E1 signal receiving apparatus 200 via the packet communication network 300.

  The E1 signal transmission apparatus 100 includes a packet termination unit 110, a clock detection unit 120, a failure monitoring unit 130, a jitter suppression clock generation circuit 160, a jitter buffer 180, and an E1 signal transmission unit 190. The E1 signal reception device 200 includes an E1 signal reception unit 210, a failure information generation unit 220, and a packet generation unit 230.

  The E1 signal received by the E1 signal receiver 210 of the E1 signal receiver 200 is encapsulated into a packet by the packet generator 230 and transferred to the packet communication network 300. The failure information generation unit 220 monitors the E1 signal state in the E1 signal reception unit 210, and sends information indicating whether the E1 signal reception is “normal” or “failure” (LOS or LOF) to the overhead during E1 encapsulation. It is added as “Line information”.

  Here, as a method for encapsulating the E1 signal into a packet, MEF8 of MEF (Metro Ethernet (Registered Trademark) Forum) is standardized, and transfer of “line information” of the E1 signal is also “L- It has been proposed to use “bit”.

  In the E1 signal transmission device 100, the packet signal received from the packet communication network 300 is terminated by the packet termination unit 110. Here, the clock extraction unit 120 regenerates the E1 clock from the received data amount of the received packet. Since the jitter due to the transmission data delay in the packet communication network 300 is added to the E1 clock, the jitter suppression clock generation circuit 160 generates a clock with the jitter suppressed, and outputs the clock to the jitter buffer 180. Further, the failure monitoring unit 130 generates “failure information” that indicates a state in which the E1 clock cannot be normally reproduced at the end of the packet by monitoring “line information” added to the packet overhead or by monitoring packet loss. “Failure information” is information indicating the state of clock extraction, and is made into two values, “normal” and “abnormal”. The jitter suppression clock generation circuit 160 has a holdover function, and this “fault information” = “abnormal” is set. When received, the hole holding function outputs a clock maintaining the previous clock accuracy to the jitter buffer 180. The jitter buffer 180 is a memory that accumulates E1 data to absorb packet arrival delay, and outputs the E1 signal to the E1 signal transmission unit 190 using the jitter-suppressed clock from the jitter suppression clock generation circuit 160.

  The above is the description of the device configuration for encapsulating the E1 signal into the packet signal and transmitting it through the packet network. FIG. 2 shows a plurality of (5 channels) E1 signals encapsulated on the E1 signal transmitting device 100 side. In the case of receiving a packet signal, the configuration is such that E1 signals having the same timing are grouped and the jitter suppression clock generation circuit 160 is reduced.

  Next, FIG. 2 will be described. FIG. 2 shows only the configuration in which the jitter suppression clock generation circuit reduction is performed in the E1 signal transmission apparatus 100 on the TDM signal transmission side among the configurations in which the E1 transmission is performed by the PWE3 illustrated in FIG.

  First, the packet termination units 110a-e, clock extraction units 120a-e, failure monitoring units 130a-e, jitter buffers 180a-e, and E1 signal transmission units 190a-e have the same functions shown in FIG. In order to transmit the 5-channel E1 signal, it has five functional blocks.

  The jitter suppression clock generation circuits 160a and 160b have the same function as the jitter suppression clock generation circuit 160 of FIG. 1, but in the device configuration that handles five channels, the circuit configuration is reduced from five to two. ing.

  The common clock group selection unit 140 selects “E1 clock” and “failure information” of CH1 to CH5 in the clock selection units 150a and 150b based on “common group information” set from a control terminal (not shown). And transfer. The clock selection units a and b select a normal clock from a plurality of “E1 clocks” according to “failure information”, and output the selected clocks to the jitter suppression clock generation circuits 160 a and 160 b. When all of the plurality of selected clocks are not normal, “failure information” is transferred to set the holdover state.

  The generated clock distribution unit 170 distributes the “E1 clock” of the jitter suppression clock generation circuits 160a and 160b to the jitter buffers 180a to 180e based on “common group information” set from a control terminal (not shown).

  In the present invention, E1 signals having a common clock source are grouped, and the jitter suppression clock generation circuit is commonly used to reduce the number of jitter suppression clock generation circuits. In the channel of the grouped E1 signal, A clock is selected by monitoring whether or not a packet that can be recovered from a clock is received, so that even if an abnormality occurs in the transmission of the grouped E1 signal, no problem occurs in the clock recovery.

This operation is (1) operation for grouping E1 signals that are common clock sources (2) normality of extracted clock ("failure information" generation)
(3) The operation will be described by dividing the grouped clocks into operations for selecting them according to “failure information”.

(1) Grouping operation of E1 signal First, for the signals of CH1 to CH5 in FIG. 2, for example, when CH1 to CH3 are E1 signals of a common clock source and CH4 and 5 are E1 signals of a common clock source, the device manager However, it is necessary to set “common group information” as shown in FIG. 3 from a control terminal (not shown).

  In the common clock group selection unit 140, the “E1 clock” and “failure information” of CH1, CH2, and CH3 are transferred to the clock selection unit 150a based on the “common group information” in FIG. “E1 clock” and “failure information” of CH4 and CH5 are transferred.

  In the generated clock distribution unit 170, the E1 clock from the jitter suppression clock generation circuit 160a is distributed to the jitter buffers 180a to 180c of CH1, CH2, and CH3 based on the “common group information” in FIG. The E1 clock from the circuit 160b is distributed to the jitter buffers 180d and e of CH4 and CH5.

(2) Determination of normality of extracted clock ("Fault information" generation)
The E1 signals are grouped to reduce the jitter suppression clock generation circuit. Of the grouped signals, the clock source E1 signal input to the jitter suppression clock generation circuit has a line fault (“LOS”, “LOF”). In a state where packet loss occurs in the packet network, the clock is not a normal clock, and an error may occur in other channel signals. Here, the normal clock means a clock synchronized with the timing of the E1 signal. For this reason, in order to determine whether the grouped clocks are normal clock signals, the failure monitoring units 140a to 140e determine the normality of the extracted clocks and generate “failure information”.

  The “failure information” is generated by performing the determination processing shown in the flowchart of FIG. 4 based on the “line failure” added to the overhead of the packet terminated by the packet termination units 110a to 110e and the packet reception state, Is generated. The “packet loss above a certain level” shown in FIG. 4 means that a packet loss of several packets does not affect the normality of clock extraction, but if a packet loss above a certain level occurs, normal clock extraction cannot be performed. Therefore, the number of packet losses at which normal clock extraction cannot be performed is determined. Since the relationship between the packet loss failure and the normality of clock extraction here is not an essential part of the present invention, it is simply described.

(3) Operation for selecting grouped clocks based on “failure information” An example of clock recovery for group 1 will be described. In the clock selection unit 150a, as described above, “E1 clock” and “failure information” of CH1 to CH3 are selectively transferred. Based on the “failure information”, the clock selection unit 150a operates according to the flowchart shown in FIG. 5 to select “E1 clock” and generate “failure information”.

  For example, when all the “failure information” of CH1 to CH3 is “normal”, the determination in step S101 is “Y”, and the processing shown in step S102 is performed. The circuit operation depends on "." From this state, when “failure information” of CH1 becomes “abnormal”, “N” is determined in step S101, and “Y” is determined in the next step S103, and the process shown in the process of step S104 In the jitter suppression clock generation circuit 160a, the circuit operation depends on the “E1 clock” of CH2.

  As described above, the present invention has the following effects. The jitter suppression clock generation circuit is generally composed of a PLL circuit, but the circuit scale can be reduced by the present invention. For example, when transmitting TDM signals for 128 channels, it is necessary to design a printed circuit board on which 128 PLL circuits are mounted. However, the clock sources for the 128 channels of E1 signals are 16 sets of common clocks. In this case, since it is sufficient to design with 16 PLL circuits, the area of the printed circuit board design can be reduced to 1/8.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

100 E1 signal transmission device 110 packet termination unit 120 clock detection unit 130 failure monitoring unit 140 common clock group selection unit 150 clock selection unit 160 jitter suppression clock generation circuit 170 generated clock distribution unit 180 jitter buffer 190 E1 signal transmission unit 200 E1 signal reception Device 210 E1 Signal Receiving Unit 220 Fault Information Generation Unit 230 Packet Generation Unit 300 Packet Communication Network

Claims (2)

N (N is an integer greater than or equal to 3) channel signal transmission device,
Based on the common group information set by the administrator, among the channels, a common clock selection unit that selects a common channel of the clock source,
M (M is an integer less than or equal to 1 and less than N) clock selection units that select one normal clock synchronized with the clock source from the channels selected by the common clock selection unit ;
A signal transmission apparatus comprising: M jitter suppression units that suppress jitter of a clock selected by the clock selection unit. Fault monitoring unit that monitors line information added to packet overhead at the end of the packet
Further comprising
The common clock selection unit selects the failure information of a channel having a common clock source, and transfers the failure information to the clock selection unit.
The signal transmission device according to claim 1.

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