KR20020005830A - Apparatus for clock synchonization between dualized STM-N signal interface cards - Google Patents

Abstract

PURPOSE: A clock synchronizing apparatus between doubled interfaces of synchronous transport module is provided to decrease data loss or link obstruction by synchronizing phase of transport clock between each interfaces in case that card interfacing synchronous transport module N signal in a synchronous digital hierarchy. CONSTITUTION: A clock generating portion(21A) generates clock for interfacing synchronous transport module(STM) N signal to output phase control terminals of the pertinent board. A doubled control portion(22A) makes an identification of a doubled state information whether the pertinent board is in an active state or in a waiting state. A clock output(23A) outputs any one between clock output from the phase control terminals and clock transferred from phase control terminals of the other board. The phase control terminals synchronizes the clock signal from the clock generating portion with the clock signal from th other board to output into the clock output.

Description

Apparatus for clock synchonization between dualized STM-N signal interface cards}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface of a synchronous optical hierarchy (SDH system), and in particular, when a card for interfacing a signal of a synchronous transport module (hereinafter referred to as STM) is redundant, a transmission clock between each interface card. The present invention relates to a clock synchronization device between dual interface cards of a synchronous transmission module suitable for reducing data loss or link failure when switching clock signals.

In general, SDH systems will process signals according to the ITU-T standard of the International Telecommunication Union. In other words, asynchronous signals are received, mapped, aligned, pointer processed, and multiplexed to form and transmit STM-1 signals of the STM series, or STM-N signals are formed through subsequent multiplexing to transmit to the other station through the optical transmission path. .

In this SDH system, the interface card for interfacing the STM-N signal is redundantly operated to prevent signal switching. That is, it is provided with an operating STM-N interface card and the standby STM-N interface card.

Therefore, the phase of the drive clock must be synchronized between the redundant STM-N interface cards of the SDH system.

Hereinafter, a clock synchronization method of a redundant STM-N interface card of the SDH system according to the present invention will be described.

First, Figure 1 is a block diagram of a redundant STM-1 interface card of the SDH system according to the prior art.

As shown in FIG. 1, the conventional apparatus generates a clock for interfacing an STM-1 signal and outputs the clock to the clock output unit 13A of the corresponding board and the clock output unit 13B of the other board, respectively. Part 11A; A redundancy control unit 12A for checking the duplication state information indicating whether the board is active or in a standby state and controlling the clock output for the interface of the clock output unit 13A; According to the control signal of the redundancy control unit 12A, the clock input unit 13A outputs a clock input from the clock generation unit 11A or a clock received from the clock generation unit 11B of another board as an interface clock. It is composed.

The above configuration relates to one of the duplicated interface cards, and the configuration of the other end of the interface card is the same as that described above.

The operation of the device configured as described above is as follows.

Conventionally, a clock is generated from each STM-1 interface card. The generated clock is transferred to the partner interface card to share the clock. That is, the stand-by interface card receives a clock transmitted from an active interface card and operates according to the received clock.

In more detail, each clock generator 11A or 11B included in the redundant STM-1 interface card generates a clock signal for the interface of the STM-1 signal. The generated clock output by each STM-1 interface card is simultaneously transmitted to the clock outputs 13A and 13B of the board and the other board.

At this time, since one of the duplicated STM-1 interface cards operates in the active state and the other end operates in the standby state, each of these interface cards exchanges redundancy state information indicating the operation state of the corresponding card and the other card. .

Redundancy status information exchanged between each STM-1 interface card allows you to determine which board generated clocks will be used to interface the STM-1 signals. That is, the redundancy control unit 12A, 12B receives the redundancy state information to check which board is operating in an active state.

For example, when the first STM-1 interface card operates in an active state, the redundancy control unit 12A of the first STM-1 interface card prevents the output of the clock received from the second STM-1 interface card while the clock is prevented. The clock output section 13A is controlled to output the generation clock of the generation section 11A as the clock for the interface.

In the case of the above example, in the second STM-1 interface card operating in the standby state, the redundancy control unit 12B controls the clock output unit 13B using the transmission control signal. Thus, the clock output unit 13B uses the clock received from the clock generation unit 11A of the first STM-1 interface card as the clock for the interface of the STM-1 signal, not from the clock generation unit 11B of the board. Will print.

Therefore, since the clock signal generated by the active card among the duplicated STM-1 interface cards is used for the card operating in the standby state, the interface clocks output from the respective STM-1 interface cards coincide with each other.

The STM-1 interface card operating in the standby state is switched to the active state due to the switching of a specific card or the detachment of the card operating in the active state. When only one STM-1 interface card is operated as described above, the redundancy control unit 12A and 12B outputs the clock generated by the clock generation units 11A and 11B of the board as the clock for the interface. 13B). In this case, it is not necessary to consider the reception clock from another board.

However, the conventional apparatus described above has a problem in that clocks generated by an interface card in an active state and an interface card in a standby state have the same frequency but a phase difference occurs between them.

That is, if the state of the interface card is changed due to switching of a specific card in a redundant STM-1 interface device, a phase difference is caused in the interface clock of the STM-1 signal according to the change of the clock generation source, resulting in signal frame or data loss. There was a problem that occurred.

In particular, there is a limitation in that a phenomenon in which the amount of data loss increases with the magnitude of the phase difference between clocks for an interface occurs.

Therefore, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to synchronize the phase of the transmission clock between each interface card when the card that interfaces the STM-N signal in the SDH system is duplicated. The present invention provides a clock synchronization device between dual interface cards of a synchronous transmission module, which is suitable for reducing data loss and link failure when switching clock signals.

In order to achieve the above object, the clock synchronization device of the dual interface card of the synchronous transmission module according to the present invention generates a clock for interfacing the STM-N series signals and outputs the clock to the phase control terminal of the board. Wealth; A redundancy control unit which checks redundancy state information indicating whether the board is active or in a standby state and controls a clock output for the interface of the clock output unit; A clock output unit configured to output one of a clock output from the phase control terminal and a clock transmitted from a phase control terminal of another board according to a control signal of the redundancy control unit as an interface clock; Technical features of the present invention include a phase control stage for synchronizing a clock signal generated by the clock generator with a clock signal transmitted from another board and outputting the clock signal to the clock output unit.

1 is a block diagram of a redundant STM-1 interface card of a conventional SDH system,

2 is a block diagram of a clock synchronization device between dual interface cards of a synchronous transmission module in an SDH system according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21A, 21B: clock generator 22A, 22B: redundancy controller

23A, 23B: clock output section 24A, 24B: phase comparison section

25A, 25B: Phase control unit

Hereinafter, the configuration and operation of the present invention will be described in detail according to an embodiment of the present invention of the apparatus for synchronizing the clock between the dual interface cards of the synchronous transmission module.

First, FIG. 2 is a block diagram of a clock synchronization device between dual interface cards of a synchronous transmission module in an SDH system according to an embodiment of the present invention.

As shown in FIG. 2, a preferred embodiment of the present invention includes a clock generator 21A for generating a clock for interfacing the STM-1 signal and outputting the clock to the phase control stages 24A and 25A of the board; A redundancy control unit 22A for checking the duplication state information indicating whether the board is active or in a standby state and controlling the clock output for the interface of the clock output unit 23A; A clock outputting one of a clock output from the phase control stages 24A and 25A and a clock transmitted from the phase control stages 24B and 25B of another board as an interface clock according to a control signal of the redundancy control unit 22A. An output section 23A; Phase control stages 24A and 25A output the clock signal generated by the clock generator 21A to the clock output unit 23A by synchronizing the clock signal transmitted from another board.

The phase control stages 24A and 25A compare phases of the clock generated by the clock generator 21A of the corresponding board with the phases of the received clocks transmitted from other boards, and compares the phase comparison information indicating the phase difference between the clock signals. A phase comparator 24A for outputting to 25A; Receives the phase comparison information output from the phase comparator 24A, synchronizes the phase of the generated clock of the clock generator 21A of the corresponding board with the phase of the received clock received from another board, and the phase synchronized clock signal. It consists of a clock control section 23A of the board and the phase control section 25A for transmitting to the phase control stages 24B and 25B of the other board.

The above configuration relates to one end of the redundant STM-1 interface card, and the same applies to the other end of the interface card.

The operation of the device configured as described above is as follows.

In the present invention, phase control stages 24A and 25A and 24B and 25B are provided for synchronizing phases between clock signals generated in the duplicated STM-1 interface cards. Thus, the phase control stages 24A, 25A, 24B, 25B synchronize the phases of the clock signals generated on the boards according to the phases of the clock signals received from other boards to prevent data loss that may occur during card switching. do.

In other words, each STM-1 interface card generates a clock. The clock is shared by transmitting the generated clock to the counterpart interface card. The stand-by interface card receives a clock transmitted from an active interface card and operates according to the received clock. .

In more detail, each clock generator 21A or 21B included in the redundant STM-1 interface card generates a clock signal for interfacing the STM-1 signal. The generation clock of each STM-1 interface card is transmitted to the phase control stages 24A and 25A 24B and 25B of the board, unlike the prior art.

At this time, one of the duplicated STM-1 interface cards operates in the active state and the other end operates in the standby state, and each of these interface cards exchanges redundancy state information indicating the operation state of the corresponding card and the other card. .

Redundancy status information exchanged between each STM-1 interface card allows you to determine which board generated clocks will be used to interface the STM-1 signals. That is, the redundancy control unit 22A, 22B receives the redundancy state information to check which board is operating in an active state.

For example, when the first STM-1 interface card operates in an active state, the redundancy control unit 22A of the first STM-1 interface card prevents the output of the reception clock received from the second STM-1 interface card. The clock output section 13A is controlled to output the clock signal output from the phase control stages 24A and 25A as the interface clock.

In the case of the above example, in the second STM-1 interface card operating in the standby state, the redundancy control unit 22B controls the clock output unit 23B using the transmission control signal. Therefore, the clock output section 13B outputs the clock received from the phase control stages 24A and 25A of the first STM-1 interface card as the interface clock of the STM-1 signal.

Therefore, since the clock signal generated by the active card among the duplicated STM-1 interface cards is used for the card operating in the standby state, the interface clocks output from the respective STM-1 interface cards coincide with each other.

In particular, the phase control stages 24A, 25A, 24B, 25B are provided with phase comparators 24A, 25A, and phase controllers 24B, 25B, and clock generators 21A, 21B of each interface card. You will receive a generated clock of. At this time, since the reception clocks of other interface cards are not input to each STM-1 interface card, each phase comparator 24A or 24B does not output phase comparison information. Therefore, the phase controllers 25A and 25B transfer the clock signal input from the clock generators 21A and 22B to an interface card different from the clock output units 23A and 23B.

The phase comparator 24B of the second interface card in the standby state by the above operation receives the clock signal from the phase controller 25A of the first interface card in the active state, and the phase and clock generator 21B of the reception clock are received. Phases of the generated clocks are compared to generate phase comparison information indicating the phase difference. The phase comparison information is transmitted to the phase controller 25A, and the phase controller 25A synchronizes the phase of the reception clock and the phase of the generation clock according to the phase comparison information.

Thus, the phases of the interface clock output from the active interface card and the interface clock output from the standby interface card coincide. When there is a change in the active / standby state of each interface card due to a change of a specific interface card, the interface card which is switched from the standby state to the active state outputs the clock signal generated from the board as the interface clock.

Thus, according to the present invention, the redundant STM-1 interface card includes a phase comparator and a phase control unit, so that the standby interface card receives a clock signal synchronized with the phase of the clock signal generated by the active interface card. Will be able to print.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. That is, the clock source may be applied to all interface cards that are located in the board and are duplicated and operated, and the interface card is not limited to a card that interfaces a specific SDH signal hierarchy.

Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the clock synchronization device between the dual interface cards of the synchronous transmission module according to the present invention is output from the card operating in the active state and the card operating in the standby state among the interface cards of the duplicated STM-N series signals. By synchronizing the phases of the clocks, the same effect as using the same clock source is achieved.

Therefore, when the active / standby state of the interface card changes due to a change of a specific card, a phase difference is caused to the interface clock of the STM-N series signal due to the change of the source of the conventional clock, thereby overcoming the problem of signal frame or data loss. In addition, by enabling the stable supply of the clock for the interface of the STM-N series signal has the effect of preventing data loss.

Claims (2)

A clock generation unit generating a clock for interfacing the STM-N series signals and outputting the clock to a phase control terminal of a corresponding board; A redundancy control unit which checks duplication state information indicating whether the board is active or in a standby state and controls a clock output for an interface of the clock output unit; A clock output unit configured to output one of a clock output from the phase control terminal and a clock transmitted from a phase control terminal of another board according to a control signal of the redundancy control unit as an interface clock; And a phase control stage for synchronizing the clock signal generated by the clock generator to a clock signal transmitted from another board and outputting the clock signal to the clock output unit. The method of claim 1, wherein the phase control stage, A phase comparator for comparing phases of a clock generated by the clock generator of the corresponding board with a phase of a reception clock transmitted from another board and outputting phase comparison information indicating a phase difference between the clock signals to a phase controller; Receives the phase comparison information output from the phase comparator, synchronizes the phase of the clock generated by the clock generator of the board with the phase of the received clock received from another board, and synchronizes the phase-locked clock signal with the clock output of the board. And a phase controller for transmitting to a phase control stage of a different board.