KR100492891B1 - Apparatus For Selecting Reference Clock In The RAM System - Google Patents

Abstract

The present invention selects one reference clock from among different reference clocks input as the RAM (Remote Access Module) directly interworks with a local exchange, an Asynchronous Transfer Mode (ATM) network, or an Internet Protocol (IP) network. A reference clock selection device in a RAM system that can generate and supply its own system clock.

The present invention implements a reference clock selection device that selects one of different reference clocks as a reference reference clock in a RAM system, so that one reference clock that is a reference among various reference clocks can be flexibly selected and used as a system clock. This makes it possible to generate and supply system clock and frame sync signals with only one PLL circuit without having to implement a phase locked loop (PLL) circuit on each board in the system, thereby reducing the overall system implementation cost. do.

In addition, the present invention generates and supplies a system clock and frame synchronization signal in one PLL circuit, thereby directly interoperating with various network sources through board expansion or flexible board mounting.

Description

Apparatus For Selecting Reference Clock In The RAM System}

The present invention relates to a reference clock used in a RAM (Remote Access Module), and in particular, by selecting one reference clock among different reference clocks input as the RAM system directly interworks with a local exchange, an ATM network, or an IP network. A reference clock selection device in a RAM system that can generate and supply its own system clock.

Recently, a total access module (TAM) system has been developed to efficiently handle voice and data traffic for PSTN / ISDN (Public Switched Telephone Network / Integrated Service Digital Network) subscribers and high-speed xDSL subscribers. As shown in FIG. 1, PSTN / ISDN / xDSL subscribers are accommodated locally and remotely to provide voice and data integration services, but local subscribers (typically within 4 km) It is directly accommodated in the TAM system and provides communication services with PSTN / ISDN subscribers, which are LE subscribers, through interworking with local exchanges using E1 / T1 matching, and remote subscribers (Remote Access Modules), which are remote systems. Accept through the system.

At this time, the RAM system interworks with the TAM system using STM-1 matching, and provides a communication service by interworking with a local exchange and an Asynchronous Transfer Mode (ATM) network through a corresponding TAM system.

Meanwhile, the RAM system described above uses an STM-1 link to interwork with a TAM system, and the SPCC board, which is a system control board, extracts a reference clock from a corresponding STM-1 link to generate its own system clock and frame synchronization signal. After supplying it to the lower boards, there was a problem in that it could not be directly linked with a local exchange or an ATM network.

In other words, the conventional RAM system provides only the STM-1 matching with the TAM system, which is the upper system. Therefore, the reference clock must be extracted from the STM-1 link to generate the system clock and frame synchronization signals that can synchronize the system itself. Therefore, it could only accommodate remote subscribers and interwork with local exchanges, ATM networks, or IP networks through the TAM system, but the network sources (eg, local exchanges, There is a problem in that the system function is limited because it does not consider the case where it can directly interwork with ATM network, IP network, FLC, etc.).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to implement a reference clock selection device capable of selecting any one of different reference clocks as a reference reference clock in a RAM system, and thereby, reference among various reference clocks. One reference clock can be chosen flexibly to be used as the system clock.

Another object of the present invention is to select one of the various reference clocks as a reference reference clock so that one PLL circuit can generate and supply a system clock and frame synchronization signal without implementing a PLL circuit on each board in the system. To reduce the overall system implementation cost.

It is still another object of the present invention to generate and supply a system clock and frame synchronization signal in one PLL circuit so that various network sources can be directly interlocked through board expansion or flexible board mounting.

A feature of the present invention for achieving the above object is, in a RAM system directly interworking with various network sources through a network interworking board, mounted in the system using priority information preset according to the system environment A priority comparison unit for assigning priorities to different reference clocks input from a plurality of reference clock sources such as a network synchronization board or a network interworking board; A state determination unit which checks the states of the respective reference clock sources and outputs a selection signal for one reference clock having the highest priority according to the priority given by the priority comparison unit; The reference clock is selected as the reference clock according to the selection signal output from the state determination unit, and the reference clock is transmitted to the PLL circuit unit which generates and supplies a system clock and frame synchronization signal to the boards mounted in the system. It is an object of the present invention to provide a reference clock selection apparatus in an RAM system including a clock selection unit.

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At this time, the state determination unit outputs a selection signal for the reference clock input from the board having the highest priority when the boards serving as the reference clock sources are duplicated, but checks the active signal and receives the reference clock input from the active board. And outputting a selection signal for.

The priority comparison unit may assign a highest priority to select a clock input from the network synchronization board as a reference clock when the network synchronization board is mounted among a plurality of reference clock sources mounted in the system. Also, if the network synchronization board is not installed among the boards that are the multiple reference clock sources installed in the system, the highest priority is given to select the clock input from the highest priority board among the network interlocking boards as the reference clock. Characterized in that.

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The priority comparison unit may be configured to give a highest priority to select a clock input from a corresponding board as a reference clock when a specific clock source selection command is input.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, as shown in FIG. 2, when an access gateway RAM system directly interoperates with network sources such as a local exchange, an ATM network, or an IP network through board expansion or flexible board mounting, the accompanying drawings As shown in FIG. 3, a reference clock of a specific board is selected in the system control board 30 to generate and supply a system clock and frame synchronization signal required for each board and bus. The implemented reference clock selection device 40 includes a clock selection unit 41 and a phase locked loop (PLL) circuit unit 42 as shown in FIG. 4.

3 is a diagram illustrating a board mounting state of a RAM system according to the present invention, wherein an ATM board 31, an ATM rear board 32, and a V5.2 board 33 are interworked with a network source. As a reference, the reference clock (19.44MHz or 2.048MHz) extracted through its own network is transferred to the system control board 30, but the network synchronization board NES (NEtwork Synchronization) board 34 is installed if applicable The reference clock is also transmitted to the NES board 34. Here, the ATM rear board 32 refers to an E1 matching board mounted on the rear of the same position when the ATM board 31 is mounted.

At this time, the NES board 34 transfers the reference clock (16.384MHz) necessary for switching to the system control board 30 by using the reference clocks input from the respective network interworking boards 31 to 33.

In addition, the system control board 30 is a Main Controller & Maintenance Card (MCMC) board in charge of the Plain Old Telephone Service (POTS) subscriber control and switching function, and the NES board 34 and the network interworking boards 31 to 33. Select one reference clock that is the highest priority among the different reference clocks input from the system, and the system clock and frame sync signal (16.384MHz, 8KHz) required for each board (31 ~ 37) and bus in the system (16.384MHz, 8KHz). And a reference clock selection device 40 for generating and supplying a LA bus (4.096 MHz, 8 KHz; HT bus). Here, LA-bus is a bus for the interface with the POTS subscriber, HT-bus means an internal bus that is connected to each network interworking board (31 ~ 33) interworking with external network sources.

In addition, in FIG. 3, the POTS board 35 and the xDSL board 36 are subscriber boards, and POTS subscribers or ADSL / VDSL subscribers, which are general telephone subscribers, are connected to each other. In addition, a line test and a dedicated line board 37 are mounted. Can be.

On the other hand, the clock selector 41 and the PLL circuit section 42 constituting the reference clock selector 40 in FIG. 4 will be described in more detail. The clock selector 41 includes the NES board 34 in the system. B. Based on whether the network interlocking boards 31 to 33 are mounted, one of the different reference clocks inputted from the corresponding boards is selected as the reference clock as the reference clock, and the currently active board is selected. The reference clock input from the reference clock is selected, and the PLL circuit section 42 generates and supplies a system clock and frame synchronization signal required for each board and bus in the system using the reference clock selected by the clock selector 41.

Here, the clock selector 41 for selecting any reference clock as the highest priority will be described in more detail with reference to FIG. 5. The priority comparator 41-1 and the state determiner 41 -2) and reference clock selector 41-3.

The priority comparison unit 41-1 is inputted from each board serving as a predetermined reference clock source, that is, the NES board 34 and the network interworking boards 31 to 33 using priority information preset according to a system environment. Priority is given to different reference clocks, but the highest priority is given to a corresponding reference clock when a specific clock source selection command is input from an upper processor.

The state judging unit 41-2 checks the states of the respective reference clock sources, and the selection signal for the reference clock having the highest priority according to the priority given to each reference clock by the priority comparing unit 41-1. Outputs a selection signal for the reference clock that is the highest priority among the reference clocks that are currently active and normal.

The reference clock selector 41-3 selects the corresponding reference clock according to the selection signal output from the state determiner 41-2 and transfers the reference clock to the PLL circuit unit 42.

The operation of the reference clock selection device 40 implemented in the above-described RAM system can be described separately according to whether the NES board 34 and the network interworking boards 31 to 33 are mounted. 34) is a redundancy concept, and is implemented by two (A, B) units and delivers active signals and reference clocks.The priority for selecting reference clocks depends on the system structure design. Assume that the board 34, ATM board 31, and V5.2 board 33 in the order.

First, when the NES board 34, which is a network synchronization board, is mounted and operates normally, that is, when an active signal and a reference clock are input from the redundant NES board 34, the corresponding NES board 34 has the highest priority. Since it is a board having a network, the reference clock (16.384MHz) input from the NES board 34 is selected as a reference clock for generating a system clock and a frame synchronization signal regardless of whether other network interworking boards 31 to 33 are mounted. Done.

Second, when the NES board 34 having the highest priority is not mounted or does not operate normally, the reference clock is selected depending on whether the network interworking boards 31 to 33 are mounted. After checking the active signals input from each network interworking boards 31 to 33, the network interworking boards that are normally duplicated are extracted, and the network interworking boards having the highest priority among the corresponding network interworking boards 31 to 33. The reference clock input from the reference clock is selected as a reference clock for generating a system clock and a frame synchronization signal.

For example, as shown in FIG. 6, when the NES board 34 is normally duplicated, a corresponding NES board is input when an '(0,1)' or (1,0) 'active signal and a reference clock are input. Since 34 is the board having the highest priority, the system clock and the frame synchronization signal are generated from the reference clock (16.384 MHz) input from the NES board 34 regardless of whether other network interworking boards 31 to 33 are mounted. The reference clock to select is selected.

If the '(0,0)' or (1,1) 'active signal is input as the NES board 34 is not mounted or does not operate normally, the next highest priority ATM board 31 is used. If the '(0,1) or (1,0)' active signal and reference clock are input from the ATM board 31, another network interworking board, that is, a V5.2 board ( The reference clock (19.44 MHz) input from the corresponding ATM board 31 is selected as the reference clock for generating the system clock and the frame synchronization signal regardless of whether the ATM board 31 is mounted or not. When the ATM rear board 32 is mounted on the rear side, among the reference clocks (19.44 MHz / 2.048 MHz) input from the ATM board 31 or the ATM rear board 32 according to a separate transmission rate selection signal (RATE_SEL). Any one reference The clock is selected as the reference clock for generating the system clock and frame synchronization signal.

In addition, when the '(0,0) or (1,1)' active signal is input because neither the NES board 34 nor the ATM board 31 is mounted or does not operate normally, the next priority is given. The reference clock (2.048 MHz) inputted from the lowest V5.2 board 33 is selected as the reference clock for generating the system clock and frame synchronization signal.

In addition, in the reference clock operation according to the above-described embodiment, when a specific clock source selection command is input from an operator, the reference clock corresponding to the corresponding operator's command is generated regardless of the priority given above. It is selected as the reference clock for generating the synchronization signal.

On the other hand, in the present invention, the reference clock selection device 40 checks the active signal input from each of the boards 31 to 34, and as a result, the NES board 34, the ATM board 31, or the V5.2 board 33 If duplexing does not work normally, that is, if both boards are redundant (ACT) or standby (STBY), alarm information corresponding to them can be output. Even if it is implemented, if only the reference clock source is input, it is selected to generate the system clock and frame synchronization signals.

In addition, the embodiments according to the present invention are not limited to the above-described embodiments, and various alternatives, modifications, and changes can be made within the scope apparent to those skilled in the art.

As described above, the present invention implements a reference clock selection device for selecting any one of different reference clocks as a reference reference clock in a RAM system, thereby flexibly selecting one reference clock among various reference clocks to provide a system clock. It can be used as.

In addition, the present invention selects one of the various reference clocks as a reference reference clock, thereby enabling the generation and supply of a system clock and frame synchronization signal using only one PLL circuit without implementing a PLL circuit on each board in the system. Therefore, the overall system implementation cost can be reduced.

In addition, the present invention generates and supplies a system clock and frame synchronization signal in one PLL circuit, thereby directly interoperating with various network sources through board expansion or flexible board mounting.

1 is a diagram illustrating an interworking structure of a conventional TAM system and a RAM system.

2 is a diagram illustrating a case where a RAM system according to the present invention is directly linked with a local exchange, an ATM network, or an IP network.

3 is a diagram illustrating a board mounted state of a RAM system in FIG. 2;

FIG. 4 illustrates a reference clock selection device implemented in the system control board of FIG. 3. FIG.

FIG. 5 is a diagram showing a detailed configuration of a clock selector in FIG. 4; FIG.

6 is a diagram illustrating an active signal of an NES board and a network interworking board for explaining the operation of the reference clock selection device according to the present invention;

Explanation of symbols on main parts of the drawing

31: ATM board 32: ATM rear board

33: V5.2 board 34: NES board

35: POTS Board 36: xDSL Board

37: line test and dedicated line board 40: reference clock selector

41: clock selector 41-1: priority comparer

41-2: state determining unit 41-3: reference clock selecting unit

42: PLL circuit part

Claims (8)

In a RAM system that works directly with various network sources through a network interworking board, Priority is given to different reference clocks inputted from a board which becomes a plurality of reference clock sources such as a network synchronization board or a network interworking board mounted in the system using priority information preset according to the system environment. A priority comparison unit; A state determination unit which checks the states of the respective reference clock sources and outputs a selection signal for one reference clock having the highest priority according to the priority given by the priority comparison unit; The reference clock is selected as the reference clock according to the selection signal output from the state determination unit, and the reference clock is transmitted to the PLL circuit unit which generates and supplies a system clock and frame synchronization signal to the boards mounted in the system. A reference clock selection device in an RAM system comprising a clock selection unit. delete The method of claim 1, The state determination unit outputs a selection signal for the reference clock input from the board having the highest priority when the boards serving as the reference clock sources are duplicated, and checks the active signal to receive the reference clock input from the active board. A reference clock selection device in an ATM system, characterized by outputting a selection signal. The method of claim 1, The priority comparison unit may assign the highest priority to select a clock input from the network synchronization board as a reference clock when a network synchronization board is mounted among a plurality of reference clock sources mounted in the system. A reference clock selection device in an RAM system. The method of claim 1, The priority comparison unit has a highest priority to select a clock input from a board having the highest priority among network interworking boards as a reference clock when a network synchronization board is not mounted among a plurality of reference clock sources mounted in a system. A reference clock selection device in an RAM system, characterized in that to provide a. delete The method of claim 1, And the priority comparison unit assigns a highest priority to select a clock input from a corresponding board as a reference clock when a specific clock source selection command is input. delete