KR100383234B1 - Apparatus for suppling network timing reference/TCM-ISDN timing reference clock in DSLAM system - Google Patents

Abstract

The present invention provides a DSLAM for supplying phase coincidence and redundant clocks to the ATU at the Central Office end (ATU-C) of the system so that both network timing reference (NTR) and TCM (ISM timing reference) can be used in common. The present invention relates to an NTR / TTR clock supply apparatus in a system, which implements a concentrator backboard and a modem self-backboard, wherein a reference clock (NTR: 8 kHz, TTR: 400 Hz) and a system clock (19 MHz) are provided in the concentrator backboard. It provides a network termination system for smooth video service, and also doubles the NTR / TTR clock supply to prevent clock interruption due to board switching and to provide stable clock supply.

Description

Entity / supply network timing reference / TCM-ISDN timing reference clock in DSLAM system}

The present invention relates to an NTR / TTR (network timing reference / TCM-ISDN timing reference) clock supply apparatus in an Asymmetric Digital Subscriber Line (ADSL) digital subscriber line access multiplexor (DSLAM) system. The NTR / TTR clock supply in a DSLAM system is designed to provide a phase-matched and redundant clock to the system's ATU at the Central Office end (ATU-C) so that both NTR and TTR can be used in common.

In general, ADSL DSLAM system is a system that provides a high-speed data service using the existing copper wire while being located in the switching center (telephone station).

The conventional DSLAM system does not supply NTR / TTR (network timing reference / TCM-ISDN timing reference), which is a reference clock, to ATU-C. In this case, high-speed data service is possible.

However, in recent years, on-demand video services (VOD) and high-speed LAN (LAN) services are required as well as high-speed Internet.

In this case, when the data transmitted is a video, ATU-C can perform a smooth video service only when the clock for the synchronization signal is provided. In the related art, since there is no device that supplies the clock for synchronization to the ATU-C, the ATU-C is a conventional DSLAM system. In the case of serving video data to C, data disconnection occurs.

Accordingly, the present invention has been proposed to solve various problems occurring in the video data service in the conventional DSLAM system as described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide an NTR / TTR clock supply apparatus in a DSLAM system for supplying phase coincidence and redundant clocks to the ATU at the Central office end (ATU-C) of the system so that NTR and TTR can be used in common. There is.

More specifically, the DSLAM system provides the reference clock (NTR: 8Khz, TTR: 400Hz) and system clock (19MHz) to the network termination system for smooth video service and NTR / TTR clock supply. It is to provide NTR / TTR clock supply in DSLAM system that redundancy prevents clock interruption due to board switching and ensures stable clock supply.

The present invention for achieving the above object,

In the DSLAM system consisting of a concentrator backboard and a modem self-backboard,

The collection unit back board,

A redundancy control board detecting each state of the duplicated reference clock distribution board and controlling master and slave operation modes according to the detected state;

Restoring the reference clock in the NTR / TTR data frame input through the cell bus, restoring the system clock in the optical data, and converting the NTR / TTR clock through the cell bus through the cell bus under the control of the redundant control board. A duplicated reference clock distribution board providing the restored system clock to a concentrator lower board and supplying a synchronization clock to a modem self-backboard;

The concentrator sub-board connected to the reference clock distribution board through the cell bus, and interfacing the cell with the modem self-backboard in synchronization with a system clock provided by the reference clock distribution board;

And a digital subscriber line interface board configured to interface subscriber and cell data in synchronization with the NTR / TTR reference clock provided by the reference clock distribution board through the cell bus.

In addition, the reference clock distribution board,

A user network interface unit for restoring a system clock from input optical data;

A cell interface unit for interfacing a cell between the user network interface unit and a cell bus;

A phase locked loop selecting one of an NTR / TTR reference clock input through the cell bus and a system clock recovered from the user network interface unit, and synchronizing the clock with a reference clock;

A clock divider for dividing the reference clock output from the phase locked loop into a plurality of dividers to output a system clock, a synchronous clock, and a TTR reference clock;

And a buffer configured to buffer the TTR reference clock output from the clock divider and output the buffered TTR reference clock to the cell bus.

In addition, the collecting unit lower board,

A cell interface unit for interfacing the cell bus with cell data;

The system clock is supplied through the cell bus, and a user network interface unit is configured to interface optical data between the cell interface unit and the modem self-backboard in synchronization with the supplied system clock.

In addition, the digital subscriber line interface board,

A cell interface unit connected to the cell bus to interface cell data;

And a network termination unit for receiving an NTR / TTR reference clock supplied through the cell bus and synchronizing the subscriber and cell data in synchronization with the NTR / TTR reference clock.

The present invention for achieving the above object,

In the DSLAM system consisting of a concentrator backboard and a modem self-backboard,

The modem self-backboard,

NTR / TTR reference clock is generated by restoring the system clock from the optical data transmitted from the concentrator subboard in the concentrator backboard and distributing the system clock in synchronization with the synchronous clock supplied through the cell bus in the concentrator backboard. A modem self interface board;

The NTR / TTR reference clock generated by the modem self-interface board is authorized through a cell bus, and the digital subscriber line interface board is configured to interface the subscriber and the cell in synchronization with the authorized NTR / TTR reference clock.

In addition, the modem self interface board,

A user network interface unit for restoring a system clock from the optical data transmitted from the concentrator sub-board in the concentrator backboard;

A cell interface unit for interfacing cell data between the user network interface unit and a cell bus;

A clock divider for dividing a system clock recovered by the user network interface unit in synchronization with a synchronous clock transmitted through the cell bus;

The clock divider divides the clock divided by a plurality of dividers to generate an NTR / TTR reference clock, and comprises a reference clock divider configured to output the cell bus.

In addition, the digital subscriber line interface board,

A cell interface unit for interfacing a subscriber cell via the cell bus;

The network terminal is configured to receive an NTR / TTR reference clock through the cell bus and interface the cell between the cell interface unit and the subscriber in synchronization with the received NTR / TTR reference clock.

1 is a block diagram showing the configuration of the NTR / TTR clock supply apparatus in the DSLAM system according to the present invention,

2 is a flowchart illustrating an NTR / TTR clock supply process in a DSLAM system according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1000 ..... Concentrator White Board

2000 ..... Modem Self Backboard

100 ..... Redundant Control Board

200 ..... Reference Clock Distribution Board

300 ..... Concentrator Subboard

400, 700 ..... Digital Subscriber Line Interface Board

600 ..... Modem Self Interface Board

Hereinafter, a preferred embodiment of the present invention according to the technical spirit as described above in detail.

First, the present invention checks whether there is an abnormality of input of 2M, 64K, and 19M of frame sync, and then selects external synchronization (E), which is a selection order of a synchronization source, to use as an input source of a PLL. In the NTR / TTR buffer, 19MHz, 8Khz, and 400Hz are output as synchronous clocks as slots for each concentration shelf (CS) and mode shelf (MS).

8Khz is basically used for system synchronization between digital network and ATU-C system of subscriber board. To this end, DSLAM system generates and distributes 8Khz sync frame from CS reference clock distribution board and provides it to digital subscriber line interface board.In case of selecting the synchronization source, the external, loop and internal clock can be selected according to the clock accuracy. do. The reference clock distribution board uses 19.44MHz for user network interface synchronization, and the digital subscriber line interface board distributes 8Hz and 400Hz, which is a requirement of TTR, for use in CS.

NTR uses 8Khz by default. The method of generation on the board is to restore from DOTS (Digital Office Timing Supply) and to distribute from the local oscillator and the frame pulse restored from the user network interface board. The reconstructed 8Khz clock is provided to the CS through 0 to 12 slot ATU-C through the buffer. The user network interface uses 19.44MHz as the reference clock, providing a restored clock to buffers 0 through 12 slots. TTR recovers 64Khz, 8Khz, 400Hz from 64Kbps AMI signal and provides it to CS 0 ~ 14 slots through buffer, and also supplies 8Khz to each MS Self using twisted pair cable. In MS Self, NTR receives 19MHz in a loop and distributes 8Khz to ATU-C for implementation, and 8Khz distributed clock provided by CS receives and distributes to ATU-C.

However, the model self-backboard does not provide 8Khz to the outside like the concentrator backboard. In CS Self, the reference clock distribution board has a redundancy function, so the source switching also performs the same switching according to board hernia, reset, loss, AIS, and RDI signals.

On the other hand, TTR in CS and MS basically uses a 400Hz clock, so the 64Khz AMI signal input through the concentrator backboard restores 64Khz from the framer chip and divides it. 400Hz is distributed to the TTR source of ATU-C through the concentrator backboard and the modem self-backboard. In MS Self, TTR clock uses 8Khz distributed from CS Self. If there is no 8Khz signal, loop clock is implemented to use 8Khz distributed at 19MHz.

That is, the MS doesn't have a port to receive NTR / TTR signals directly like a concentrator backboard, but instead receives 8Khz provided by the CS, and also doesn't use externally distributed connectors.

The concentrator backboard needs one port to receive 2.048Mbps HDB3 frames for NTR, one port to receive 64Kbps AMI frames for TTR, and a connector to distribute 8Khz to MS Self. Since four types of clocks, such as 19.44MHz, 2MHz, 8Khz, and 64Khz, are distributed on one board, a synchronous distribution clock requires a shield structure in which a clock signal line is shielded. In addition, a two-signal line is needed to compare phases between the master and slave boards.

In software, the reference clock distribution board allows manual and automatic switching of the synchronous clocks in the order of external, loop, and internal clock, which can be displayed on the front panel. Implement this to work.

1 is a diagram illustrating a configuration of an antique / tial clock supply device in a DRAM system according to the present invention.

Here, reference numeral 1000 denotes a Concentration Redundant Uplink Board (CSBB), and reference numeral 2000 denotes a Modem Shelf Back Board (MSBB).

In addition, the concentrator back board 1000 detects each state of the redundant reference clock distribution board and controls a master and slave operation mode according to the detected state (CRMB: Concentration Redundancy Management Board (CRMB) ( 100); Restoring a reference clock from an NTR / TTR data frame input through a cell bus 500, restoring a system clock from optical data, and controlling the NTR / TTR clock under control of the redundant control board 200. Is provided to the Digital Subscriber Line Interface Board (DSLB) 400 through the cell bus 500, and the restored system clock is provided to a Concentration Shelf Down Link Board (CSDB) 300. A duplicated reference clock distribution board 200 for providing a synchronous clock to a modem shelf back board (MSBB) 2000; The home, which is connected to the reference clock distribution board 200 through the cell bus 500 and interfaces the cell with the modem self-backboard 2000 in synchronization with a system clock provided by the reference clock distribution board 200. A first lower board 300; It consists of a digital subscriber line interface board 400 for interfacing subscriber and cell data in synchronization with the NTR / TTR reference clock provided by the reference clock distribution board 200 through the cell bus 500.

In addition, the modem self-backboard 2000 restores the system clock from the optical data transmitted from the concentrator lower board 300 in the concentrator backboard 1000, and restores a system bus 500 in the concentrator backboard 1000. A Modem Shelf Interface Board (MSIB) 600 for generating an NTR / TTR reference clock by distributing the system clock in synchronization with a synchronous clock supplied through the &lt; RTI ID = 0.0 &gt; A digital subscriber line interface board for receiving the NTR / TTR reference clock generated by the modem self interface board 600 through the cell bus 800 and for interfacing the subscriber and the cell in synchronization with the authorized NTR / TTR reference clock. DSLB: Digital Subscriber Down Link Board (700).

The operation of the NTR / TTR clock supply device in the DSLAM system according to the present invention configured as described above is as follows.

First, the redundant control board 100 detects each state of the redundant reference clock distribution boards 200 and 200 ', and determines the master reference clock distribution board and the slave reference clock distribution board. Here, although only one reference clock distribution board 200 is shown in the drawing, in practice, the same reference clock distribution board is dually configured. For convenience, the reference clock distribution board 200 is assumed to be a master reference clock distribution board. Hereinafter, only operations of the reference clock distribution board 200 set as the master will be described.

Next, the reference clock distribution board 200 generates an NTR / TTR reference clock using NTR (2MHz) / TTR (64Khz) signal input through the cell bus 500 and 155MHz optical data transmitted through the optical cable. Then, it is supplied to the lower board and the modem self-backboard 2000.

The operation of the reference clock distribution board 200 will be described in more detail as follows.

The reference clock distribution board 200 includes: a user network interface unit (UNI) 210 for recovering a system clock (19 MHz) from input optical data (155 Mbps); A cell interface unit (Cubit) 220 for interfacing a cell between the user network interface unit 210 and the cell bus 500; Phase synchronization is performed by selecting one of an NTR / TTR reference clock input through the cell bus 500 and a system clock restored by the user network interface unit 210 and outputting the synchronized clock as a reference clock. A loop portion (PLL: Phase Locked Loop) 230; A clock divider 240 for dividing the reference clock output from the phase locked loop unit 230 into a plurality of dividers to output a system clock, a synchronous clock, and a TTR reference clock; The buffer 250 is configured to buffer the TTR reference clock 400 Hz output from the clock divider 240 and output the buffered TTR reference clock to the cell bus 500.

The reference clock distribution board 200 configured as described above, first separates the data and the clock from the 155Mbps optical data transmitted through the optical cable from the user network interface unit 210, the separated optical data (cell) is the cell interface unit 220 ), And the separated clock is restored to the system clock of 19 MHz and transmitted to the phase locked loop unit 230.

The cell interface unit 220 transmits the cell transmitted from the user network interface unit 210 to the cell bus 500 side, and the cell transmitted from the cell bus 500 to the user network interface unit 210. To pass.

Next, the phase locked loop unit 230 is a 19 MHz system clock provided by the user network interface unit 210, a 2 MHz NTR clock supplied through the cell bus 500, a TTR clock of 64 Khz and the board itself. After receiving a 19 MHz clock for internal synchronization generated using an oscillator (oscillator), only one reference clock is selected according to the synchronization selection signal, and the phase synchronization is provided to the clock divider 240.

Here, the synchronization clock is selected in order of external synchronization, loop synchronization, and internal synchronization.

The clock divider 240 divides the reference clock output in synchronization with the phase lock loop 230 into a plurality of dividers therein to generate a system clock of 19 MHz and a synchronization clock of 8 kHz to generate the synchronous clock of the cell bus 500. The TTR clock of 400 Hz is generated and transferred to the buffer 250.

The buffer 250 buffers the input TTR clock and outputs the buffered TTR clock to the cell bus 500.

The system clock transmitted to the cell bus 500 is supplied to the concentrator lower board 300, the TTR reference clock and the synchronization clock are supplied to the digital subscriber line interface board 400, and the 8Khz synchronization clock is the modem self. It is supplied to the back board 2000.

The concentrator lower board 300 includes a cell interface unit 310 and a user network interface unit 320 to interface the cell bus 500 and cell data in the cell interface unit 310. The user network interface unit 320 receives a system clock (19 MHz) through the cell bus 500, and synchronizes the cell interface unit 310 and the modem self-backboard 600 with the system clock supplied thereto. The optical data between the interfaces.

Next, the digital subscriber line interface board 400 includes a cell interface unit 410 and a network termination unit 420, and is connected to the cell bus 500 at the cell interface unit 410 to receive cell data. Interface, and receives an NTR / TTR reference clock supplied through the cell bus 500 from an ATU-C (ATU at the Central office end (network operator) 420), the NTR / TTR reference The subscriber and cell data are interfaced in synchronization with the clock.

On the other hand, the modem self-backboard 2000 is composed of a modem self-interface board 600, a cell bus 800 and a digital subscriber line interface board 700, and synchronizes with a synchronous clock supplied from the concentrator backboard 1000. FIG. To process cell data.

The detailed operation of each component of the modem self-backboard 2000 will be described below.

First, the modem self-interface board 600 includes: a user network interface unit 610 for restoring a system clock from optical data (155 Mbps) transmitted from the collecting unit lower board 300 in the collecting unit back board 1000; A cell interface unit 620 for interfacing cell data between the user network interface unit 610 and the cell bus 800; A clock divider 630 for dividing a system clock restored by the user network interface unit 610 in synchronization with a synchronous clock transmitted through the cell bus 800; The clock divider 630 divides the clock divided by a plurality of dividers to generate a NTR / TTR reference clock and a reference clock divider 640 for outputting the cell bus 800.

The modem self-interface board 600 configured as described above first receives 155 Mbps optical data transmitted from the concentrator lower board 300 from the user network interface 610, and separates the data and the clock from the received optical data. The data is transmitted to the cell interface unit 620, and the clock is restored to the system clock of 19 MHz and transferred to the clock divider 630.

Then, the cell interface unit 620 outputs the cell data transmitted from the user network interface unit 610 to the cell bus 800, and the subscriber cell data output from the cell bus 800 is the user network interface unit. Interface 610.

Next, the clock divider 630 synchronizes the phase of the 8 kHz synchronous clock transmitted through the cell bus 800 in synchronization with the system clock supplied from the user network interface 610 and then the reference clock divider. Forward to 640.

The reference clock distributor 640 transmits the 8Khz synchronous clock as it is to the cell bus and divides it into an internal divider to generate a TTR clock of 400 Hz and outputs the TTR clock to the cell bus 800.

The 8Khz synchronous clock and 400Hz TTR clock delivered to the cell bus 800 are supplied to the digital subscriber line interface board 700, and the digital subscriber line interface board 700 is a subscriber to the supplied synchronization clock and TTR clock. Process cell data.

The operation of the digital subscriber line interface board 700 will be described in more detail as follows.

The digital subscriber line interface board 700 includes: a cell interface unit 710 for interfacing a subscriber cell via the cell bus 800; The network terminal unit 720 receives an NTR / TTR reference clock through the cell bus 800 and interfaces a cell between the cell interface unit 710 and a subscriber in synchronization with the received NTR / TTR reference clock. do.

The digital subscriber line interface board 700 configured as described above first transmits the cell data transferred from the cell interface unit 710 through the cell bus 800 to the network termination unit 720, and the network termination unit 720. The cell delivered from) interface with the cell bus 800.

In addition, the network termination unit 720 processes the subscriber cell in synchronization with the synchronization clock and the TTR reference clock input through the cell bus 800, and transmits the cell transmitted from the subscriber to the cell interface unit 710. .

2 is a flow chart briefly illustrating an operation of an entity clock clock device in a DRAM system according to the present invention.

As shown in the drawing, when frame data (2 MHz, 64 Khz, 19 MHz) is input, the frame is selected. Frame selection is based on priority. In other words, for external synchronization (E), a 2Mbps frame is received in case of NTR, and a 64Kbps frame in case of TTR. If there are no two external synchronization frames, the loop synchronization (L) 19Mbps frame is selected. If there is no loop synchronization signal, the internal synchronization (O) is selected and used as the input of the PLL synchronization unit.

Next, in outputting the synchronized clock signal, the board state is determined and the master outputs the signal. In the case of a board error or a slave board, the output is synchronized to the standby state without outputting the reference clock.

According to the present invention described above, the "ential / tial clock supply apparatus in a DRAM system", there is an advantage that the NTR / TTR clock signal can be distributed in the concentrator backboard.

These benefits also allow the NTR / TTR clocks to be tailored to the country or user's environment, reducing system implementation costs and eliminating the need to install additional clock supplies.

In addition, by implementing the NTR / TTR clock supply in redundancy, it is possible to provide a stable clock even in the event of board failure, failure of the signal line, and board detachment, thereby improving system stability.

In addition, since the modem self receives 8 kHz synchronized from the concentrator self, the synchronous clock can be provided by only distributing to the ATU-C without synchronizing separately from the modem self, thereby reducing the cost and providing high-speed data and The advantage is that the video signal can be transmitted smoothly without interruption.

Claims (7)

In the DSLAM system consisting of a concentrator backboard and a modem self-backboard, The collection unit back board, A redundancy control board detecting each state of the duplicated reference clock distribution board and controlling master and slave operation modes according to the detected state; Restoring the reference clock in the NTR / TTR data frame input through the cell bus, restoring the system clock in the optical data, and converting the NTR / TTR clock through the cell bus through the cell bus under the control of the redundant control board. A duplicated reference clock distribution board providing the restored system clock to a concentrator lower board and supplying a synchronization clock to a modem self-backboard; The concentrator sub-board connected to the reference clock distribution board through the cell bus, and interfacing the cell with the modem self-backboard in synchronization with a system clock provided by the reference clock distribution board; Providing an entity / tial clock in a DRAM system comprising a digital subscriber line interface board for interfacing subscriber data with cell data in synchronization with the NTR / TTR reference clock provided by the reference clock distribution board through the cell bus. Device. According to claim 1, wherein the reference clock distribution board, A user network interface unit for restoring a system clock from input optical data; A cell interface unit for interfacing a cell between the user network interface unit and a cell bus; A phase locked loop selecting one of an NTR / TTR reference clock input through the cell bus and a system clock recovered from the user network interface unit, and synchronizing the clock with a reference clock; A clock divider for dividing the reference clock output from the phase locked loop into a plurality of dividers to output a system clock, a synchronous clock, and a TTR reference clock; An ENTIAL / TIAL clock supply device in a DRAM system comprising a buffer configured to buffer the TTR reference clock output from the clock divider and output the buffered TTR reference clock to the cell bus. The board of claim 1, wherein the concentrator lower board includes: A cell interface unit for interfacing the cell bus with cell data; The system clock is supplied through the cell bus, and the user network interface unit is configured to interface optical data between the cell interface unit and the modem self-backboard in synchronization with the supplied system clock. R clock supply. The method of claim 1, wherein the digital subscriber line interface board, A cell interface unit connected to the cell bus to interface cell data; The NTR / TTR reference clock supplied through the cell bus, and an ENTIAL / TIAL clock in a DRAM system comprising an end of a network for interfacing subscriber data with a subscriber in synchronization with the NTR / TTR reference clock. Feeder. In the DSLAM system consisting of a concentrator backboard and a modem self-backboard, The modem self-backboard, NTR / TTR reference clock is generated by restoring the system clock from the optical data transmitted from the concentrator subboard in the concentrator backboard and distributing the system clock in synchronization with the synchronous clock supplied through the cell bus in the concentrator backboard. A modem self interface board; The NTR / TTR reference clock generated by the modem self-interface board is authorized through a cell bus, and is configured as a digital subscriber line interface board configured to interface a subscriber and a cell in synchronization with the authorized NTR / TTR reference clock. ENTIAL / TIAL clock supply in RAM system. The method of claim 5, wherein the modem self interface board, A user network interface unit for restoring a system clock from the optical data transmitted from the concentrator sub-board in the concentrator backboard; A cell interface unit for interfacing cell data between the user network interface unit and a cell bus; A clock divider for synchronizing and outputting a phase of a synchronous clock transmitted through the cell bus in synchronization with a system clock output from the user network interface unit; And a clock clock divider for dividing the clock output from the clock divider into a divider to generate an NTR / TTR reference clock and output the NTR / TTR reference clock to the cell bus. The method of claim 5, wherein the digital subscriber line interface board, A cell interface unit for interfacing a subscriber cell via the cell bus; The NTR / TTR reference clock is input through the cell bus, and the network terminal is configured to interface the cell between the cell interface unit and the subscriber in synchronization with the received NTR / TTR reference clock. / Tial clock supply.