KR20030039800A - ISDN Network clock distribution device for ADSL connection - Google Patents

Abstract

PURPOSE: A device of distributing ISDN network clocks for an ADSL connection is provided to supply network synchronous clock signals of an ISDN to many DSLAMs without delay, and to prevent the supplying of the network clock signals from stopping owing to malfunction of the DSLAMs and DOTS, thereby stably supplying an ADSL connection service. CONSTITUTION: A network clock signal receiver(110) receives at least one network clock signal composed of DOTS signals from an ISDN network clock transmitter, and converts the received signal into TTL data. A network clock signal processor(140) extracts predetermined ISDN synchronous data and the clock signal from the TTL data, and outputs the extracted data and the signal. A clock distributor(160) distributes the outputted ISDN synchronous data and the clock signal to many output units in the same signal type. Many differential clock signal transmitters(170) supply the second network clock signal converting the outputted signals of the clock distributor(160) into differential clocks to many DSLAMs(50).

Description

ISDN Network clock distribution device for ADSL connection for asymmetric digital subscriber line connection

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a Co., Ltd. equipment for transmitting an asymmetric digital subscriber line (ADSL) signal over an ISDN line, and in particular, a plurality of digital subscriber line access multiplexers (DSLAM) The present invention relates to an ISDN network clock distribution device for an ADSL connection that can provide a stable clock signal.

Asymmetric Digital Subscriber Line, which is sufficient to accommodate multimedia services due to the recent development of the Internet, and is economical, and enables high-speed digital data communication using existing telephone lines or integrated services digital network (ISDN) lines. Standards have been proposed and are rapidly spreading.

The signal transmission method according to the ADSL standard is divided into the conventional twisted pair cable, that is, the ANNEX A method for transmitting an ADSL signal using a telephone line, and the ANNEX C method for transmitting an ADSL signal using an ISDN line. The ANNEX A method is used in North America, and the ANNEX C method is used in Japan, where the ISDN network is widely spread.

Hereinafter, the network configuration of the conventional ADSL system according to the ANNEX A or ANNEX C scheme will be briefly described.

FIG. 1 is a block diagram showing the configuration of an ADSL network system according to the conventional ANNEC A scheme. As shown in FIG. 1, a subscriber station 10 and a digital subscriber line access multiplexer (DSLAM) are illustrated. (Hereinafter referred to as 'DSLAM') 20 and a network access server (NAS: hereinafter referred to as 'NAS') 30.

The subscriber station 10 of FIG. 1 is a subscriber side equipment for using an ADSL service, which includes a subscriber side splitter (not shown), a subscriber side ADSL interface ATU-R, a subscriber computer, and a telephone. The DSLAM 20 of FIG. 1 is used to perform traffic aggregation and relaying of subscribers between the subscriber station 10 and the NAS 30, which is an ATU-C, which is not shown, a splitter and a telephone station ADSL interface. And a network interface for connecting to an external communication network.

In addition, the NAS 30 of FIG. 1 performs traffic processing according to subscriber access, authentication, and data transmission and reception, and connects a plurality of DSLAMs 20 to the Internet 3. Detailed description of the ADSL network system according to the conventional ANNEC A method of FIG. 1 is a general description, and thus the detailed description thereof will be omitted.

Meanwhile, the ADSL network system shown in FIG. 1 is applied to an ISDN network, and the ADSL network system shown in FIG. Figure 2 is a block diagram showing the configuration of the ADSL network system according to the conventional ANNEC C scheme, which is shown in Figure 2 subscriber terminal 10, NAS 30, network clock transmission apparatus (DOTS) (hereinafter referred to as , Referred to as 'DOTS') 40 and DSLAM (50: 50 ₁ ~ 50 _n ).

The subscriber station 10 and the DSLAM 50 of FIG. 2 are communicatively connected through an ISDN line 3, and the DOTS 40 is a DSLAM 50, which includes a synchronization signal SYNC of an ISDN signal. This is to supply the network clock signal. In addition, the DSLAM 50 of FIG. 2 has an internal interface for receiving a predetermined network clock signal from the DOTS 40 to the DSLAM 20 of FIG. 1 and an internal interface for sequentially transmitting the network clock signal to another DSLAM 50. It will be provided.

The network clock signal is synchronized with the transmission of the ADSL signal according to the ISDN transmission standard, and the DOTS signal and 0.4KHz reference clock shown in FIG. 3 according to the ANNEX C scheme so that the phase of the transmitted ADSL signal matches the phase of the ISDN signal ( Reference clock) or selectively use the 32Kbps synchronization data and 64KHz clock shown in FIG. Meanwhile, the 32Kbps synchronization data and the 64KHz clock shown in FIG. 4 represent signals supplied to the ATU-C in the DSLAM 50, and the signals transmitted through the actual communication lines are differential clock signals.

The DOTS signal of FIG. 3 includes a synchronization signal marked in black every 8 KHz period. The specification and operation of the network clock signal are described in the APPENDIX ANNEC C of the ITU G.992.1 and the ITU G.992.2 standard, and the detailed description thereof will be omitted. The 32 Kbps synchronization data of FIG. 4 includes frame synchronization of the ISDN, and the clock signal shown in FIGS. 3 and 4 represents a half cycle clock signal and actually has a period of 0.2 KHz.

That is, the ANNEX C scheme is proposed to transmit an ADSL signal through an ISDN line. When an ISDN signal and an ADSL signal are transmitted in the same cable, an ISDN signal is not transmitted to prevent an interference between transmission lines of each signal. It finds a time zone that does not transmit the ADSL signal.

In this case, since the DSLAM 50 needs to be synchronized with the ISDN network in order to find a time zone during which the ISDN signal is not transmitted, the DOTS 40 of FIG. 2 supplies the network clock signal to the DSLAM 50 directly connected thereto, and the network clock. The DSLAM 50 receiving the signal sequentially transmits the network clock signal to another DSLAM 50 connected thereto.

In addition, the DSLAM 50 receiving the network clock signal checks whether there is signal interference due to simultaneous transmission of the ISDN signal and the ADSL signal, and when there is no signal interference, that is, finds a time zone during which the ISDN signal is not transmitted and transmits the ADSL signal. do.

However, in the above-described ADSL network system according to the ANNEC C standard, one DSLAM 50 is configured to receive the network clock signal directly from the DOTS 40 and then sequentially transmit the same to the other DSLAM 50. Therefore, there is a delay in the network clock signal transmitted through a plurality of DSLAM (50), there is a problem that the number of installation of the DSLAM (50) that can be sequentially connected to one DOTS (40).

Also, since a plurality of DSLAMs 50 are serially connected as shown in FIG. 2, when an abnormality occurs in one DSLAM 50, the DSLAM 50 connected to a subsequent stage of the corresponding DSLAM 50 may be connected to a network clock signal. There is a problem that the supply is stopped.

Accordingly, the present invention has been made in view of the above circumstances, and provides the ISDN network network clock signal to a plurality of DSLAMs without delay, and prevents the network clock signal supply interruption caused by the failure of DOTS and DSLAM through the ISDN circuit. The purpose of the present invention is to provide an ISDN network clock distribution device for ADSL access that can stably provide an ADSL access service.

1 is a block diagram showing the configuration of an ADSL network system according to the conventional ANNEC A scheme.

Figure 2 is a block diagram showing the configuration of an ADSL network system according to the conventional ANNEC C system.

Figure 3 is a waveform diagram showing a DOTS signal and 0.4KHz reference clock according to the ANNEX C scheme.

4 is a waveform diagram showing a 32Kbps synchronization data and a 64KHz clock for finding frame synchronization of an ISDN.

Figure 5 is a block diagram showing the configuration of an ADSL network system to which the ISDN network clock distribution apparatus according to the present invention.

Figure 6 is a block diagram showing the internal configuration of the ISDN network clock distribution device for ADSL access according to an embodiment of the present invention.

7 is a functional block diagram functionally showing the configuration of the clock signal processing unit 140 shown in FIG.

FIG. 8 is a waveform diagram showing 64 Kbps TTL data of the positive and negative pole portions output from the network clock signal receiver 110 shown in FIG.

9 is a waveform diagram showing differential 32 Kbps sync data and 64 KHz clock for finding frame synchronization of an ISDN;

*** Explanation of symbols for the main parts of the drawing ***

10: subscriber terminal,

20, 50 (50 ₁ ~ 50 _P ): Digital Subscriber Line Multiplexer (DSLAM),

30: network access server (NAS), 40: network clock transmission device (DOTS)

100 (100 ₁ ~ 100 _m ): network clock distribution unit, 110: network clock signal receiver,

120: differential clock signal receiver, 130: oscillator,

140: clock signal processing unit, 141: synchronous clock extraction unit,

142: clock monitor unit, 143: local clock generator,

144: clock selector, 145: display processor,

150: clock status display unit, 160: clock distribution unit,

170 (170 ₁ ~ 170 _x ): differential clock signal transmitter

ISDN network clock distribution device for ADSL connection to achieve the above object is ISDN network as a plurality of digital subscriber line access multiplexer to provide ADSL access service by communication connection between a plurality of subscriber terminal and network access server connected to ISDN line An apparatus for supplying a synchronous clock, the apparatus comprising: a network clock signal receiving means for receiving at least one first network clock signal composed of a DOTS signal from an ISDN network clock transmission apparatus and converting the TCL data into positive and negative portions; Network clock signal processing means for extracting and outputting predetermined ISDN synchronization data and clock signals from the TTL data of the positive and negative portions output from the signal receiving means, and the ISDN synchronization data and clock signals outputted from the network clock signal processing means. Clock distribution means for distributing and outputting to a plurality of output stages in the same signal form; Including a plurality of differential clock signals sending means for supplying a second clock signal network converts the output signal from each of the differential clock of the unit groups the plurality of digital line access multiplexer is characterized in that configured.

In addition, the present invention further comprises a differential clock signal receiving means for receiving the second network clock signal supplied from another ISDN network clock distribution device and converts it into the ISDN synchronization data and clock signal, the network clock signal processing The means comprises: synchronous clock extracting means for extracting the ISDN synchronization data and clock signal from an output signal of the network clock signal receiving means, and ISDN synchronization of at least two lines transmitted through the synchronous clock extracting means and the differential clock signal receiving means; And a clock monitor and selection means for selectively outputting the ISDN synchronization data and the clock signal of the normal line by checking the operation state of the data and the clock signal.

In the present invention, the synchronous clock extracting means performs a NOT operation on the positive portion TTL data output from the network clock signal receiving means, and outputs the ISDN synchronous data by outputting at a predetermined transmission rate and the positive portion TTL data and the negative electrode. And extracting a clock signal having a predetermined frequency by performing an AND operation on the partial TTL data.

In addition, the present invention further comprises an oscillation means for oscillating a local clock of a predetermined frequency, the network clock signal processing means is the ISDN using the predetermined network synchronizer data of the ISDN network provided in the local clock and the internal storage means And a local clock generating means for generating synchronous data and a clock, wherein the clock monitor and selecting means are configured to determine that the output signals of the synchronous clock extracting means and the differential clock signal receiving means are not all in a normal state. And output the ISDN synchronization data and the clock generated from the local clock generating means.

Also, in the present invention, the local clock generating means outputs the network synchronizer data to the local clock to generate ISDN synchronization data of the positive and negative portions, respectively, and AND-generates the ISDN synchronization data to generate a clock signal of a predetermined frequency. Characterized in that configured.

Therefore, according to the above configuration, it is possible to stably provide a network synchronizer clock signal of an ISDN network to a plurality of DSLAMs.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 5 is a block diagram showing the configuration of an ADSL network system to which an ISDN network clock distribution apparatus according to the present invention is applied. The same reference numerals are given to the same components as those shown in FIG. Will be omitted.

A plurality of network clock distribution devices 100: 100 ₁ to 100 _m are sequentially connected to DOTS 40 of FIG. 5, and a plurality of DSLAMs 50: 50 ₁ to 50 _P are sequentially connected to each network clock distribution device 100. ) Are connected in parallel. In this case, the installation number of the network clock distribution device 100 is installed in an appropriate number in consideration of the delay of the network clock signal.

The DOTS 40 of FIG. 5 supplies the DOTS signal of FIG. 3 to a network clock distribution device 100 ₁ directly connected thereto as a network clock signal (hereinafter referred to as a 'first network clock signal'), and the network clock. The distribution apparatus 100 ₁ converts the first network clock signal into 32 Kbps synchronization data, which is a differential clock signal, and 64 KHz (hereinafter, referred to as a 'second network clock signal').

That is, FIG. 8 shows the 32Kbps synchronization data and the 64KHz clock of FIG. 4 as the normal and reverse phase differential clocks. Since the differential clock has a strong characteristic against noise during high frequency data transmission as is well known, it is generally used in data communication. It is a clock.

A plurality of network clock distribution apparatuses 100 ₂ to 100 _m sequentially connected to the rear ends of the network clock distribution apparatus 100 ₁ are respectively connected to the second and second network clock distribution apparatus 100 of FIG. The network clock signal is supplied to supply the second network clock signal of the same type to the network clock distribution device 100 connected to the rear end. Each network clock distribution device 100 supplies the second network clock signal to a plurality of DSLAMs 50 connected in parallel thereto.

In addition, when the supply of the first network clock signal from the DOTS 40 is stopped and the supply of the second network clock signal from the other network clock distribution device 100 of FIG. The local clock generating means generates the network clock signal of FIG. 4 and converts it to the second network clock signal, and then supplies it to the other network clock distribution apparatus 100 and the DSLAM 50.

Hereinafter, embodiments of the present invention will be described in more detail with reference to FIGS. 6 to 8.

6 is a block diagram showing an internal configuration of an ISDN network clock distribution device for ADSL connection according to an embodiment of the present invention, which is a network clock signal receiver 110, a differential clock signal receiver 120, and an oscillator 130. ), A clock signal processor 140, a clock state display unit 150, a clock divider 160, and a differential clock signal transmitter 170.

The network clock signal receiver 110 of FIG. 6 receives the DOTS signal of FIG. 3, which is a bipolar signal, from the DOTS 40, and then divides the DOTS signal into (+) and (−) pole portions as shown in FIG. 8. This is for converting and outputting the separated 64Kbps TTL data.

That is, since the bipolar signal is a main transmission signal of a transmission system using a metal cable as a transmission medium, the bipolar signal is converted into a TTL signal suitable for digital signal processing. The network clock signal receiver 110 uses, for example, XRT6164A of EXAR as a circuit interface transceiver.

Meanwhile, the XRT6164A is a device configured to receive a bipolar signal and output an active low level TTL signal. As shown in FIG. 8, the (+) pole portion of the 64 Kbps TTL data has a low level of the DOTS signal. Positive (+) clock and ground are output as 64Kbps TTL data marked as high level, and negative (-) pole of 64Kbps TTL data is displayed as (-) clock and ground of DOTS signal as high level and (+) clock as low level. Output as 64Kbps TTL data.

The differential clock signal receiver 120 of FIG. 6 receives the second network clock signal of FIG. 9, which is a differential clock, from another network clock distribution apparatus 100, and converts the second network clock signal into TTL single data on a phase. Is transmitted to a clock signal processor 140 to be described later. The differential clock signal receiver 120 uses, for example, the DS26LS32 manufactured by National Semiconductor.

Although the network clock signal receiver 110 and the differential clock signal receiver 120 of FIG. 6 each have only one input / output port, the input / output port may be configured as two input / output ports. In this case, the network clock signal receiver 110 receives two lines of DOTS signals from the DOTS 40, and the differential clock signal receiver 120 receives two second network clocks from two network clock distribution apparatuses 100. You will receive a signal.

The oscillator 130 of FIG. 6 is for oscillating a local clock of 16.384 MHz, for example. The clock signal processor 140 to be described later uses the oscillated local clock and predetermined synchronization data provided in the internal storage means. The 32Kbps synchronization data and 64KHz clock of FIG. 4 are generated.

The clock signal processor 140 of FIG. 6 extracts / generates the 32Kbps synchronization data and 64KHz clock of FIG. 4 from the output signals of the network clock signal receiver 110, the differential clock signal receiver 120, and the oscillator 130. In addition, to check whether there is a failure of each output line and selectively output 32Kbps synchronization data and 64KHz clock supplied from the normal line, for example, it is composed of a programmable logic device (PLD), which will be described later.

The clock state display unit 150 of FIG. 6 is provided with first and second network clocks supplied from the DOTS 40 and the other network clock distribution device 100 based on a predetermined control signal output from the clock signal processor 140. This is for visually displaying the operation status of the signal and the 32Kbps synchronization data and the output line of the 64KHz clock using LEDs.

The clock divider 160 of FIG. 6 distributes the 32Kbps synchronization data and the 64KHz clock outputted from the clock signal processing unit 140 through a plurality of output stages in the same signal form, and in the present embodiment, 32Kbps synchronization data. And 64KHz clock are distributed to 48 output stages, for example. The clock divider 160 uses, for example, IDT74FCT807 manufactured by Integrated Device Technology.

The differential clock signal transmission unit of Figure _{6 (170: 170 1 ~ 170} x) are as shown in each of Fig. 9 the 32Kbps synchronous data with the 64KHz clock which is transmitted from each output terminal of the clock distributor 160 to convert the differential clock As a second network clock signal, the converted signal is transmitted to the plurality of DSLAMs 50 or the network clock distribution apparatus 100 connected thereto. The differential clock signal transmitter 170 uses, for example, the DS26LS31 manufactured by National Semiconductor as a differential line driver.

Hereinafter, the clock signal processor 140 will be described in more detail with reference to FIG. 7.

FIG. 7 is a functional block diagram functionally showing the configuration of the clock signal processor 140. The clock signal processor 142, the clock monitor 142, and the local clock generator 143 as shown in FIG. And a clock selector 144 and a display processor 145.

The sync clock extractor 141 of FIG. 7 uses the 32 Kbps sync data of FIG. 4 from 64 Kbps TTL data (see FIG. 8) of the positive and negative pole portions output from the network clock signal receiver 110. And to extract the 64KHz clock, the synchronous clock extraction unit 141 performs a NOT operation on the (+) pole 64Kbps TTL data of Figure 8, and outputs as 32Kbps to extract the 32Kbps synchronization data of FIG. The 64KHz clock of FIG. 4 is extracted by performing an AND operation on the positive pole TTL data and the negative pole TTL data of FIG. 8.

The clock monitor 142 of FIG. 7 checks the operation states of the 32Kbps synchronization data and the 64KHz clock applied from the synchronous clock extractor 141 and the differential clock signal receiver 120 to describe predetermined clock operation state information. Output to the clock selector 144.

The clock operation state information is extracted from the 32 Kbps synchronization data extracted from the first network clock signal supplied by the DOTS 40 of FIG. 5 and the second network clock signal supplied from the network clock distribution device 100 that is different from the 64 KHz clock. It is composed of 32Kbps synchronization data and information indicating whether the 64KHz clock is in a normal / abnormal state.

The local clock generator 143 of FIG. 7 divides the 16.384 MHz local clock supplied from the oscillator 130 of FIG. 6 to generate a 32 KHz clock, and generates a 32 KHz clock and a predetermined network device provided in the internal storage means. The data is used to generate the 32Kbps synchronization data and 64KHz clock of FIG. 4 using the data. For example, the network synchronizer data is obtained by extracting 32 Kbps synchronization data of FIG. 4 during a 0.2 KHz period.

The local clock generator 143 outputs the network synchronizer data as a 32KHz clock to generate 32Kbps sync data of the (+) and (-) poles, respectively, and ANDs the two 32Kbps sync data to 64KHz. Generate a clock.

The clock selector 144 of FIG. 7 is connected to output terminals of the synchronous clock extractor 141, the differential clock signal receiver 120, and the clock monitor 142, respectively, and is connected to a normal state based on the clock operation state information. 32Kbps synchronization data and 64KHz clock are selected and output as the source data of the second network clock signal.

In addition, the clock selector 144 of FIG. 7 determines that the output lines of the synchronous clock extractor 141 and the differential clock signal receiver 120 are not in a normal state from the local clock generator 143. The generated 32Kbps synchronization data and 64KHz clock are output as source data of the second network clock signal.

The display processor 145 of FIG. 7 is connected to one end of the clock selector 144 and based on the clock operation state information according to the signal output of the synchronous clock extractor 141 and the differential clock signal receiver 120. The clock state display unit 150 of FIG. 6 is controlled to display the clock operation state of each output line and the output lines of the 32Kbps synchronization data and the 64KHz clock output from the current clock selector 144.

Therefore, the user checks the abnormality of the network clock signal supplied from the DOTS 40 or the other network clock distribution device 100 through the clock status display unit 150, and synchronizes 32 Kbps based on the current network clock signal of any line. You will be able to verify that the data and the 64KHz clock are output.

Hereinafter, the operation of the ISDN network clock distribution device for the ADSL connection having the above configuration will be described.

First, the DOTS 40 supplies the network clock signal of FIG. 3 to the ISDN network to supply frame synchronization of the ISDN signal. Meanwhile, the network clock distribution apparatus 100 of FIG. 5 is connected to an output terminal of the DOTS 40 to receive a clock signal having the same type as the DOTS signal of FIG. 3 supplied to the ISDN network as the first network clock signal.

In addition, the network clock distribution device 100 connected in series at the rear end of the other network clock distribution device 100 among the network clock distribution device 100 of FIG. 5 is connected to the ISDN network from the network clock distribution device 100 connected to the front end thereof. Differential 32Kbps synchronization data and 64KHz clock are supplied as the second network clock signal to match frame synchronization.

Thereafter, the network clock signal receiver 110 of FIG. 6 converts the first network clock signal, which is the bipolar data supplied from the DOTS 40, into 64Kbps TTL data divided into the positive and negative pole parts of FIG. 8. The converted signal is output to the clock signal processor 140 of FIG. 6.

In addition, the differential clock signal receiver 120 of FIG. 6 converts the second network clock signal supplied from another network clock distribution apparatus 100 into 32Kbps synchronization data and 64KHz clock, that is, TTL single data in the same phase as in FIG. Outputs to the clock monitor 142 and the clock selector 144 of FIG.

In addition, the oscillator 130 of FIG. 6 oscillates a local clock of 16.384 MHz and supplies it to the clock signal processor 140. The clock signal processor 140 generates an oscillated local clock of 32 Kbps synchronization data and a 64 KHz clock. It will be used as source data for.

Meanwhile, the synchronous clock extractor 141 of FIG. 7 performs NOT operation on the (+) pole 64 Kbps TTL data output from the network clock signal receiver 110 of FIG. 6 and outputs the 32 Kbps to output the 32 Kbps synchronous data of FIG. 4. In addition to extracting and AND operation of the (+) pole portion TTL data and (-) pole portion TTL data of Figure 8 to extract the 64KHz clock of Figure 4 to output to the clock monitor 142 and the clock selector 144. do.

Thereafter, the clock monitor 142 of FIG. 7 checks whether the 32Kbps synchronization data and the 64KHz clock are abnormal from the synchronous clock extractor 141 and the differential clock signal receiver 120, respectively, and checks the clock operation state information of FIG. 7. The clock selector 144 outputs the clock selector 144 to select the 32Kbps synchronization data and the 64KHz clock in the normal state based on the clock operation state information and output the clock signal to the clock divider 160.

At this time, when it is determined that the supply of the first network clock signal from the DOTS 40 is stopped and that the supply of the second network clock signal from the other network clock distribution device 100 is also stopped as a result of reading the clock operation state information (abnormal) The clock selector 144 of FIG. 7 divides the 32 Kbps synchronization data and the 64 KHz clock supplied from the local clock generator 143 into a clock divider. 160). The supply interruption / abnormal state of the first and second network clock signals is performed by checking whether the 64 kHz clock is supplied more than 2 clocks, for example.

In addition, the display processor 145 of FIG. 7 receives the clock operation state information from the clock selector 144 to display the signal states of the synchronous clock extractor 141 and the differential clock signal receiver 120, respectively. Visual output of 32Kbps sync data and 64KHz clock output line. This is performed through the clock status display unit 150 provided with the status display LED for each output line of the network clock distribution apparatus 100.

Thereafter, the clock divider 160 of FIG. 7 divides and outputs the 32Kbps sync data and the 64KHz clock of the phase output from the clock selector 144 through the 48 output stages in the same signal form, for example, and the differential clock of FIG. 6. The signal transmitter 170 converts the 32Kbps synchronization data and the 64KHz clock of the phases respectively transmitted from the clock divider 160 into second network clock signals of FIG. 9, that is, differential 32Kbps synchronization data and 64KHz clock, and are connected to each other. It is transmitted to the network clock distribution apparatus 100 and a plurality of DSLAM (50).

In addition, the DSLAM 50 receiving the second network clock signal, that is, the network synchronizer clock signal, from the network clock distribution apparatus 100 of FIG. 5 checks the presence or absence of signal interference due to simultaneous transmission of the ISDN signal and the ADSL signal. The ADSL signal is transmitted by finding a time zone where there is no interference between the ADSL signals.

Therefore, in the present embodiment, a relatively small number of network clock distribution apparatuses 100 are serially connected to one DOTS 40, and a plurality of DSLAMs 50 are connected in parallel to each network clock distribution apparatus 100 of the ISDN network. Since it is configured to supply the network synchronizer clock signal at the same time, the transmission delay time of the network clock signal can be greatly reduced.

That is, when the DSLAM 50 receives a network clock signal through the DOTS 40, for example, the conventional ADSL network system of FIG. 2 generates clock delays of about 90 DSLAMs 50. Since the network clock distributor 100 simultaneously supplies the network clock signals to up to 48 DSLAMs 50, only two clock delays are generated, thereby greatly reducing the transmission delay. .

And each network clock distribution device 100 generates a separate network clock signal through the internal local clock generation means to generate a network clock signal according to whether the clock supply stop of the DOTS 40 and other network clock distribution device 100 By supplying the replacement, it is possible to prevent the network clock signal supply interruption caused by the operation of the DOTS 40 or DSLAM 50 abnormality.

As described above, according to the present invention, the ISDN network synchronizer clock supplied from the DOTS can be provided to the plurality of DSLAMs without time delay, and the ISDN circuit is prevented by preventing the operation of the network synchronizer clock due to the abnormal operation of the DOTS and DSLAM. It is possible to provide stable ADSL access service.

Claims (7)

An apparatus for supplying an ISDN network clock to a plurality of digital subscriber line access multiplexers providing an ADSL access service by communicating between a plurality of subscriber station terminals connected to an ISDN line and a network access server. Network clock signal receiving means for receiving the at least one first network clock signal consisting of a DOTS signal from the ISDN network clock transmission device and converts the TTL data of the positive and negative portions, Network clock signal processing means for extracting and outputting predetermined ISDN synchronization data and a clock signal from the TTL data of the positive and negative portions output from the network clock signal receiving means; Clock distribution means for distributing and outputting the ISDN synchronization data and the clock signal output from the network clock signal processing means to a plurality of output terminals in the same signal form; ISDN for ADSL connection comprising a plurality of differential clock signal transmission means for supplying a second network clock signal, each of which converts the output signal from the clock distribution means into a differential clock, to a plurality of digital line connection multiplexers. Network clock distribution device. The method of claim 1, And a differential clock signal receiving means for receiving the second network clock signal supplied from another ISDN network clock distribution device and converting it into the ISDN synchronization data and a clock signal. The network clock signal processing means may include synchronization clock extraction means for extracting the ISDN synchronization data and a clock signal from an output signal of the network clock signal receiving means; Clock monitor and selection for selectively outputting ISDN synchronization data and clock signal of the normal line by checking the operation state of the ISDN synchronization data and clock signal of at least two lines transmitted through the synchronization clock extracting means and the differential clock signal receiving means ISDN network clock distribution device for ADSL connection, characterized in that it comprises a means. The method of claim 2, The synchronous clock extracting means performs NOT operation on the positive portion TTL data output from the network clock signal receiving means, outputs the ISDN synchronization data by outputting at a predetermined transmission rate, and extracts the positive portion TTL data and the negative portion TTL data. ISDN network clock distribution device for ADSL connection, characterized in that configured to extract a clock signal of a predetermined frequency by AND operation. The method of claim 2, And oscillating means for oscillating a local clock of a predetermined frequency, The network clock signal processing means further comprises a local clock generation means for generating the ISDN synchronization data and the clock by using the predetermined network synchronizer data of the ISDN network provided in the local clock and the internal storage means, The clock monitor and the selecting means are configured to output the ISDN synchronization data and the clock generated from the local clock generating means when it is determined that the output signals of the synchronous clock extracting means and the differential clock signal receiving means are not all in a normal state. ISDN network clock distribution device for ADSL connection. The method of claim 4, wherein The local clock generating means is configured to output the network synchronizer data to the local clock to generate ISDN synchronization data of the positive and negative portions, respectively, and to generate an clock signal of a predetermined frequency by AND-operating the ISDN synchronization data. ISDN network clock distribution device for ADSL connection. The method of claim 4, wherein An operation state of the first and second network clock signals supplied from the ISDN network clock distribution device and another network clock distribution device on the basis of a predetermined control signal of the clock signal processing means, and output of the currently output ISDN synchronization data and clock ISDN network clock distribution device for ADSL connection, characterized in that it further comprises a clock state display means for visually displaying the line. The method according to any one of claims 1 to 6, The first network clock signal is a bipolar 64 Kbps DOTS signal according to the ANNEXC method including an ISDN frame synchronization signal every 8 KHz cycle, The ISDN sync data and clock signal are 32Kbps sync data and 64KHz clock on a positive phase. The second network clock signal is ISDN network clock distribution device for ADSL access, characterized in that the differential 32Kbps synchronization data and 64KHz clock.