JP2003163952A - Isdn network clock distribution equipment for asymmetric digital subscriber's loop connection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide ISDN network clock distribution equipment for ADSL connection which can stably provide a network synchronous clock signal of an ISDN network to many digital subscriber's loop connection multiplexers (DSLAM). <P>SOLUTION: The ISDN network clock distribution equipment is provided with a network clock signal receiving means which receives at least one first network clock signal constituted of a DOTS signal from an ISDN network clock transfer equipment, and converts it into TTL data of a positive pole and a negative pole, a network clock signal processing means which extracts prescribed ISDN synchronous data and the clock signal from the TTL data of the positive and negative parts outputted from the receiving means and outputs the extracted data and signal, a clock distributing means which distributes and outputs the synchronous data and the clock signal outputted from the signal processing means in the same signal form to many output terminals, and many differential clock signal transmitting means which supply a second mesh clock signal wherein the output signal from the distributing means is converted into a differential clock to many digital loop connection multiplexers. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated information communication network (I
Asymmetric Digital Subscriber Line (ADSL) to SDN line
The present invention relates to station equipment (Co) equipment for transferring signals, and more specifically, a large number of digital subscriber line connection multiplexers (D).
ISL for ADSL connection that can stably provide the network synchronization clock signal of the ISDN network to SLAM).
The present invention relates to an N network clock distribution device.

[0002]

2. Description of the Related Art Recently, it has been enough to accept multimedia services on the back of the development of the Internet.
Highly economical, existing telephone lines and ISDN (Integra)
arated Services Digital Net
ADSL (Asymmetric Digit) that enables high-speed digital data communication using a work line
The Al Subscriber Line) standard has been proposed and is rapidly spreading.

A signal transfer method based on the ADSL standard is an AD method using an existing twisted pair cable, that is, a telephone line.
It is classified into an ANNEX A system that transfers SL signals and an ANNEX C system that transfers ADSL signals using an ISDN line. The ANNEX A method is used in North America and the like, and the ANN EX C method is used in Japan and the like where the ISDN network is widely spread. The network configuration of the conventional ADSL system based on the ANNEX A or ANNEX C system will be briefly described below.

FIG. 1 shows an A according to the conventional ANNEX A method.
FIG. 2 is a block configuration diagram showing a configuration of a DSL network system, which is, as shown in FIG. 1, a subscriber terminal unit 10, a digital subscriber line connection multiplexer (DSLAM:
Digital Subscriber Line A
ccess Multiplexer) (hereinafter, 'DS
LAM ') 20 and network connection server (NAS: Network Access Server)
r) (hereinafter referred to as “NAS”) 30.

The subscriber terminal unit 10 shown in FIG.
Subscriber side equipment for using the service, which is a subscriber side splitter (not shown), subscriber side AD
It has an ATU-R that is an SL interface, a subscriber computer, and a telephone. The DSLAM 20 shown in FIG. 1 is used for concentrating and relaying the traffic of the subscriber between the subscriber terminal unit 10 and the NAS 30, which is a telephone station side splitter (ATU) which is a telephone station side ADSL interface (not shown). -B and a network interface for connecting to an external communication network.

Further, the NAS 30 of FIG.
Traffic processing by authentication and data transmission / reception is performed, and a large number of DSLAMs 20 are connected to the Internet 2. ADS according to the conventional ANNEX A system of FIG.
The detailed description of the L network system is a general technical content, and thus the detailed description will be omitted.

On the other hand, the ADSL network system shown in FIG. 2 is an application of the ADSL network system shown in FIG. 1 to an ISDN network. FIG. 2 is a block diagram showing a configuration of an ADSL network system according to the conventional ANNEX C system.
As shown in configured to include the subscriber terminal unit 10, NAS 30, the network clock transfer device (DOTS) (hereinafter, referred to as 'DOTS') 40 and DSLAM50 and ₍₅₀ 1 _{~50 n),} the.

The subscriber terminal unit 10 and the DSLAM 50 shown in FIG.
Is communicatively connected via the ISDN line 3 and the DOTS4
0 is an ISDN signal synchronization signal (SYN) to the DSLAM 50.
It is for supplying a predetermined network clock signal including C). The DSLAM 50 of FIG. 2 is the DS of FIG.
The LAM 20 is provided with an internal interface for transferring a predetermined network clock signal from the DOTS 40 and an internal interface for sequentially transferring the network clock signal to another DSLAM 50.

The network clock signal is shown in FIG. 3 by the ANNEX C method so that the transfer of the ADSL signal is synchronized according to the ISDN transfer standard and the phase of the transferred ADSL signal matches the phase of the ISDN signal. DOTS signal and 0.4 KHz reference clock (Reference
It is specified that the 32 Kbps synchronous data and the 64 KHz clock shown in FIG. 4 are selectively used. On the other hand, the 32 Kbps synchronous data and the 64 KHz clock shown in FIG.
The signal supplied to U-b is shown, and the signal actually transferred via the communication line is a differential clock signal.

The DOTS signal of FIG. 3 contains a sync signal marked in black every 8 KHz period. The standard and operation of the network clock signal are ITU G. 992.1 and ITU
G. 992.2 standard APPENDIX ANNEX
C, and detailed description thereof will be omitted in the present specification. The 32 Kbps synchronization data in FIG. 4 includes ISDN frame synchronization, and the clock signals shown in FIGS. 3 and 4 are half-cycle clock signals and actually have a cycle of 0.2 KHz.

That is, the ANNEX C method is based on ISD.
It is proposed to transfer the ADSL signal through the N line, and when the ISDN signal and the ADSL signal are transferred in the same cable, the ISDN signal is used so as to prevent the problem that interference occurs between the transfer lines of each signal. This is a method in which an ADSL signal is transferred by searching for a time zone in which it is not transferred.

At this time, since the DSLAM 50 should be synchronized with the ISDN network in order to find a time period during which the ISDN signal is not transferred, the DOTS 40 of FIG. 2 supplies the network clock signal to the DSLAM 50 directly connected thereto. , DSLAM50 which received the transfer of the network clock signal
However, the network clock signal is sequentially transferred to other DSLAMs 50 connected thereto.

The DSLAM 50 which has received the transfer of the network clock signal confirms the presence or absence of signal interference due to the simultaneous transfer of the ISDN signal and the ADSL signal, and searches for a time period when there is no signal interference, that is, a time period during which the ISDN signal is not transferred. To transfer the ADSL signal.

However, in the case of the conventional ADSL network system according to the above-mentioned ANNEX C standard, one DSLAM 50 is configured to receive the network clock signal directly from the DOTS 40 and then sequentially transfer it to the other DSLAM 50. Because there are many DSLA
A delay may occur in the network clock signal transferred through the M50, so that the DTSs may be sequentially connected to one DOTS 40.
There is a problem that the number of installed SLAM 50 is limited.

Further, since a large number of DSLAMs 50 are sequentially connected in series as shown in FIG.
When an abnormality occurs, the DSLAM 50 connected to the rear end of the corresponding DSLAM 50 has a problem that the supply of the network clock signal is interrupted.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a network synchronization clock signal of an ISDN network to a large number of DSLAMs without delay and to provide DOTS and DSLAM. An object of the present invention is to provide an ISDN network clock distribution device for ADSL connection, which can stably provide ADSL connection service through the ISDN line by preventing interruption of network clock signal supply due to a failure.

[0017]

In order to achieve the above-mentioned object, an ISDN network clock distribution device for ADSL connection communicates between a large number of subscriber terminals connected to an ISDN line and a network connection server. Connected ADSL
An apparatus for supplying an ISDN network synchronization clock to a plurality of digital subscriber line connection multiplexers for providing connection service, receiving at least one first network clock signal composed of a DOTS signal from an ISDN network clock transfer apparatus. A network clock signal receiving means for converting the TTL data of the positive and negative portions, and a predetermined IS from the TTL data of the positive and negative portions output from the network clock signal receiving means.
A network clock signal processing means for extracting and outputting the DN synchronization data and the clock signal, and the ISDN synchronization data and clock signal output from the network clock signal processing means are distributed to a plurality of output terminals in the same signal form. And a plurality of differential clock signal transmitting means for supplying the second network clock signals obtained by converting the output signals from the clock distributing means to differential clocks to a plurality of digital line connection multiplexers. It is characterized by being configured.

Further, the present invention further comprises a differential clock signal receiving means for receiving the second network clock signal supplied from another ISDN network clock distribution device and converting and outputting the second network clock signal into the ISDN synchronization data and the clock signal. The network clock signal processing means includes a synchronous clock extracting means for extracting the ISDN synchronous data and a clock signal from an output signal of the network clock signal receiving means, and a transfer through the synchronous clock extracting means and the differential clock signal receiving means. Check the operating conditions of at least two lines of ISDN synchronization data and clock signals, and check the ISDN of normal lines.
And a clock monitor and a selection means for selectively outputting the synchronous data and the clock signal.

Further, in the present invention, the synchronous clock extracting means performs a NOT operation on the positive polarity part TTL data output from the network clock signal receiving means and then outputs it at a predetermined transfer rate to extract ISDN synchronous data. The positive part TTL data and the negative part TTL data are
It is characterized in that it is configured to perform a D operation to extract a clock signal of a predetermined frequency.

The present invention further comprises oscillating means for oscillating a local clock having a predetermined frequency, and the network clock signal processing means uses the local clock and predetermined network synchronization data of the ISDN network provided in the internal storage means. Further comprises local clock generation means for generating the ISDN synchronization data and clock, and the clock monitor and selection means determines that all the output signals of the synchronization clock extraction means and the differential clock signal reception means are not in a normal state. In this case, the ISDN synchronization data and the clock generated from the local clock generating means are output.

In the present invention, the local clock generation means outputs the network synchronization data to the local clock to generate positive and negative ISDN synchronization data, and performs an AND operation on the ISDN synchronization data to determine a predetermined value. It is characterized in that it is arranged to generate a clock signal of frequency.

Therefore, according to the configuration described above, the network synchronization clock signal of the ISDN network is stably provided to a large number of DSLAMs.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 5 shows I according to the present invention.
FIG. 6 is a block configuration diagram showing a configuration of an ADSL network system to which the SDN network clock distribution device is applied, and the same configuration as that shown in FIG. 2 is given the same reference numeral, Detailed description is omitted.

A large number of network clock distribution devices 100 (100 _{1 to} 1000 _m ) are sequentially connected in series to the DOTS 40 of FIG. 5, and a large number of DSs are provided in each network clock distribution device 100.
The LAMs 50 (50 ₁ to 50 _p ) are connected in parallel and configured. In this case, the number of network clock distribution devices 100 to be installed is set to an appropriate number in consideration of the delay of the network clock signal.

The DOTS 40 of FIG. 5 supplies the DOTS signal of FIG. 3 as a network clock signal (hereinafter referred to as the “first network clock signal”) to the network clock distribution device 100 ₁ directly connected thereto, and Network clock distribution device 100
₁ converts the first network clock signal into 32 Kbps synchronous data which is a differential clock signal and 64 KHz (hereinafter referred to as "second network clock signal") as shown in FIG.

That is, FIG. 8 is a diagram showing the 32 Kbps synchronous data and the 64 KHz clock of FIG. 4 as a differential clock of a positive phase and a reverse phase. As is well known, the differential clock causes noise during high frequency data transfer. Because of its strong properties,
This clock is generally used during data communication.

The network clock distribution device 100 ₁ of the rear end, sequentially numerous serially connected network clock distribution device 100 ₂
.About.100 _m are respectively supplied with the second network clock signal of FIG. 9 from the network clock distribution device 100 connected to the front end thereof, and the network clock distribution device 10 connected to the rear end thereof.
0 to a second network clock signal of the same form. Then, each network clock distribution device 100 is supplied with the second network clock signal to a large number of DSLAMs 50 connected in parallel.

Further, the network clock distribution device 100 of FIG.
When the supply of the first network clock signal from the DOTS 40 is interrupted and the supply of the second network clock signal from the other network clock distribution device 100 is also interrupted, the network clock signal of FIG. After being generated and converted into the second network clock signal, it is supplied to the other network clock distribution device 100 and the DSLAM 50.

The embodiment of the present invention will be described in more detail with reference to FIGS. 6 to 8. FIG. 6 is a block diagram showing an internal structure of an ISDN network clock distribution device for ADSL connection according to an embodiment of the present invention, which is a network clock signal receiving unit 110, a differential clock signal receiving unit 120, The oscillator 130, the clock signal processor 140, the clock status display unit 150, the clock distributor 160, and the differential clock signal transmitter 170 are provided.

The network clock signal receiving section 110 of FIG.
After receiving the DOTS signal of FIG. 3 which is a bipolar signal from the OTS 40, the DOTS signal is converted and output as 64 Kbps TTL data divided into a positive electrode portion and a negative electrode portion as shown in FIG.

That is, since the bipolar signal is a main transfer signal of a transfer system using a metal cable as a transfer medium,
This is converted into a TTL signal suitable for digital signal processing. The network clock signal receiving unit 110 is a line interface transceiver (Transceiver) and uses, for example, XRT6164A manufactured by EXAR.

On the other hand, the XRT 6164A is an element configured to receive a bipolar signal and output an active-low level TTL signal. As shown in FIG. 64KbpsT with (-) clock displayed at low level and (+) clock and ground displayed at high level
The negative portion of the 64 Kbps TTL data is output as the 64 Kbps TTL data in which the (-) clock and ground of the DOTS signal are displayed at high level and the (+) clock is displayed at low level.

The differential clock signal receiving section 120 shown in FIG.
The second network clock signal of FIG. 9 which is a differential clock is received from another network clock distribution device 100, and the positive phase TTL is received.
It is for converting into single data, and the converted data is transferred to the clock signal processing unit 140 described later. The differential clock signal receiving unit 120 is, for example, Nati
DS26L from onal Semiconductor
S32 is used.

Each of the network clock signal receiving section 110 and the differential clock signal receiving section 120 of FIG. 6 is shown with only one input / output port, but it is also possible to configure this with two input / output ports. . In this case, the network clock signal receiving unit 110 receives the two-line DOTS signals from the DOTS 40, and the differential clock signal receiving unit 120 receives the two second network clock signals from the two network clock distribution devices 100.

The oscillator 130 shown in FIG. 6 is, for example, 16.38.
The clock signal processing unit 140, which will be described later, is for oscillating a 4 MHz local clock.
The 32 Kbps synchronous data and the 64 KHz clock of FIG. 4 are generated using the oscillated local clock and the predetermined synchronous data provided in the internal storage means.

The clock signal processing section 140 of FIG. 6 includes a network clock signal receiving section 110 and a differential clock signal receiving section 12.
0 and the output signal of the oscillator 130 from 32 Kbps in FIG.
This is for extracting / generating the synchronous data and 64KHz clock, checking the presence / absence of a fault in each output line, and selectively outputting the 32Kbps synchronous data and the 64KHz clock supplied from the normal line.
(Programmable Logic Device
e), the detailed description of which will be given later.

The clock status display unit 150 of FIG. 6 operates the first and second network clock signals supplied from the DOTS 40 and another network clock distribution device 100 based on a predetermined control signal output from the clock signal processing unit 140. The status and the output line of the 32 Kbps synchronous data currently output and the 64 KHz clock are visually displayed by using an LED or the like.

The clock distribution unit 160 of FIG. 6 is for distributing and outputting the 32 Kbps synchronous data and the 64 KHz clock output from the clock signal processing unit 140 to the same signal form through a large number of output terminals. In this case, 32Kbps synchronous data and 64KHz clock,
For example, the data is distributed to 48 output terminals. The clock distribution unit 160 is a clock driver, and for example, Integra
An IDT74FCT807 manufactured by Rated Device Technology, Inc. is used.

The differential clock signal transmitter 170 (1 in FIG.
70 _{1 to} 170 _x ) are 32 Kbps synchronous data transferred from each output terminal of the clock distribution unit 160 and 64 KHz.
Each of the clocks is converted into a differential clock as shown in FIG. 9, and the converted signal is a second network clock signal, and a large number of DSLs connected to the second network clock signal.
It is transferred to the AM 50 or the network clock distribution device 100. The differential clock signal transmission unit 170 is a differential line driver, and may be, for example, a National Semiconductor.
DS26LS31 manufactured by Uctor is used.

Hereinafter, the clock signal processing unit 140 will be described in more detail with reference to FIG. FIG. 7 is a functional block diagram functionally showing the configuration of the clock signal processing unit 140, which includes a synchronous clock extracting unit 141, a clock monitoring unit 142, a local clock generating unit 143, a clock selecting unit 144, and a display processing unit 145. , And are configured.

The synchronous clock extraction unit 141 of FIG. 7 uses the 64 Kbps TTL data (see FIG. 8) of the positive electrode portion and the negative electrode portion output from the network clock signal receiving unit 110, as shown in FIG.
The 32 Kbps synchronous data and the 64 KHz clock are extracted. The synchronous clock extracting unit 141 performs NOT operation on the positive portion 64 Kbps TTL data of FIG. 8 and then outputs it to 32 Kbps to extract the 32 Kbps synchronous data of FIG. , AND data of the positive electrode portion TTL data and the negative electrode portion TTL data of FIG.
Extract the Hz clock.

The clock monitor unit 142 of FIG. 7 includes a synchronous clock extraction unit 141 and a differential clock signal reception unit 120.
The operation state of the 32 Kbps synchronous data and the operation state of the 64 KHz clock which are applied from the CPU are confirmed, and the predetermined clock operation state information is output to the clock selecting unit 144 described later.

The clock operation state information is DO of FIG.
32Kbps synchronous data and 64KHz clock extracted from the first network clock signal supplied by the TS40, and 32Kbps synchronous data and 64K extracted from the second network clock signal supplied from another network clock distribution device 100.
It is composed of information indicating whether the Hz clock is normal or abnormal.

The local clock generator 143 shown in FIG.
16.384 MHz supplied from the oscillator 130 of FIG.
The local clock of 32 KHz is divided to generate a 32 KHz clock, and the generated 32 KHz clock and predetermined network synchronization data provided in the internal storage means are used to generate 32 Kbp of FIG.
It is for generating s synchronization data and a 64 KHz clock. The network synchronization data is, for example, 32 Kb in FIG.
Data extracted from the ps synchronization data during a 0.2 KHz cycle is used.

The local clock generator 143 outputs the network synchronization data to the 32 KHz clock to generate the 32 Kbps synchronization data of the positive and negative portions, respectively, and ANDs the two 32 Kbps synchronization data to obtain 6
Generate a 4 KHz clock.

The clock selection unit 144 of FIG. 7 is connected to the output ends of the synchronous clock extraction unit 141, the differential clock signal reception unit 120, and the clock monitor unit 142, respectively, and in a normal state based on the clock operation state information. This is for selecting a certain 32 Kbps synchronous data and a 64 KHz clock and outputting them as the source data of the second network clock signal.

Then, the clock selection section 144 of FIG.
Synchronous clock extraction unit 141, differential clock signal reception unit 1
If it is determined that all of the 20 output lines are not in the normal state, 32 generated by the local clock generation unit 143
The Kbps synchronous data and the 64 KHz clock are output as the source data of the second network clock signal.

The display processing unit 145 shown in FIG. 7 is connected to one end of the clock selecting unit 144, and the synchronous clock extracting unit 141.
6 and controls the clock status display section 150 of FIG. 6 based on the clock operation status information output from the differential clock signal receiving section 120 to output the clock operation status for each output line and the current clock selection section 144. 32 Kb
It is for displaying the output line of ps synchronization data and 64 KHz clock.

Therefore, the user is required to select the clock status display section 15
It is confirmed whether the network clock signal supplied from the DOTS 40 or another network clock distribution device 100 is abnormal through 0, and at present, based on the network clock signal of any line, 3
It can be confirmed whether 2 Kbps synchronous data and 64 KHz clock are output.

Hereinafter, the ADS having the above-mentioned configuration
The operation of the ISDN network clock distribution device for L connection will be described. First, the DOTS 40 supplies the network clock signal of FIG. 3 to the ISDN network in order to supply the frame synchronization of the ISDN signal. On the other hand, the network clock distribution device 100 of FIG. 5 is connected to the output terminal of the DOTS 40 and is supplied with a clock signal of the same form as the DOTS signal of FIG. 3 supplied to the ISDN network as the first network clock signal.

The network clock distribution device 100 connected in series to the rear end of the other network clock distribution device 100 of the network clock distribution device 100 of FIG. 5 is connected to the ISDN from the network clock distribution device 100 connected to the front end thereof. Differential 32 Kbps synchronization data and 64 KHz clock for matching the network and frame synchronization are supplied as the second network clock signal.

After that, the network clock signal receiving unit 11 of FIG.
0 is converted into the first network clock signal, which is the bipolar data supplied from the DOTS 40, into 64 Kbps TTL data divided from the positive electrode part and the negative electrode part of FIG. 8 and output to the clock signal processing unit 140 of FIG. .

Then, the differential clock signal receiving section 1 of FIG.
The second network clock signal 20 supplied from the other network clock distribution device 100 has a positive phase of 32 Kb as shown in FIG.
ps sync data and 64KHz clock, ie TTL
The data is converted into single data and output to the clock monitor unit 142 and the clock selection unit 144 in FIG. 7.

The oscillator 130 shown in FIG.
The local clock of 6.384 MHz is oscillated and supplied to the clock signal processing unit 140.
0 uses the oscillated local clock as source data for generating 32 Kbps synchronous data and 64 KHz clock.

On the other hand, the synchronous clock extraction unit 141 of FIG.
6 performs a NOT operation on the positive polarity portion 64 Kbps TTL data output from the network clock signal receiving unit 110 of FIG. 6 and outputs the result to 32 Kbps to extract the 32 Kbps synchronous data of FIG. 4 and the positive polarity portion TTL data of FIG. , The negative electrode portion TTL data is AND-operated to obtain 6 in FIG.
Clock monitor unit 142 that extracts a 4 KHz clock
To the clock selection unit 144.

After that, the clock monitor unit 142 of FIG.
Is 32 Kbps synchronous data transferred from the synchronous clock extracting unit 141 and the differential clock signal receiving unit 120 and 64 K
Whether or not the Hz clock is abnormal is confirmed, and the clock operating state information is output to the clock selecting unit 144 in FIG. 7. The clock selecting unit 144, based on the clock operating state information, outputs the 32 Kbps synchronous data in the normal state and 64
The KHz clock is selected and output to the clock distribution unit 160.

At this time, as a result of the interpretation of the clock operation state information, it is determined that the supply of the first network clock signal from the DOTS 40 is interrupted and the supply of the second network clock signal from the other network clock distribution device 100 is also interrupted. 7 (including the case where the first and second network clock signals in an abnormal state are supplied), the clock selection unit 144 of FIG. 7 distributes the 32 Kbps synchronous data and the 64 KHz clock supplied from the local clock generation unit 143. Output to the unit 160. The supply interruption / abnormal state of the first and second network clock signals is confirmed by whether or not the supply of the 64 KHz clock for 2 clocks or more is interrupted.

The display processing unit 145 of FIG. 7 receives the clock operating state information from the clock selecting unit 144 and displays the signal states of the synchronous clock extracting unit 141 and the differential clock signal receiving unit 120, respectively. ,
Visually display the selected 32 Kbps sync data and 64 KHz clock output line. This is performed through the clock status display unit 150 provided with the output line status display LEDs of the network clock distribution device 100.

After that, the clock distributor 160 of FIG.
32 Kb of positive phase output from the clock selection unit 144
The ps synchronization data and the 64 KHz clock are distributed and output in the same signal form through, for example, 48 output terminals, and the differential clock signal transmission unit 170 of FIG.
From the positive phase 32 Kbps synchronous data and the 64 KHz clock, respectively, to the second network clock signal in FIG. 9, that is, the differential 32 Kbps synchronous data and the 64 KHz clock.
It is converted into a clock and transferred to the network clock distribution device 100 and a large number of DSLAMs 50 which are communicatively connected to the clock.

Then, the network clock distribution device 100 of FIG.
From the second network clock signal, that is, the network synchronization clock signal, is transmitted to the DSLAM 50 by the ISDN signal and the ADSL.
Check for signal interference due to simultaneous signal transfer, and
The ADSL signal is transferred by searching for a time zone where there is no interference between the DN signal and the ADSL signal.

Therefore, in the case of this embodiment, one DOTS
40 is connected in series to a relatively small number of network clock distribution devices 100, and each network clock distribution device 100 has a large number of DSs.
The LAM 50 is connected in parallel and is configured to supply the network synchronization clock signal of the ISDN network at the same time, so that the transfer delay time of the network clock signal can be significantly reduced.

That is, when the number of DSLAMs 50 to which the network clock signal is supplied through the DOTS 40 is 90, for example, the conventional ADSL network system of FIG. Since one network clock distribution device 100 supplies network clock signals to up to 48 DSLAMs 50 at the same time, only two clock delays of the network clock distribution device 100 are generated, and the transfer delay is greatly reduced.

Then, each network clock distribution device 100
By generating another network clock signal through the internal local clock generation means and substituting the network clock signal generated depending on whether the clock supply of the DOTS 40 and the other network clock distribution device 100 is interrupted, D
It is possible to prevent interruption of the network clock signal supply due to an abnormal operation of the OTS 40 or the DSLAM 50.

[0064]

As described above, according to the present invention, the DO
A large number of ISDN network synchronization clocks supplied from TS
Can supply to SLAM without time delay, DOTS and DSL
It is possible to stably provide the ADSL connection service using the ISDN line by preventing the interruption of the network synchronization clock supply due to the abnormal operation of the AM.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of an ADSL network system according to a conventional ANNEX A system.

FIG. 2 is a block diagram showing a configuration of a conventional ADSL network system based on the ANNEX C system.

FIG. 3 is a waveform diagram showing a DOTS signal according to the ANNEX C system and a 0.4 KHz reference clock.

FIG. 4 32 Kb for looking for ISDN frame sync
FIG. 7 is a waveform diagram showing ps synchronization data and a 64 KHz clock.

FIG. 5 is a block diagram showing a configuration of an ADSL network system in which the ISDN network clock distribution device according to the present invention is used.

FIG. 6 is a block diagram showing an internal configuration of an ISDN network clock distribution device for ADSL connection according to an exemplary embodiment of the present invention.

7 is a functional block diagram functionally showing the configuration of a clock signal processing section 140 shown in FIG.

8 is a waveform diagram showing the 64 Kbps TTL data of the positive and negative electrodes output from the network clock signal receiving unit 110 shown in FIG.

FIG. 9: Differential 32 for searching for frame synchronization of ISDN
It is a wave form diagram showing Kbps synchronous data and a 64 KHz clock.

[Explanation of symbols]

10 subscriber terminal units 20, 50 (50 ₁ to 50 _p ) digital subscriber line connection multiplexer (DSLAM) 30 network connection server (NAS) 40 network clock transfer device (DOTS) 100 (100 _{1 to} 100 _m ) network Clock distribution device 110 Network clock signal receiver 120 Differential clock signal receiver 130 Oscillator 140 Clock signal processor 141 Synchronous clock extractor 142 Clock monitor 143 Local clock generator 144 Clock selector 145 Display processor 150 Clock status display Unit 160 Clock distribution unit 170 (170 _{1 to} 170 _x ) Differential clock signal transmission unit

Continued front page    F term (reference) 5K028 AA14 BB01 KK01 KK03 NN01                       NN05 NN32                 5K047 AA11 BB17 CC02 GG03 GG08                       GG11 GG16 GG22                 5K050 AA07 AA13 BB03 BB06 BB12                       DD21

Claims (7)

[Claims] 1. An ISDN network synchronization clock is supplied to a plurality of digital subscriber line connection multiplexers which are communicatively connected between a plurality of subscriber terminal units connected to an ISDN line and a network connection server to provide an ADSL connection service. In the supplying device, a network clock signal receiving means for receiving at least one first network clock signal composed of a DOTS signal from the ISDN network clock transfer device and converting the network clock signal into positive and negative TTL data, and the network clock signal. Network clock signal processing means for extracting and outputting predetermined ISDN synchronization data and a clock signal from the TTL data of the positive and negative portions output from the receiving means, and the ISDN output from the network clock signal processing means.
Clock distribution means for distributing and outputting the synchronization data and the clock signal to a plurality of output terminals in the same signal form, and a plurality of digital second network clock signals obtained by converting the output signals from the clock distribution means into differential clocks. An ISDN network clock distribution device for connecting an asymmetric digital subscriber line, comprising: a plurality of differential clock signal transmitting means for supplying to a line connection multiplexer. 2. A differential clock signal receiving means for receiving the second network clock signal supplied from another ISDN network clock distribution device, converting the second network clock signal into the ISDN synchronous data and the clock signal, and outputting the clock signal. The network clock signal processing means is transferred through the synchronous clock extracting means for extracting the ISDN synchronization data and the clock signal from the output signal of the network clock signal receiving means, the synchronous clock extracting means and the differential clock signal receiving means. A clock monitor and a selecting means for checking the operating states of the ISDN synchronization data and the clock signal of at least two lines and selectively outputting the ISDN synchronization data and the clock signal of the normal line. The ISDN network clock component for connecting an asymmetric digital subscriber line according to claim 1. Apparatus. 3. The synchronous clock extracting means performs a NOT operation on the positive polarity part TTL data output from the network clock signal receiving means, and then outputs the data at a predetermined transfer rate to ISD.
The asymmetric digital subscriber according to claim 2, wherein the N-sync data is extracted and the positive polarity TTL data and the negative polarity TTL data are AND-operated to extract a clock signal of a predetermined frequency. ISDN network clock distribution device for line connection. 4. The oscillating means for oscillating a local clock having a predetermined frequency, wherein the network clock signal processing means uses the local clock and predetermined network synchronization data of an ISDN network provided in an internal storage means to perform the ISDN. Further comprising local clock generating means for generating synchronous data and a clock, wherein the clock monitor and selecting means determines that all output signals of the synchronous clock extracting means and the differential clock signal receiving means are not in a normal state, 3. The ISDN network clock distribution device for connecting an asymmetric digital subscriber line according to claim 2, wherein the ISDN synchronization data and the clock generated from the local clock generating means are output. 5. The local clock generating means outputs the network synchronization data to the local clock to generate positive and negative ISDN synchronization data, respectively, and ANDs the ISDN synchronization data to obtain a clock of a predetermined frequency. An ISDN network clock distribution device for asymmetric digital subscriber line connections according to claim 4, characterized in that it is arranged to generate signals. 6. An operating state of the first and second network clock signals supplied from the ISDN network clock transfer device and another network clock distribution device based on a predetermined control signal of the clock signal processing means, and is currently output. 5. The ISDN network for connecting an asymmetric digital subscriber line according to claim 4, further comprising clock status display means for visually displaying an output line of ISDN synchronous data and clock. Clock distribution device. 7. The first network clock signal is an ANNEX including an ISDN frame synchronization signal every 8 KHz cycle.
It is a bipolar 64 Kbps DOTS signal according to the C method, and the ISDN synchronization data and clock signal are positive phase 3
7. The asymmetric digital subscriber line according to claim 1, wherein the second network clock signal is 2 Kbps synchronous data and 64 KHz clock, and the second network clock signal is differential 32 Kbps synchronous data and 64 KHz clock. ISDN network clock distribution device for connection.