JP5683142B2 - Information processing apparatus or information processing method - Google Patents

Description

  The present invention relates to an information processing apparatus or an information processing method using the information processing apparatus.

  In a configuration in which a plurality of devices are connected using a high-speed transmission technology such as PCI (Peripheral Component Interconnect) -Express, normal communication may not be performed if different reference clocks are used between the connected ports. In particular, when operating with a reference clock to which a spread spectrum clock (hereinafter referred to as SSC) is applied as a measure against EMI (Electro Magnetic Interference), the frequency deviation caused by mutual frequency fluctuations increases. Connection between them was difficult. Therefore, a configuration in which SSC is not applied to the serial communication unit and SSC is applied only to other portions (Patent Document 1), or a configuration in which the same reference clock is supplied to each port from a fixed clock supply source. (Patent Document 2) and the like are used.

JP 2001-148690 A JP2009-043818

  However, when the devices use different reference clocks as in Patent Document 1, a communication failure may occur if the reference clock of one device fluctuates. Further, as in Patent Document 2, if the configuration is such that a common reference clock is always received from an external device and is operated, when the operation of the external device is suspended, the reference clock is always supplied to the device that is supplied with the reference clock. Inability to receive the clock supply causes inconvenience in operations other than communication with an external device.

In order to solve the above-described problem, an information processing apparatus according to the present invention receives the first synchronization signal from an external apparatus that generates a first synchronization signal subjected to spread spectrum processing, and communicates with the external apparatus. an apparatus, first receiving and generating means for generating a second synchronization signal after the spread spectrum processing, information indicating a frequency variation range of the first synchronizing signal from said external device at a predetermined frequency variation range and communication means, the first synchronization signal and before Symbol second control means for selecting one of the synchronization signals based on the frequency fluctuation range of the synchronizing signal, the external device based on the selected synchronization signal of the control means and having a second the communication means for communicating with.

  The present invention suppresses a host-to-host connection failure caused by a frequency deviation of a synchronization signal (reference clock) even when the information processing apparatus and the external apparatus operate with synchronization signals having different frequency fluctuation ranges. be able to.

FIG. 3 is a block diagram illustrating connection between hosts according to the first exemplary embodiment. FIG. 2 is a block diagram illustrating an internal configuration of each information processing apparatus according to the first embodiment. 3 is a flowchart illustrating processing of the communication system according to the first embodiment. FIG. 6 is a block diagram illustrating an internal configuration of each host according to the second embodiment. 10 is a flowchart illustrating processing of the communication system according to the second embodiment. 10 is a flowchart illustrating an operation for disconnecting a connection between hosts according to the second exemplary embodiment. It is a block diagram which shows the internal structure of each host in other embodiment.

<Embodiment 1>
First, an overall outline of the communication system according to the first embodiment which is an embodiment of the present invention will be described.

  FIG. 1 is a block diagram showing connections between a plurality of information processing apparatuses (hereinafter referred to as hosts) constituting the data communication system of the present invention. The host 110 and the host 120 are connected by a high-speed serial interface, and in this embodiment, the PCI-Express link 130 is applied as a high-speed serial interface to perform data communication between the hosts. PCI-Express is a type of input / output interface that can communicate using a clock subjected to spread spectrum processing.

  FIG. 2 is a block diagram showing an internal configuration of each host. The CPU 111 (or 121) controls the entire system of the host 110 (or 120), and performs data communication with each device connected by a PCI-Express link via the root complex 112 (or 122). The switch device 113 (or 123) and the endpoint device 114 (or 124), which are PCI-Express devices, have a PCI-Express hierarchy (a tree structure based on the root complex) with the root complex 112 (or 122) as the highest level. Can be configured. Note that there may be a plurality of endpoint devices 114 (or 124), and a plurality of switch devices may exist in a plurality of layers.

  The root complex 112 (or 122) communicates with the endpoint device 114 (or 124) located at a lower level of the hierarchy via the switch device 113 (or 123) functioning as a bridge. The switch device 113 (or 123) includes a port for connecting an external device different from the endpoint device 114 (or 124), and can be connected to the external host via the PCI-Express link 130. It has become. (That is, the root complex 112 can communicate with the endpoint device 124 via the switch devices 113 and 123 after establishing the host-to-host connection 130.)

  The SSC generation unit 115 (or 125) generates a reference clock to be supplied to the PCI-Express device, applies SSC (spread spectrum) to the reference clock, and applies a SSC (hereinafter referred to as an SSC clock). Is output. Further, the SSC control signal 116 (or 126) is a signal from the CPU 110 (or 120), and is a signal for setting the presence / absence of SSC application of the SSC generation unit 115 and parameters (frequency variation range, etc.) when performing SSC. It is.

  The SSC clock 118 output from the SSC generation unit 115 is supplied to the host 110 and the external host 120. The SSC clock 128 output from the SSC generation unit 125 is supplied to the host 120. The clock switching unit 127 selects either the SSC clock 118 output from the SSC generation unit 115 or the clock 128 supplied from the host 120 and outputs the reference clock 129. In the host 110, the SSC clock 118 output from the SSC generation unit 115 is supplied as it is to the PCI-Express device inside the host 110 as the reference clock 119, and these devices operate based on the reference clock 119.

  As described above, the host 110 and the host 120 are configured to be able to supply the reference clock generated by the respective clock generation units (SSC generation units 115 and 125 in the figure) to their own PCI-Express devices. Yes. Here, the host 120 further has a configuration in which another reference clock supplied from the host 110 can be supplied to its own PCI-Express device instead of the reference clock generated by the SSC generation unit 125.

  FIG. 3 is a flowchart for explaining processing of the data communication system having the above-described configuration. Here, when the host 110 and the host 120 are to be connected, an operation of the host 120 that receives a clock supply from the host 110 and performs link reconnection between each PCI-Express device will be described. Further, in a state until the connection between the hosts is detected (first communication state), the host 110 and the host 120 use the reference clock generated inside each host to link the PCI-Express devices. Is maintained (first connection state), but the operation is based on a standard procedure based on the definition of PCI-Express and the like, and thus the description thereof is omitted.

  First, in step S301, when the switch device 123 of the host 120 detects connection with the host 110, which is an external host, the process proceeds to step S302. When the root complex 122 determines that the reference clock needs to be switched on the host 120 side in step S302, the root complex 122 disconnects the link between each PCI-Express device of the host 120 in step S303. (At this time, the link between the PCI-Express devices on the host 110 side is not disconnected.) Furthermore, when the clock switching unit 127 is supplied with the reference clock from the host 110 in step S304, the clock switching unit 127 receives each PCI- The clock 128 (first synchronization signal) supplied to the Express device is switched to the reference clock 118 (second synchronization signal) from the host 110. If the root complex 122 detects the reference clock (external clock) supplied from the host 110 in step S305, the process proceeds to step S306. When the host 120 reaches a state where it can be connected to the host 110 in step S306, the root complex 122 executes link reconnection processing between each PCI-Express device in step S307, and switches based on the reference clock 118. The inter-host connection 130 is established (second communication state) by connecting the device 123 and each device (including the host 110) (second connection state).

  In this embodiment, it is assumed that a clock switching unit is provided in a host that needs to switch clocks in advance. For example, when the variation range (corresponding to the modulation range) of one host is included in the variation range of the frequency of the reference clock of the other host, a clock switching unit is provided in advance for the other host. That is, a device for which the fluctuation range of the synchronization signal received from the outside is smaller than the fluctuation range of the synchronization signal generated by itself is provided with a clock switching unit as a host that needs to switch the clock.

  As described above, according to the first embodiment, it is possible to perform the host-to-host connection using the high-speed serial interface while suppressing the problem of the host-to-host connection caused by the frequency deviation caused by different reference clocks. Further, on the host side where there is no need to switch the clock, the connection destination can be expanded while maintaining the PCI-Express link connection.

<Embodiment 2>
Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram illustrating an internal configuration of each host according to the second embodiment. 2 that are not structurally different from the elements of FIG. 2 already described are given the same reference numerals, and are not described unless they are structurally and functionally different.

  In this embodiment, a plurality of hosts have clock switching units (117, 127), respectively, and each host can switch clocks with its own clock switching unit (117, 127). The communication unit 401 included in the host 110 and the communication unit 402 included in the host 120 exchange data through the second inter-host connection 403 (second communication unit) other than the PCI-Express link 130 (first communication unit). Is possible.

  This inter-host connection 403 applies asynchronous serial communication using UART (Universal Synchronous Receiver Transmitter Transmitter) or the like. Communication between hosts 403 adds a start bit before fixed-length data, a stop bit after data, and adds a synchronization signal to the data itself every time data is transmitted / received. No signal line is required. Therefore, the host-to-host connection 403 can exchange information with each other even when the PCI-Express link is not connected. On the other hand, in the communication by the host-to-host connection 403, it is difficult to add a synchronization signal to the data and to increase the data length, so extra traffic is generated for the synchronization signal. Accordingly, the communication efficiency is inferior to a method using a synchronization signal such as a clock signal for synchronization such as PCI-Express.

  FIG. 5 is a flowchart illustrating processing of the data communication system according to the second embodiment. In the state where the host 110 and the host 120 are not connected, as described in the first embodiment, the host 110 and the host 120 operate link connection between each PCI-Express device using the reference clock generated by each. I am letting.

First, in step S501, when the switch device 123 of the host 120 detects a connection with the host 110 that is an external host, in step S502, the CPU 121 activates the communication unit 402 to start communication via the host-to-host connection 403, so Set up. When communication preparation by the communication unit 402 is completed in step S503, the CPUs 111 and 121 of the respective hosts relate to the reference clock applicable to their own PCI-Express device in step S504 via the respective communication units 401 and 402. The parameters (applicable clock frequency range, presence / absence of SSC function, etc.) are notified to the connection destination host as drive information. In step S505, the CPUs 111 and 121 select a reference clock to be used for communication with the external host based on the drive information received from the external host. (Selection criteria will be described later.)
After the reference clock is selected, the reference clock switching process is executed in the same manner as the procedure from step S303 to S307 in FIG. 3, and each host shifts to a mode in which it operates with the same reference clock.

  Here, the range of the clock frequency applicable to each PCI-Express device for each host indicates the frequency fluctuation range (corresponding to the modulation range) of the reference clock to which SSC is applied. For example, in the state before the connection between the hosts is established, when the frequency variation range of the reference clock applied to each PCI-Express device in the host 120 is narrower than the frequency variation range of the host 110 If the host 120 uses the reference clock supplied from the host 110, a malfunction may occur. Therefore, in step S505 described above, a reference clock having a variation range included in the variation range of the reference clock of another host is selected.

The PCI-Express standard (Base 1.1) is based on 100 MHz and is + 0% to -0.5% from the standard (corresponding to 99.5% to 100.0% when the standard is 100%). It is defined so that modulation is possible in the range (down spread). For example, when the modulation range of the reference clock of the host 120 is + 0% to −0.40% and the modulation range of the reference clock of the host 110 is + 0% to −0.45%, the reference clock of the host 120 If so, each device of the host 110 is also within the applicable range, so it is considered that there is little trouble. Therefore, in this case, the CPU 111 of the host 110 selects the reference clock of the host 120 in step S505, and the clock switching unit 117 switches the reference clock in subsequent steps. (In actuality, the clock switching unit of the host other than the host 120 is switched to use the reference clock of the host 120.)
In consideration of the case where the frequency variation ranges are the same, it is determined in advance so that which host clock is used as the reference clock is uniquely determined based on the ID or priority of each host. It may be set. In that case, information such as IDs and priority orders of the respective hosts may be exchanged by the communication units 401 and 402.

  In this way, the respective hosts check each other's operating conditions, select the reference clock supply source, and then switch the reference clock. In addition, the SSC generator built in each host can adjust the presence / absence of SSC and the frequency fluctuation level based on the SSC control signal, which is different from the case where each host operates with a different reference clock. It is also possible to generate and supply a reference clock (third synchronization signal). For example, if the frequency variation range of each host is different and is not in an inclusive relationship, a frequency in the common variation range of the frequency variation range of each host is generated, and the frequency in this common variation range is created in each host. May be used.

  FIG. 6 is a flowchart illustrating processing when the connection between the hosts is disconnected in the data communication system according to the second embodiment and each host again shifts to a mode in which it operates with its own reference clock. The following describes how the host 110 receives a disconnection request from the host 120 and disconnects the connection between the hosts, and the host 110 continues to operate with its own reference clock.

  In step S601, when the communication unit 401 receives a notification requesting disconnection from the communication unit 402 of the host 120 through the host-to-host connection 403, the CPU 111 of the host 110 switches the reference clock according to the clock supply status in step S602. Determine if necessary.

  In step S603, when the reference clock is supplied from the SSC generator 115 of the reference clock and the operation can be continued with the supplied clock (the hosts 110 and 120 operate with the clock 118 generated by the SSC generator 115). The CPU 111 determines that clock switching is unnecessary, and the CPU 111 notifies the host 120 of permission to disconnect the connection via the communication unit 401. On the other hand, if the source of the reference clock is the host 120, the link between the PCI-Express devices is temporarily disconnected by the root complex 112 in order to switch the reference clock to the output of the built-in SSC generation unit 115 in step S604. To do. When the link disconnection is completed and preparation for switching the clock is completed, the host 120 is notified of permission to disconnect the connection via the communication unit 401 in step S605.

  In step S606, the CPU 111 controls the clock switching unit 117 so that the clock supplied from the built-in SSC generation unit is supplied as a reference clock to each PCI-Express device. When the clock switching unit 117 starts supplying the reference clock from the SSC generation unit 115 and the reconnection start timing is reached in step S607, the route complex 112 executes reconnection of the link between each PCI-Express device in step S608. Is done.

  When the link is reconnected by the route complex 112, the host 110 operates in such a manner as to control each PCI-Express device based on the reference clock supplied from the built-in SSC generation unit. In step S609, the SSC generation unit 115 stops the clock supply to the host 120 and completes the disconnection between the hosts.

  After notifying the disconnection request to the other host, the host is prevented from shifting to the suspension / disconnection until receiving a disconnection permission notification from the other host.

  As described above, according to the second embodiment, it is possible to flexibly cope with changing the system configuration by establishing a connection with another host while maintaining the operation state of the own host, and suspending / disconnecting another connected host. It becomes possible to do.

  In addition, in the method in which the SSC is not applied to the serial communication unit as in Patent Document 1, the EMI countermeasure effect by the SSC may be insufficient. However, in this embodiment, the SSC is also applied to the communication unit. The EMI resistance is improved as compared with the first method.

<Other embodiments>
In the present embodiment, the host-to-host connection PCI-Express link 130 transmits and receives drive information between hosts instead of the host-to-host connection 403 in the second embodiment.

  In the following, based on FIG. 7, each configuration is not functionally different from that of the above-described embodiment, and thus the description thereof is omitted, and the operation at the time of connection between the hosts will be mainly described by the host 120. When the switch device 123 of the host 120 detects a connection with the host 110 that is an external host, the root complex 122 temporarily disconnects the link between each PCI-Express device. Further, the CPU 121 controls the SSC control signal 116 to generate a reference clock to which the SSC is not applied from the SSC generator 115 and supply it to the internal and external hosts. In the configuration of the present embodiment, it is assumed that the host that is the source of the reference clock in the information exchange that is performed when connection is detected is determined in advance in a register (not shown) or the like.

  Similarly, the host 110 similarly disconnects the link between each PCI-Express device, switches to the reference clock supplied from the host 120, and reconnects the link of each internal PCI-Express device so that both do not perform SSC. A common reference clock is obtained in the state and connected. In this way, by connecting with a common reference clock that does not apply SSC, each host described above can avoid communication problems caused by differences in frequency or the like, and exchange necessary information.

  Subsequent operations are the same as the processing after step S504 described in the second embodiment (including the processing of steps S303 to S307 in FIG. 3), and each host operates with respect to each internal PCI-Express device. To notify the destination host of applicable reference clock conditions. Further, an appropriate reference clock is selected based on the notified information, and a process of switching to the selected clock is executed, and each host shifts to a mode in which it operates with the same reference clock.

  The control procedure at the time of disconnection is basically the same as that described with reference to FIG. 6 in the second embodiment, but information exchange regarding the disconnection request and the disconnection permission notification is made to the inter-host connection PCI-Express link 130. Is different in that Each host needs to maintain the supplied reference clock until each host switches to a reference clock generated internally and starts operation. For this reason, control is performed so that the supply of the clock is stopped after a certain time from when the disconnection permission notification is sent.

  As described above, in this embodiment, information on each host is acquired while switching between the first communication method that modulates the clock used for communication synchronization and the second communication method that does not modulate the clock used for communication synchronization. Therefore, compared with the second embodiment, although the reconnection process of the link with each device is necessary, the same effect as the second embodiment can be obtained without the second inter-host connection 403.

  The present invention is not limited to the above-described embodiment, and is a case where a plurality of devices are connected using a transmission technique synchronized with a clock other than PCI-Express, and at least one of the devices varies the frequency of the reference clock. In the case of using the connection method, the connection failure due to the frequency difference between the hosts can be suppressed. Further, although the configuration in which two hosts are connected has been described, it goes without saying that the above-described problem can be similarly solved even when three or more hosts are connected and linked.

  In the above-described embodiment, description is made using PCI-Express, but SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), FB-DIMM (Fully Buffered DIMM), or the like is used. Similar effects can be obtained.

  The SSC generator that generates the synchronization signal may be a PLL (Phase Lock Loop) that receives a clock from outside the apparatus and changes the frequency at a predetermined rate. Although not described in detail in the above embodiment, the drive information may be set in advance in a register of the communication unit and output to an external host when necessary. At that time, the host that supplies the reference clock is selected by comparing the drive information received from the external host with the drive information of its own host (corresponding to the selection of the synchronization signal), and the switching unit is controlled. The setting without SSC may be handled in the same manner as the setting with SSC. For example, when there is no SSC, the expression of PCI-Express may be handled as down spread of 0%. However, frequency fluctuation (error) due to the circuit configuration itself of the apparatus is ignored for the setting of SSC.

  In the above-described embodiment, the serial communication method is described. However, the present invention is applied to other communication methods such as a parallel method as long as the communication method is based on a timing signal such as a clock. Thus, the same effect can be obtained.

  In the above embodiment, for the sake of simplicity of explanation, the information processing apparatus is used as a host and the connection between the hosts is described. However, the information processing apparatus includes a printer and a printer server, a printer and a printer, or a chip in the printer. A chip (for example, a printer controller and an engine controller) may be used. (Here, the printer controller executes control such as scheduling for a job that enters the printer, and the engine controller draws an image included in the job.) When each information processing apparatus generates a synchronization signal, the present invention is By applying it, it is possible to suppress communication failures due to differences in synchronization signals.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (15)

An information processing device that receives the first synchronization signal from an external device that generates a first synchronization signal subjected to spread spectrum processing, and communicates with the external device,
Generating means for generating a second synchronization signal after the spread spectrum processing at a predetermined frequency fluctuation range,
First communication means for receiving information indicating a frequency variation range of the first synchronization signal from the external device;
Control means for selecting one of the synchronization signals based on the frequency fluctuation range of the first synchronization signal and before Symbol second synchronizing signal,
The information processing apparatus characterized by a second the Communication means for communicating with said external device based on the selected synchronization signal of the control means. The control means selects the second synchronization signal when the frequency fluctuation range of the second synchronization signal is included in the frequency fluctuation range of the first synchronization signal, and the frequency fluctuation range of the first synchronization signal is the first fluctuation signal. The information processing apparatus according to claim 1, wherein the first synchronization signal is selected when included in a frequency variation range of two synchronization signals. When the frequency variation range of the first synchronization signal and the frequency variation range of the second synchronization signal are not in an inclusive relationship, the generation unit is configured such that the frequency variation range of the second synchronization signal is the frequency variation of the first synchronization signal. The frequency variation range of the second synchronization signal is changed so as to be included in the range, and the control unit selects the second synchronization signal in which the frequency variation range is changed. Information processing device. When the frequency variation range of the first synchronization signal and the frequency variation range of the second synchronization signal are not in an inclusive relationship, the generation unit performs spread spectrum processing so as to be included in the frequency variation range of the first synchronization signal. Generating a third synchronization signal, and transmitting the third synchronization signal to the external device;
The information processing apparatus according to claim 1, wherein the control unit selects the third synchronization signal. Further comprising a device that communicates with the second the Communication unit based on the second synchronization signal,
Wherein, when said first selected the synchronization signal, the second from the first communication state to communicate with the device and the second the Communication means on the basis of the synchronization signal, the first synchronization signal any from the second synchronization signal to switch to the second communication state to communicate with the second the communication unit and the device of claim 1, wherein the switching to the first synchronization signal on the basis of The information processing apparatus according to claim 1 . Further comprising a detecting means for detecting a connection to the external device, wherein the connection with the external device is detected, claims 1 to 5, characterized in that to receive the first synchronization signal from the external device The information processing apparatus according to any one of the above. Further comprising a device in communication with the second the Communication unit based on the second synchronization signal,
Wherein, when selecting the second synchronization signals, any one of claims 1 to 4, characterized in that maintaining the first communication state to communicate with the said second the Communication unit device The information processing apparatus according to item . The first communication means, wherein the information from the previous Kigaibu apparatus showing a variation range of the frequency of the first synchronization signal to any one of claims 1 to 5, characterized in that receiving in asynchronous Information processing device. The control means by comparing the first frequency fluctuation range of the generated second synchronizing signal with the frequency fluctuation range of the synchronization signal the generating means of the external device based on information indicating the frequency fluctuations range 9. The information processing apparatus according to claim 1, further comprising a determination unit that determines a synchronization signal to be selected by the control unit. The information processing apparatus according to any one of claims 1 to 9, wherein the second the Communication means and performs data communication serial form. Wherein, when the communication is disconnected between said external device and the second the Communication means, said notifies the disconnection request to the external device, and receives a permission notification to the disconnection request from the external device the apparatus according to any of claims 1 to 10, characterized by cutting the communication with the external device and the second the communication unit from.   The information processing apparatus according to claim 11, wherein the control unit disconnects the communication by stopping output of a synchronization signal by the generation unit. An information processing device that receives the first synchronization signal from an external device that generates a first synchronization signal and communicates with the external device,
Generating means for generating a second synchronization signal;
Information indicating a frequency variation range when the external device performs spread spectrum processing on the first synchronization signal is received based on the first synchronization signal or the second synchronization signal not subjected to spread spectrum processing. Communication means;
One synchronization signal to be subjected to spread spectrum processing is selected based on a frequency variation range when performing spread spectrum processing on the second synchronization signal and the frequency variation range of the first synchronization signal received by the communication means Control means for
The information processing apparatus, wherein the communication means communicates with the external device based on the synchronization signal obtained by performing spread spectrum processing on the synchronization signal selected by the control means. An information processing method by an information processing apparatus that receives the first synchronization signal from an external apparatus that generates a first synchronization signal subjected to spread spectrum processing and communicates with the external apparatus ,
A generation step of generating a second synchronization signal subjected to spread spectrum processing within a predetermined frequency variation range;
A first communication step of receiving information indicating a frequency variation range of the first synchronization signal from the external device by a first communication means;
And a control step of selecting one of the synchronization signals based on the frequency fluctuation range of the first synchronization signal and before Symbol second synchronizing signal,
By the second communication means, a second communication step of communicating with the front Kigaibu device based on the synchronization signal selected by said control step,
An information processing method characterized by comprising: An information processing method by an information processing apparatus that receives the first synchronization signal from an external apparatus that generates a first synchronization signal and communicates with the external apparatus,
A generating step of generating a second synchronization signal;
Information indicating a frequency variation range when the external device performs spread spectrum processing on the first synchronization signal is determined by communication means based on the first synchronization signal or the second synchronization signal not subjected to spread spectrum processing. A first communication step for receiving;
One synchronization signal to be subjected to spread spectrum processing is selected based on a frequency variation range when performing spread spectrum processing on the second synchronization signal and the frequency variation range of the first synchronization signal received by the communication means A control process,
  A second communication step of communicating with the external device by the communication means based on the synchronization signal subjected to spread spectrum processing on the synchronization signal selected in the control step;
An information processing method characterized by comprising:

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