CN109995681B - Device and method for realizing double-master-control main-standby switching by single chip - Google Patents
Device and method for realizing double-master-control main-standby switching by single chip Download PDFInfo
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- CN109995681B CN109995681B CN201910171099.4A CN201910171099A CN109995681B CN 109995681 B CN109995681 B CN 109995681B CN 201910171099 A CN201910171099 A CN 201910171099A CN 109995681 B CN109995681 B CN 109995681B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
- H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
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Abstract
The invention discloses a device and a method for realizing double-master-control main-standby switching by a single chip, wherein the device comprises the following steps: the main control board, reserve main control board, pcie switch and exchange chip, pcie switch and main control board or reserve main control board link to each other, and the pcie switch links to each other with exchange chip, and exchange chip passes through the switching of pcie switch and links to each other with main control board or reserve main control board, and the state of switching the backup CPU on the main control board is unanimous with the state of switching CPU on the preceding main control board. The invention can effectively reduce the cost and efficiently realize the main/standby switch at the same time.
Description
Technical Field
The present invention relates to a dual master control implementation scheme, and in particular, to a device and method for implementing dual master control active/standby switching by a single chip.
Background
The dual master control is a common redundancy backup mechanism adopted to improve the system stability, and is widely used at present. In the switch system, the dual master control has two roles of main master and standby master, and the main master and the standby master respectively and independently work, wherein the main master is responsible for communicating with all interface boards (such as various items below, receiving and sending messages, responding to various events and the like) and controlling the operation of the whole dual master control device. Under normal conditions, only the main master control works, and the synchronization between the main and the standby is completed through the upper layer protocol. When the main master control normally operates, the standby master control does not communicate with the interface board and does not interfere the operation of the whole double master control equipment, and only receives the backup data backed up by the main master control. When the main device fails, the standby device is switched to immediately, and the standby main control receives the backup data of the main control, so that all work of the original main control can be seamlessly taken over, and the main-standby switching is completed.
However, in the prior art, when implementing dual master control, it is necessary to configure independent CPUs and switch chips on the main device and the standby device, that is, at least 2 CPUs and 2 switch chips are needed, and in the network switch device, the switch chip is a core component, which is relatively high in cost, so that it is necessary to reduce the production cost as much as possible on the basis of implementing dual master control.
Disclosure of Invention
The present invention aims to overcome the defects of the prior art, and provides a device and a method for realizing the switching between a dual master control main standby by a single chip.
In order to achieve the purpose, the invention provides the following technical scheme: a device for realizing double-master-control main-standby switching by a single chip comprises: the main control board, reserve main control board, pcie switch and exchange chip, the pcie switch links to each other with main control board or reserve main control board, the pcie switch links to each other with exchange chip, exchange chip passes through the switching of pcie switch and links to each other with main control board or reserve main control board.
Preferably, the main control board and the standby main control board both include a CPU, and after switching, the state of the CPU on the standby main control board is consistent with the state of the CPU on the main control board before switching.
Preferably, the pcie switch is connected with the main control board or the standby main control board through a pcie link.
Preferably, the CPU of the standby main control board is connected to the receiving end of the main control board through a socket interface, and reads the configuration on the switch chip connected to the main control board.
The invention also discloses another technical scheme: a method for realizing double-master-control main-standby switching by a single chip comprises the following steps:
s1, the state of the CPU on the main control board for switching the backup is consistent with the state of the CPU on the main control board before switching;
and S2, when the main control board has a problem, the switching chip is connected with the standby main control board through the switching of the pcie switch, and the main-standby switching is completed.
Preferably, the S1 includes:
s11, the main control board sends the configuration to the exchange chip and synchronizes the configuration to the standby main control board;
s12, the standby main control board receives the configuration and issues the configuration;
s13, the standby main control board sends an access instruction to the main control board to request to read the chip value of the exchange chip;
and S14, the main control board receives the access instruction, reads out the chip value of the exchange chip and returns the chip value to the standby main control board, and the state of the CPU on the main control board for switching the backup is consistent with the state of the CPU on the main control board before switching.
Preferably, the configuration issued by the main control board and the standby main control board sequentially passes through a protocol layer, an adaptation layer and SDK software to an IO Shim layer, and the main control board finally issues the configuration to the switching chip through a pcie link.
Preferably, in S13, the standby main control board transmits the access command to the main control board through the socket.
Preferably, in S14, after receiving the access instruction, the main control board reads the chip value from the switch chip through the pcie link.
Preferably, in S2, after the problem occurs in the main control board, the pcie switch connects the pcie link switch with the standby main control board.
The invention has the beneficial effects that:
1. the invention controls the connectivity of the main control board and the standby main control board through the pcie switch, realizes that the main/standby switching of the double main control boards can be realized only by one switching chip, namely two CPUs on the double main control boards share one chip, switches between the main/standby through the pcie link, can effectively reduce the cost, and simultaneously realizes the main/standby switching efficiently.
2. In terms of software implementation, before the main control board fails, the standby main control board transmits an access instruction of read operation to the main control board through a socket, the main control board reads data of the exchange chip and returns the data to the standby main control board, the condition that the state of a CPU on the main control board for switching the standby main control board is consistent with the state of the CPU on the main control board before switching is guaranteed, and therefore complete synchronization of configuration of the main control board and the standby main control board is achieved.
Drawings
FIG. 1 is a schematic diagram of the apparatus of the present invention;
FIG. 2 is a schematic diagram illustrating the principle of primary/standby synchronization according to the present invention;
fig. 3 and 4 are schematic flow diagrams of primary and standby synchronization according to an embodiment of the present invention.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
The device and the method for realizing the main/standby switching of the double main controls by the single chip utilize one switching chip to realize the main/standby switching of the double main controls, and reduce the cost for realizing the double main controls.
As shown in fig. 1, the apparatus for implementing dual master/standby switching by a single chip according to the embodiment of the present invention includes a master control board, a standby master control board, a pcie (high speed serial computer extended bus standard) switch, and a switch chip, where the switch chip is connected to the master control board or the standby master control board through pcie switch.
Specifically, the main control board and the standby main control board are both connected with the pcie switch through a pcie link (lane). When the main control board works normally, the pcie link between the main control board and the pcie switch is connected, and the pcie link between the standby main control board and the pcie switch is disconnected, namely, only one pcie link is connected at the same time. The pcie switch is connected with the switching chip, namely the invention is connected with the main control board or the standby main control board through switching of the pcie switch, namely the connectivity of the pcie lane is controlled by the pcie switch. When the main control board works, the pcie link between the standby main control board and the exchange chip is disconnected. When the master control board goes wrong, the pcie switch is switched to a pcie link of one path of the standby master control board.
The switching chip itself does not change in the switching process, so that it can be ensured that packet forwarding and packet loss do not occur in the switching process, and only the state of the CPU on the switching backup main control board is required to be consistent with the state of the CPU on the main control board before switching.
How to ensure that the state of the CPU on the switching backup main control board is consistent with the state of the CPU on the main control board before switching is shown in fig. 2 to 4. All the configurations issued by the CPUs of the main control board need to be synchronized to the CPU of the standby control board, and the CPU of the standby control board also issues the same configurations. The difference is that the configuration issued by the CPU of the main control board is issued to the switch chip all the way, and the CPU of the standby control board cannot normally access the resource of the switch chip because the pcie link between the CPU of the standby control board and the switch chip is disconnected, and needs to be implemented through an IO Shim (input output Shim) layer at this time, and the read operation of the CPU of the standby control board to the switch chip is transmitted to the receiving end on the main control board through a socket (socket), and the main control board completes the read access to the chip and returns the result to the standby main control board, and the write operation of the standby main control board does not need to be processed, and the return is successful. The specific flow is shown in fig. 2 to 4:
and A1, the master control board issues configuration to the switching chip.
Specifically, in this embodiment, the CPU of the main control board issues the configuration a, and normally issues the configuration a, and the configuration a is sequentially issued through the protocol layer, the adaptation layer, and the SDK (Software Development Kit) Software to the IO Shim layer, where the IO Shim layer is connected to the switch chip through a pci link, and when the main control board normally works, the pci link between the main control board and the switch chip is connected (active), so that the CPU of the main control board finally successfully configures the configuration a to the switch chip through the pci link.
A2, master control board and synchronizes configuration to the standby master control board.
The present invention does not need to describe details about how to synchronize configuration to the standby main control board, and can be implemented by referring to the existing principle of implementing synchronization between the main control board and the standby main control board of dual main control.
And A3, the standby main control board receives the configuration and issues the configuration.
Similar to the configuration principle issued by the main control board, the standby main control board issues the received configuration a to the IO Shim layer sequentially through the protocol layer, the adaptation layer and the SDK software, and although the IO Shim layer is also connected with the switch chip through the pci link, when the main control board normally works, the pci link between the standby main control board and the switch chip is disconnected (i.e., inactive), so that the configuration a on the standby main control board cannot be issued continuously after being issued to the IO Shim layer, and a read operation is required to obtain a chip value on the switch chip, which is specifically shown in the following step a 4.
And A4, the standby main control board sends an access instruction to the main control board to request to read the chip value of the exchange chip.
Specifically, the standby main control board needs to read a chip value on the switch chip, and the standby main control board is implemented through a socket, and the IO Shim layer of the standby main control board is connected with the IO Shim layer of the main control board through the socket. Firstly, the standby main control board transmits an access instruction to an IO Shim layer of the main control board through a socket, and then transmits the access instruction to a CPU of the main control board through SDK software, an adaptation layer and a protocol layer in sequence. The access instruction is a request instruction for reading a chip value of the switch chip.
And A5, the main control board receives the access instruction, reads out the chip value of the exchange chip and returns the chip value to the standby main control board.
Specifically, after receiving the access instruction, the CPU of the main control board reads the chip value on the exchange chip through the pcie link working between the CPU of the main control board and the exchange chip, and returns the chip value to the CPU of the standby main control board. After the configuration is returned to the CPU of the standby main control board, the configuration is written into the CPU of the standby main control board, but since the correct chip value is processed on the main control board at this time, the standby main control board does not need to write, and the main control board directly returns the read chip value to the standby main control board. Thereby realizing the consistency of the state of the CPU on the main control board for switching the backup and the state of the CPU on the main control board before switching
A6, when the main control board has a problem, the switching chip is switched by the pcie switch to connect with the standby main control board, and the main-standby switching is completed.
How to switch, namely, as introduced above, the pcie switch switches the pcie link to the standby main control board, so that the standby main control board is communicated with the switching chip through the pcie switch.
In the network switching equipment, the switching chip is a core component, and the cost is high. The two CPUs on the dual-master control card share one switching chip to realize the switching between the master control card and the slave control card, namely, the master control card and the slave control card can realize the master-slave switching of the dual-master control card only by one switching chip, thereby effectively reducing the cost.
The switching chip in the present invention is not limited to an ASIC (Application Specific Integrated Circuit) chip, and may include an FPGA (Field-Programmable Gate Array) or an NP (network processor).
Therefore, the scope of the present invention should not be limited to the disclosure of the embodiments, but includes various alternatives and modifications without departing from the scope of the present invention, which is defined by the claims of the present patent application.
Claims (8)
1. A method for realizing double-master-control main-standby switching by a single chip is characterized in that the method is realized based on a device for realizing double-master-control main-standby switching by the single chip, and the device comprises the following steps: the system comprises a main control board, a standby main control board, a pcie switch and a switching chip, wherein the pcie switch is connected with the main control board or the standby main control board, the pcie switch is connected with the switching chip, and the switching chip is connected with the main control board or the standby main control board through switching of the pcie switch; the method comprises the following steps:
s1, the state of the CPU on the main control board for switching the backup is consistent with the state of the CPU on the main control board before switching; the S1 includes:
s11, the main control board sends the configuration to the exchange chip and synchronizes the configuration to the standby main control board;
s12, the standby main control board receives the configuration and issues the configuration;
s13, the standby main control board sends an access instruction to the main control board to request to read the chip value of the exchange chip;
s14, the main control board receives the access instruction, reads out the chip value of the exchange chip and returns the chip value to the standby main control board, and the state of the CPU on the main control board for switching the backup is consistent with the state of the CPU on the main control board before switching;
and S2, when the main control board has a problem, the switching chip is connected with the standby main control board through the switching of the pcie switch, and the main-standby switching is completed.
2. The method according to claim 1, wherein the main control board and the standby main control board each include a CPU, and a state of the CPU on the standby main control board after switching is consistent with a state of the CPU on the main control board before switching.
3. The method for realizing dual-master-slave switching by the single chip according to claim 1, wherein the pcie switch is connected to the master control board or the backup master control board through a pcie link.
4. The method for a single chip to implement dual master control active/standby switch according to claim 2, wherein a CPU of the standby master control board is connected to a receiving end of the master control board through a socket interface, and reads a configuration on a switch chip connected to the master control board.
5. The method for realizing the switching between the main and the standby dual-master control through the single chip according to claim 1, wherein the configurations issued by the main control board and the standby main control board sequentially pass through a protocol layer, an adaptation layer and SDK software to an IO Shim layer, and the main control board finally issues the configurations to the switch chip through a pcie link.
6. The method for realizing dual-master-slave switching by the single chip according to claim 1, wherein in S13, the standby master board transmits the access command to the master board through a socket.
7. The method according to claim 1, wherein in S14, after receiving the access instruction, the main control board reads the chip value from the switch chip through a pcie link.
8. The method of claim 1, wherein in S2, after the main control board has a problem, the pcie switch connects pcie link switching to the standby main control board.
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| CN110543390B (en) * | 2019-09-19 | 2024-07-09 | 深圳市友华通信技术有限公司 | Quick response method, device and communication equipment for interrupt reconnection |
| CN112235192B (en) * | 2020-10-10 | 2022-07-08 | 苏州盛科通信股份有限公司 | Linkagg port switching method for stacking equipment and Linkagg-based stacking equipment |
| CN113407480A (en) * | 2021-06-25 | 2021-09-17 | 新华三信息安全技术有限公司 | Centralized management's frame switch |
| CN116582471B (en) * | 2023-07-14 | 2023-09-19 | 珠海星云智联科技有限公司 | PCIE equipment, PCIE data capturing system and server |
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