JP2001244812A - Method and device for clock switching - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for clock switching, which can switch the clock without any data error. SOLUTION: This device for clock switching from a 1st clock to a 2nd clock includes a 1st switching means which performs switching from the 1st clock to the output clock from an oscillator having its phase synchronized with the 1st clock, a detecting means which detects the phase difference between the output clock from the oscillator and the 2nd clock decreasing below a specific value, and a 2nd switching means which performs switching from the output clock from the oscillator to the 2nd clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock switching method and a clock switching device, and more particularly, to a clock switching method and a clock switching device for improving the clock stability of a transmission device at the time of switching.

[0002] Current data transmission devices (hereinafter abbreviated as transmission devices) operate on the basis of an external clock (for example, a clock generated by a rubidium oscillator such as DCS). However, when the transmission system is duplicated, the data transmission is duplicated. The phase of the external clock may be different. In this state, a transmission device that can supply a stable clock even when the clock is switched and does not cause a data error is required.

For this reason, phase absorption is performed by a PLL or the like, and the phase is varied at a speed determined by an internal time constant of the PLL. There are times when we can't handle it. Therefore, even when there is a phase difference between the external clocks, it is necessary to perform clock switching without a data error.

[0004]

2. Description of the Related Art FIG. 15 is a block diagram showing a configuration example of a conventional circuit. In the figure, reference numeral 5 denotes a CREC (clock receiver) switching unit which receives a 0-system clock signal and a 1-system clock signal and switches a reception clock by a switching signal;
Is a TANK (tank) circuit which receives the output of the CREC switching unit 5 and temporarily reproduces the clock when the clock is cut off. Reference numeral 7 denotes a PLL (phase lock loop) circuit that receives an output of the tank circuit 6. Reference numeral 8 denotes a switching control unit that receives a disconnection detection signal or a setting (forced switching) signal and supplies a switching signal to the CREC switching unit 5.

In the circuit configured as described above, CR
The EC switching unit 5 uses the switching signal to set the reception clock to 0.
Either the system or the system 1 is used as the working system. The CR
The output of the EC switching unit 5 is provided to the PLL circuit 7 via the tank circuit 6. During operation of such a circuit, when a clock loss in the active system is detected or a forced switching signal is given, the switching control unit 8
A switching signal is given to the C switching unit 5 to switch the standby system to the working system.

In such a conventional circuit,
If switching between the 0 system and the 1 system is performed when the clock phases are significantly different, the clock phase may fluctuate rapidly before and after the switching. However, the phase fluctuation of the clock generated at the time of such switching is usually absorbed by the PLL circuit.

[0007] This will be described with reference to FIG. FIG. 16 shows the phase fluctuation amount (pp) of the output signal of the PLL circuit.
m) on the vertical axis and time (t) on the horizontal axis.

The clock signal from the TANK circuit 6 for clock disconnection correction is input to the PLL circuit 7, but the phase may fluctuate rapidly due to the switching as described above. However, the amount of phase variation of the output signal of the PLL circuit 7 increases at the switching timing. However, the feedback control in the PLL circuit 7 reduces the amount of variation over time and stabilizes the phase variation of the output signal. Become.

[0009]

In the above-described conventional circuit, a rapid phase fluctuation of the clock generated at the time of switching by the following operation of the PLL circuit 7 can be suppressed.
Generally, the allowable phase fluctuation amount of the output signal of the circuit is different. Therefore, if a PLL circuit having a predetermined time constant is used uniformly regardless of the system, there is a problem that the phase fluctuation amount of the output signal of the PLL circuit cannot be suppressed within the phase fluctuation amount required in the system. .

[0010] Here, by setting the time constant to a large value, the range of the phase fluctuation of the input clock can be expanded. Will have an adverse effect.

It is an object of the present invention to minimize the time constant of a PLL circuit by minimizing the amount of phase fluctuation of a clock input to the PLL circuit even when clock switching is performed.

Further, while keeping the time constant of the PLL circuit constant (realizing common use of the PLL circuit) irrespective of the system, the amount of phase fluctuation of the input clock is changed according to the system, and the PLL required by the system is changed. An object of the present invention is to satisfy an allowable phase fluctuation amount of an output signal of a circuit.

[0013]

According to a first aspect of the present invention, there is provided a method for switching a clock from a first clock to a second clock, wherein the phase is synchronized from the first clock to the first clock. Switching the clock to the output clock from the oscillator, and when the phase difference between the output clock from the oscillator and the second clock becomes equal to or smaller than a predetermined value, the second clock is output from the oscillator to the second clock. Switching a clock to a clock.

With this configuration, even when clock switching is performed, the time constant of the PLL circuit can be suppressed to a small value by minimizing the amount of phase fluctuation of the clock input to the PLL circuit. It is also possible to change the phase fluctuation of the input clock according to the system while keeping the time constant of the PLL circuit constant irrespective of the system, thereby satisfying the allowable phase fluctuation of the output signal of the PLL circuit required in the system. it can.

(2) FIG. 1 is a block diagram showing the principle of the present invention. The same components as those in FIG. 15 are denoted by the same reference numerals.
In the figure, reference numeral 10 denotes a reception clock switching unit for switching between the 0-system clock and the 1-system clock, and 20 detects the phases of the 0-system clock and the 1-system clock, and according to the detected phase difference, the frequency deviation of the internal oscillator 15. The clock generation unit 12 that naturally changes the clock phase by utilizing the output of the reception clock switching unit 10 (external clock) and the output of the clock generation unit 20 (oscillator frequency-divided clock). An oscillation clock switching unit to be selected.

The transmission clock switching unit 12 switches the clock from the first clock to the output clock from the oscillator 15 synchronized in phase with the first clock. The clock generator 20 detects that the phase difference between the output clock from the oscillator 15 and the second clock has become equal to or smaller than a predetermined value. The oscillation clock switching unit 12 detects
The clock is switched from the output clock from the oscillator 15 to the second clock.

With this configuration, even when clock switching is performed, the time constant of the PLL circuit can be suppressed to a small value by minimizing the amount of phase fluctuation of the clock input to the PLL circuit. It is also possible to change the phase fluctuation of the input clock according to the system while keeping the time constant of the PLL circuit constant irrespective of the system, thereby satisfying the allowable phase fluctuation of the output signal of the PLL circuit required in the system. it can.

(3) A transmission apparatus according to claim 3, wherein two or more external clocks are input and the transmission apparatus has a function of switching clocks between the external clocks.
First switching means for performing clock switching to an output clock from an oscillator whose phase is synchronized with one external clock used before switching, and a phase difference between an output clock from the oscillator and another external clock being equal to or less than a predetermined value. Detecting means for detecting the occurrence of the external clock, and second switching means for performing clock switching from the output clock from the oscillator to the other external clock by the detection.
Click switching from the one clock to the other clock is realized.

With this configuration, the clock can be switched from one clock to another clock without a data error.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. 1 and 15 are denoted by the same reference numerals. In the figure, reference numeral 5 denotes a CREC switching unit that receives a 0-system clock and a 1-system clock and switches to any system by a switching signal A, and 6 receives the output of the CREC switching unit 5 and switches the clock when the clock is cut off. This is a tank circuit for temporarily regenerating. The CREC switching unit 5 and the tank circuit 6 combine the reception clock switching unit 1 of FIG.
0.

An oscillation clock switching unit 12 receives an external clock output from the reception clock switching unit 10 and an oscillator frequency-divided clock (internal clock) generated in the apparatus, and selects one of them according to a switching signal B. Department.
The oscillation clock switching unit 12 outputs a PLL input reference signal. Reference numeral 7 denotes a PLL circuit that receives the output of the oscillation clock switching unit 12.

Reference numeral 21 denotes a phase comparison unit for comparing the phases of the 0-system clock and the 1-system clock. 22 is a comparison unit which receives the output of the phase comparison unit 21 and compares whether the phase difference is larger than a set phase difference. , 23 are oscillation clock generators which receive an external clock and the output of the internal oscillator 15 and generate an oscillator divided clock. A phase difference is set in the comparator 22 by a setting signal, and a fluctuation rate is set in the oscillation clock generation unit 23 by an external setting signal, and an oscillator divided clock is generated based on the fluctuation rate.

Reference numeral 24 denotes a disconnection detecting circuit which receives a 0-system clock and a 1-system clock to detect a clock disconnection, and 25 designates an output of the disconnection detecting circuit 24, an output of the comparator 22, a setting signal (forcible switching signal), In response to this, it is a switching control unit that controls clock switching and generates switching signals A and B. The phase comparison unit 21, the comparator 22, the oscillation clock generation unit 23, the disconnection detection circuit 24, and the switching control unit 25 constitute the clock generation unit 20 in FIG. The operation of the device configured as described above will be described below.

In the case of automatic switching that occurs when the disconnection of the 0-system clock and the 1-system clock is detected, and when forcible switching is performed by setting a command or the like, the phase difference (0-system clock, 1-system clock) If the phase difference is larger than the set value, the clock generated from the internal oscillator 15 is used), the fluctuation rate (the fluctuation rate of the clock generated from the internal oscillator 15 (the internal oscillation clock fluctuates by 1 bit during the set period)) ) Is set.

The fluctuation rate can be set from 0. When the fluctuation rate is set to 0, the edge naturally moves due to the frequency deviation by utilizing the characteristic that the external clock and the oscillation clock of the internal oscillator 15 are asynchronous.

When the clock is actually switched from the 0-system to the 1-system, the oscillation clock generation unit 23 generates an internal oscillator divided clock that matches the edge with the normal selection clock. FIG. 3 is a diagram showing operation waveforms in a normal state.
(A) is a 0 system clock, (b) is a 1 system clock, (c)
Is an external clock, and (d) is an oscillator divided clock.
As is clear from this figure, in the normal state, CR
The EC switching unit 5 selects, for example, the 0 system, and the oscillation clock switching unit 12 selects an external clock. The external clock and the internal oscillator divided clock have the same phase.

In this way, the clock can be switched from the external clock to the oscillator frequency-divided clock side without any problem by holding the in-phase clock having the same frequency as the external clock in the transmission device.

Here, consider a case where an instruction to switch from the 0 system to the 1 system occurs (for example, clock cut or forced switching). For example, when the phase difference between the 0-system clock and the 1-system clock is larger than the phase difference set by the setting signal (for example, when the phase difference exceeds a predetermined value), the output of the phase comparator 21 is given to the comparator 22, Indicates the comparison result to the switching control unit 25.
Give to. As a result, the switching control unit 25 supplies the switching signal B to the oscillation clock switching unit 12. The oscillation clock switching unit 12 switches the clock from an external clock up to that time to an oscillator divided clock (internal clock) whose phase has been adjusted to the 0-system clock.

According to this, the clock can be switched without causing a phase difference between the clock before switching and the clock after switching.

At this time, the external clock shifts to the 1-system clock by switching from the 0-system clock to the 1-system clock by the CREC switching unit 5. In this case, it is possible to move the edge slowly by using the internal oscillator 15 having a small frequency deviation.

When the oscillator divided clock is selected by the oscillation clock switching unit 12, the external clock and the oscillator divided clock are set by free-running the oscillator divided circuit (not shown) in the oscillation clock generating unit 23. Becomes asynchronous. FIG. 4 is a diagram showing operation waveforms during a free run.
(A) is a system 0 clock, (b) is a system 1 clock, (c)
Is an external clock, and (d) is an oscillator divided clock.
As is clear from the figure, the oscillator divided clock is in a free-run state with respect to the external clock. Since the frequency is divided by free-run, the external clock and the oscillator divided clock are asynchronous.

When the rate of change of the setting signal is 0, the edge naturally fluctuates due to the deviation of the internal oscillator 15. FIG. 6 is an explanatory diagram of the clock fluctuation in the device at this time. Δ in the figure is the oscillator deviation. During this period, the oscillator divided clock is in a free-run state.

When the setting signal is set so that the output of the internal oscillator 15 fluctuates by one bit during a certain period (for example, once every 100 periods of the oscillator divided clock), the clock fluctuates at the speed of deviation + fluctuation rate. . FIG. 7 is a diagram showing clock fluctuations at this time. During the free run state, there is an increase in the variation due to the variation rate.

When the edges of the external clock and the oscillator divided clock match during the clock fluctuation, or when the edges fall within a predetermined interval, the oscillation clock switching unit 12
Switch to external clock. FIG. 5 is a diagram showing operation waveforms at the time of phase matching. (A) is 0 system clock, (b) is 1
A system clock, (c) is an external clock, and (d) is an oscillator divided clock. After the phase of the external clock (here, the system 1 clock) matches the phase of the oscillator divided clock, the CRE
The C switching unit 5 keeps the 1 system selected while the oscillation clock switching unit 1
2 selects an external clock. That is, the output of the oscillation clock switching unit 12 switches back to the external clock. In the present invention,
After the phase match, the phase is always adjusted to the external clock.
According to this, the clock is switched back when the phase of the external clock coincides with the phase of the oscillator divided clock.
The clock can be switched back without generating a phase difference.

As described above, according to the embodiment of the present invention, when the clock input to the transmission device is switched, the clock phase is naturally changed using the frequency deviation of the internal oscillator 15. Even if the external clock has a phase difference, the clock generated by the clock generator 20 is changed by the internal oscillator 15 at an arbitrary speed.
By inputting the signal to the circuit 7, the internal clock of the transmission device can be changed at an arbitrary speed, and the clock can be switched without a data error.

Further, according to the present invention, since the variation rate is arbitrarily set externally and given to the oscillation clock generation unit 23, the optimal clock instantaneous interruption switching can be performed.

As described above, according to the present invention,
When switching an external clock having a large phase difference, a clock obtained by dividing the output of the internal oscillator 15 is used to arbitrarily change the rate of change of the reference of the PLL circuit 7.
It is possible to supply a stable clock at an arbitrary fluctuation speed regardless of the fluctuation speed due to the internal time constant of the PLL circuit as in the related art.

The switching to the internal oscillator 15 may be performed by the phase comparator 21 even if the phase comparison results of the 0 system and 1 system are not large (irrespective of the comparison result).

FIG. 8 is a flowchart showing the clock switching operation according to the present invention. In the figure, waveforms 1 to 3
Respectively correspond to the operation waveforms of FIGS. First, it is assumed that the system is in the 0 system selection state of the duplicated clock (S1). At this time, the 0-system clock, the 1-system clock, the external clock, and the oscillator-divided clock have timings as shown in FIG.

Next, it is determined whether or not the phase difference between the system 0 and the system 1 is larger than an arbitrarily set value (S2). If the phase difference is smaller than an arbitrarily set value, switching is performed without using the internal oscillator 15 (S3). As a result, the external clock is switched from the 0-system to the 1-system clock (S4), and the 1-system clock is selected (S5). As a result, the clock is switched from system 0 to system 1 with a sufficiently small phase difference.

On the other hand, if the phase difference between the system 0 and the system 1 is larger than an arbitrarily set value, switching from the system 0 to the system 1 as it is may cause a data error. In this case, the following switching operation is performed.
That is, in this case, switching is performed using the internal oscillator 15 (S6). Next, the clock fluctuation rate (fluctuation speed) generated by the internal oscillator 15 is set by the external setting signal (S7).

The CREC switching unit 5 switches the received clock to the first system clock (S4). Next, the oscillating clock switching unit 12 selects a clock generated by the internal oscillator whose phase has been adjusted to the 0-system clock (S8). That is,
Since the 0-system clock, which is an external clock, has been used as the output clock (PLL input reference clock) up to that time, switching to the oscillator-divided clock (internal clock) having the same phase as the 0-system clock provides a phase difference. You can switch without it.

FIG. 4 is a diagram showing operation waveforms at this time.
The oscillation clock switching unit 12 selects an oscillator divided clock. As a result, the oscillator divided clock is in a free-run state with respect to the external clock.

In the free-run state, the phase of the oscillator divided clock approaches that of the first system clock. An external clock (in this case, 1)
System clock) and the phase of the oscillator frequency-divided clock. When the phases match, the switching control unit 25 outputs a switching signal B, and the oscillation clock switching unit 12 outputs the switching signal B to the external clock. The process returns (S9). FIG.
Is a diagram showing an operation waveform at the time of phase matching at this time. The clock switches back to the external clock when the oscillator divided clock and the external clock match. As a result, clock switching is performed in a state where there is no phase difference with the oscillator divided clock used so far, and instantaneous interruption switching can be performed.

Next, specific embodiments of the present invention will be described. 9 is a block diagram showing a specific configuration example of the present invention, FIG. 10 is a block diagram showing a specific configuration example of the switching control unit, FIG. 11 is a time chart showing the operation of the phase comparison unit, and FIG. A time chart showing the operation of
FIG. 13 is a time chart showing the operation of the phase coincidence determination unit;
FIG. 14 is a time chart showing the operation of the oscillation clock generator. The same components as those in FIG. 2 are denoted by the same reference numerals.

In the embodiment shown in FIG. 9, the reception clock 64K0 system clock (64KHz system clock).
And 64K1 system clock (64KHz 1 system clock)
Switching unit 5 for switching the clock, a disconnection detection circuit 24 for detecting a disconnection of the clock, a phase comparison unit 21 for comparing the phases of the 0 system and the 1 system, and a tank circuit 6 for correcting the clock
A differentiating circuit 27 for differentiating the output of the tank circuit 6, and a switching controller 25 for generating a clock switching control signal.
Oscillating clock generating unit 23 that generates an oscillator divided clock, a phase matching determining unit 26 that determines the phase matching between the oscillator divided clock and the external clock, and selects one of the external clock and the oscillator divided clock. An oscillation clock switching unit 12 is provided.

Here, the phase comparator 21 includes an inverter G1 for inverting the phase of the 0-system clock, and an inverter G1.
A differentiating circuit 30 for differentiating the output of the inverter G2, an inverter G2 for inverting the phase of the 1-system clock, an AND gate G3 for ANDing the output of the inverter G2 and the 0-system clock,
A counter 31 receiving the output of the differentiating circuit 30 as a load (LD) signal, the output of the AND gate G3 as an enable (EN) signal, and the output of the internal oscillator 15 as a clock;
It comprises a comparator 32 which receives the output of the counter 31, the output of the differentiating circuit 30, and a set value (for example, "20") and outputs a phase difference signal. The oscillation frequency of the internal oscillator 15 is 16.384 MHz here.

The phase coincidence judging section 26 is composed of an AND gate G11 receiving the output of the differentiating circuit 27 at one of its inputs, and a flip-flop 50 receiving the output from the oscillation clock generating section 23. The output of the flip-flop 50 enters the other input of the AND gate G11.

The oscillation clock generator 23 receives an output of the differentiating circuit 27 at one input, an AND gate G5 receiving a mask signal of the switching controller 25 at the other input, and an inverted signal of the mask signal by an inverter G10. An AND gate G7 that receives a feedback signal at the other input, an OR gate G8 that receives an output of the AND gate G5 at one input, an output of the AND gate G7 at the other input, and an OR gate G8 that receives the output of the AND gate G7 at the other input. An OR gate G9 which receives an output at one input and a feedback signal at the other input, and loads the output of the OR gate G9 (L
D) Input the output of the internal oscillator 15 as a clock (ck)
An 8-bit counter 40 receiving an input, an OR gate G12 receiving an output of an AND gate G7 at one input, an output of a differentiating circuit 42 at another input, and a carry-out signal Co of the 8-bit counter 40 at one of the inputs. The AND gate G13 receiving the select signal B at the other input, the set value “156”, the output of the OR gate G12 to the load (LD) input, the output of the AND gate G13 to the enable (EN) input, 8-bit counter 41 receiving the output of oscillator 15 at the clock (ck) input
It is composed of The carry-out signal Co of the 8-bit counter 40 enters the OR gate G9 and the flip-flop 50 as a feedback signal. The carry-out signal Co of the 8-bit counter 41 enters the AND gate G7.

As the internal oscillator 15, for example, a crystal oscillator is used, and its oscillation frequency is 16.384M.
Hz, and the 8-bit counter 40 has 256
The frequency is divided into a 64K clock.

In the switching control unit shown in FIG. 10, reference numeral 60 designates a 64K (Hz) 0 system disconnection signal as a set input and 64K1
An SR flip-flop receiving a system disconnection signal at a reset input, a selector 61 receiving an output of the SR flip-flop 60 and a forced switching signal, and an output of the selector 61 is a select signal A; G20 is an AND gate that receives a 64K0 clock cutoff signal, a 64K1 clock cutoff signal, and an enable signal, the output of which is given to the selector 61 as a select signal. Reference numeral 62 denotes a differentiating circuit which receives the output of the selector 61 at one input and the oscillator clock at the other input. The differentiating circuit 62 includes a rising differentiating circuit 62a and a falling differentiating circuit 62b.

G21 is a NAND gate receiving the phase difference signal at one input and a feedback signal (output of the OR gate G23 receiving the output of the differentiating circuit 62) at the other input, and 63 is the output of the NAND gate G21 as its set input. An SR flip-flop in which a signal obtained by inverting a phase matching signal by an inverter G22 enters a reset input. The output of the flip-flop 63 is the select signal B
And the output of the flip-flop 63 is connected to the inverter G
The signal inverted at 23 is output as a mask signal.

In the time chart of FIG. 11, (a)
Is a 64K0 system clock, (b) is a 64K1 system clock,
(C) is an internal oscillator clock, and (d) is a counter LD.
(Load) signal, (e) is count EN (enable)
(F) is a counter output, (g) is a phase difference set value (here, 20), (h) is a phase difference determination signal, (i) is a phase difference latch signal, and (j) is a phase difference signal. .

In the time chart of FIG. 12, (a)
Is the 64K0 disconnection signal, (b) is the 64K1 disconnection signal,
(C) is a forced switching signal, (d) is an enable signal,
(E) is a phase difference signal, (f) is a select signal A, (g)
Is a select signal B, (h) is a mask signal, and (i) is a phase matching signal.

In the time chart of FIG. 13, (a)
Is an external clock, (b) is a phase matching differential pulse signal,
(C) is the oscillator divided clock, (d) is Co (carry-out signal) of the frequency dividing counter, (e) is the output of the flip-flop 50 of the phase coincidence determination unit 26, and (f) is the phase coincidence signal. .

In the time chart of FIG. 14, (a)
Is the output of the gate G10, (b) is the output of G7, (c) is the output of G8, (d) is the output of G9, (e) is the oscillator divided clock, (f) is the external clock, (g) Is a phase matching signal, (h) is a phase matching differential pulse, (i) is a counter 4
0 carry-out (Co) signal, (j)
1 carry out (Co) signal, (k) is counter 4
A load (LD) signal of 0, (l) is a set value of the counter 41 (here, 156), (m) is an enable (EN) signal of the counter 41, and (n) is a load (L) of the counter 41.
D) signal, (o) is a Q output of the counter 41, (p) is a select signal B, and (q) is a mask signal.

The operation of the thus configured device will be described as follows.

The selector of the CREC switching unit 5 switches the 64K 0-system clock and the 64K 1-system clock according to the select signal A from the switching control unit 25. The disconnection detection circuit 24 detects the disconnection of the 0-system clock and the 1-system clock, and sends a 64K0 system disconnection detection signal and a 64K1 system disconnection detection signal to the switching control unit 25 when the disconnection is detected.

In the phase comparing section 21, the differentiating circuit 30 differentiates the 0-system clock, and the differentiated pulse is sent to the counter 31 as a load signal (LD) ((d) in FIG. 11). Also, the AND of the system 0 clock and system 1 clock inverted by the inverter G2 is taken by G3,
A counter enable signal (EN) is generated ((e) in FIG. 11).

In the counter 31, 0 is set in the counter 31 by the load signal (LD), and the internal oscillator 15 is used as a clock while the enable signal is “High”.
The phase difference between the 4K0 system clock and the 64K1 system clock is counted ((f) in FIG. 11). In the comparator 32,
When the Q output of the counter 31 exceeds the preset phase difference set value “20” of the system 0 and system 1 clocks, the phase difference determination becomes “High” ((h) in FIG. 11). And 0
A phase difference signal is generated using the differentiated pulse obtained by inverting the system clock as a phase difference latch signal (FIG. 11 (j)).

The tank circuit 6 generates a clock corresponding to the 0-system clock or the 1-system clock during the period from when the 0-system clock or the 1-system clock is cut off to when the selector of the CREC switching unit 5 performs the switching. And correct the clock.

The differentiating circuit 27 differentiates the clock selected by the selector of the CREC switching unit 5. And
The rising differentiation becomes a phase matching differential pulse of the phase matching determination unit 26 and enters the AND gate G11. The phase coincidence differential pulse is also input to the AND gate G5 of the oscillation clock generator 23.

The switching control section 25 generates a control signal for switching the clock in the selector of the CREC switching section 5 and the selector of the oscillation clock switching section 12.
FIG. 10 is a block diagram of the switching control unit 25, and FIG. 12 is a time chart of the operation. FIG. 12 shows a time chart when the 0-system clock is cut off, the phase difference between the 0-system clock and the 1-system clock is larger than the set value, and no forcible switching is performed.

In this case, the 64K0 system disconnection detection signal is "Lo"
The clock cut is detected by "w", and since the 64K1 system is normal, the latch output of the SR flip-flop 60 becomes "High" as shown in (b). The select signal A which is this signal is selected by the selector of the CREC switching unit 5. And the first system clock is selected.

Then, the select signal A enters the differentiating circuit 62, and a differentiated pulse is generated. The differentiated pulse and a phase difference signal output from the comparator 32 are output from a NAND gate G21.
And the output of the NAND gate G21 enters the set input of the SR flip-flop 63. As a result, the Q output of the SR flip-flop 63 becomes “High”,
This is output as the select signal B shown in (g), and the inverted signal of the inverter G23 is output as the mask signal shown in (h).

The select signal B is supplied to the oscillation clock switching unit 12
The output of the oscillation clock generation unit 23 is selected when the signal is “High”, and the external clock (here, the first system clock) is selected when the signal is “Low”.

In the oscillation clock generator 23, the output of the internal oscillator 15 is frequency-divided in the 8-bit counter 40 to generate the same oscillator-divided clock of 64 kHz as the external clock (FIG. 14 (e)). When the oscillator divided clock is selected by the selector of the oscillation clock switching unit 12,
Since the mask signal is “Low”, the AND gate G5 is closed.

As a result, the external clock and the oscillator divided clock become asynchronous as shown in FIGS. 14 (e) and 14 (f), and the carry output Co of the 8-bit counter 40 and the load signal of the counter 40 remain unchanged. As a result, the 8-bit counter 40 runs free.

When the rate of change is set in the 8-bit counter 41 provided after the 8-bit counter 40, the change rate of the oscillator divided clock can be set arbitrarily.

In the 8-bit counter 41, first, a set value is loaded by differentiating the rising edge of the select signal B.
The set value is “156” as shown in FIG. 9 and 14, when the 8-bit counter 41 counts 100, the total count becomes 256, and the carry signal Co is generated as shown in (j) of FIG.

The OR condition output of this signal and the carry signal Co of the 8-bit counter 40 becomes the load signal of the 8-bit counter 40. That is, the carry signal Co of the 8-bit counter 40 and the carry signal Co of the 8-bit counter 41.
Enter the OR gate G9, and the output of the OR gate G9 enters the load input of the 8-bit counter 40. By doing so, the divided clock of the 64K oscillator becomes 100
When counting, the load period of the 8-bit counter 40 becomes longer by the load period of the 8-bit counter 41, and the 8-bit counter 40 starts counting with a delay.

As a result, the divided clock of the transmitter becomes 1.5
16,384 for 6 ms (1 / (64 kHz x 100))
The internal oscillator of MHz changes by one bit. During the fluctuation, the edges of the external clock and the oscillator-divided clock are set to (e) in FIG.
When they match as shown in (f), the oscillation clock switching unit 12 switches from the oscillator divided clock to the external clock.

At this time, the falling differential pulse of the external clock (the output of the differentiating circuit 27) is supplied to the 8-bit counter 4
It becomes a load signal of 0, and an oscillator divided clock having the same phase as the external clock is newly generated.

The phase coincidence judging section 26 (a) of FIG.
When the phase of the external clock shown in (c) coincides with the phase of the oscillator divided clock shown in (c), the output of the flip-flop 50 obtained by delaying the carry signal Co sent from the 8-bit counter 40 of the oscillation clock generator 23 by 1 bit The phase coincidence differential pulse shown in FIG.
, A phase match signal shown in (f) is generated. Then, this phase coincidence signal is sent to the switching control unit 25, the select signal B becomes "Low", and the external clock is selected.

As described above, according to the present invention,
When switching between clocks supplied to the transmission device and having different phases is performed, the clock of the transmission device can be smoothly switched by the clock fluctuation generated by the internal oscillator. For this reason, it is possible to supply a stable clock that does not cause a data error, and it is possible to contribute to improvement in performance of the data transmission device.

[0077]

As described above, according to the present invention,
The following effects can be obtained.

(1) According to the first aspect of the present invention, a step of performing clock switching from the first clock to an output clock from an oscillator whose phase is synchronized with the first clock, and an output from the oscillator. Switching the clock from the output clock from the oscillator to the second clock when the phase difference between the clock and the second clock becomes equal to or smaller than a predetermined value. The allowable phase fluctuation amount of the output signal of the PLL circuit can be satisfied.

(2) According to the second aspect of the present invention, the first switching means for switching a clock from the first clock to an output clock from an oscillator whose phase is synchronized with the first clock, Detecting means for detecting that the phase difference between the output clock from the oscillator and the second clock is equal to or less than a predetermined value, and switching the clock from the output clock from the oscillator to the second clock by the detection; And the second switching means for performing the operation, it is possible to satisfy the allowable phase fluctuation amount of the output signal of the PLL circuit required in the system.

(3) A transmission apparatus according to claim 3, wherein two or more external clocks are inputted and the transmission apparatus has a function of switching clocks between the external clocks.
First switching means for performing clock switching to an output clock from an oscillator whose phase is synchronized with one external clock used before switching, and a phase difference between an output clock from the oscillator and another external clock being equal to or less than a predetermined value. Detecting means for detecting the occurrence of the external clock, and second switching means for performing clock switching from the output clock from the oscillator to the other external clock by the detection.
Clock switching from one clock to another clock can be performed without a data error.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing operation waveforms in a normal state.

FIG. 4 is a diagram showing operation waveforms during a free run.

FIG. 5 is a diagram showing operation waveforms at the time of phase matching.

FIG. 6 is an explanatory diagram of a clock fluctuation in the device of the present invention.

FIG. 7 is an explanatory view of another variation of the internal clock of the present invention.

FIG. 8 is a flowchart showing a clock switching operation according to the present invention.

FIG. 9 is a block diagram showing a specific configuration example of the present invention.

FIG. 10 is a block diagram illustrating a specific configuration example of a switching control unit.

FIG. 11 is a time chart illustrating an operation of the phase comparison unit.

FIG. 12 is a time chart illustrating an operation of the switching control unit.

FIG. 13 is a time chart illustrating an operation of a phase match determination unit.

FIG. 14 is a time chart illustrating an operation of the oscillation clock generation unit.

FIG. 15 is a block diagram illustrating a configuration example of a conventional circuit.

FIG. 16 is an explanatory diagram of a conventional clock fluctuation in the device.

[Explanation of symbols]

 Reference Signs List 10 reception clock switching unit 12 oscillation clock switching unit 15 internal oscillator 20 clock generation unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoichi Nakao 3-22-8 Hakata-ekimae, Hakata-ku, Fukuoka-shi, Fukuoka F-term within Fujitsu Kyushu Digital Technology Co., Ltd. F-term (reference) 5J106 AA04 BB02 CC03 CC21 DD03 DD06 DD09 DD17 DD43 DD48 EE01 EE06 FF06 GG18 HH10 KK05 5K014 AA01 CA06 FA01 5K028 AA15 NN31 QQ01 5K047 AA06 AA12 GG03 GG07 GG08 GG11 KK18 MM49 MM60 MM63

Claims (3)

[Claims] 1. A method for switching a clock from a first clock to a second clock, comprising: switching a clock from the first clock to an output clock from an oscillator that is phase-synchronized with the first clock; Switching the clock from the output clock from the oscillator to the second clock when the phase difference between the output clock from the oscillator and the second clock becomes equal to or less than a predetermined value. Clock switching method 2. A clock switching device for switching from a first clock to a second clock, wherein a first clock for switching a clock from the first clock to an output clock from an oscillator whose phase is synchronized with the first clock is provided. Switching means; detecting means for detecting that the phase difference between the output clock from the oscillator and the second clock is equal to or less than a predetermined value; by the detection, the second clock is output from the output clock from the oscillator. And a second switching means for switching the clock to the clock switching device. 3. A transmission apparatus to which two or more external clocks are inputted and which has a function of switching clocks between the external clocks, wherein an oscillator whose phase is synchronized with one external clock used before the switching is used. First switching means for switching the clock to the output clock of the following; detecting means for detecting that the phase difference between the output clock from the oscillator and another external clock has become equal to or less than a predetermined value; And a second switching means for switching the clock from the output clock to the other external clock, thereby realizing click switching from the one clock to the other clock. .