JP2000049599A - Frame phase synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame phase synchronizing circuit by which a slip due to the phase fluctuation of an input frame is prevented from occurring and synchronizing data with higher quality is transmitted. SOLUTION: A phase comparator 1 compares the phase of an input clock with that of the output of a frequency divider 3 and outputs a phase difference signal to a frame phase difference control circuit 5. A VCO 2 supplies the clock signal of a frequency which is proportionate to the voltage of a VCO control signal being the output of the frame phase difference control circuit 5 respectively to a clock output terminal 13, an output frame generating counter 4 and the frequency divider 3 as an output clock. The frame phase difference control circuit 5 is operated so as to monitor whether the difference of the phase of the output frame against the phase of the input frame is within a previously stipulated range or not, to output the output of the phase comparator 1 to the VCO 2 as it is when it is within the range and to output the VCO control voltage in the direction for reducing the frame phase difference to the VCO 2 when it exceeds the range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame phase synchronization circuit, and more particularly to a VCO (Voltage Controller) for synchronizing (changing) a frame phase while synchronizing a clock phase in a digital transmission device or the like.
old oscillator (voltage controlled oscillator)
(Phase Locked Loop)
p) The present invention relates to a method for improving occurrence of frame synchronization slip in a circuit (frequency conversion circuit).

[0002]

2. Description of the Related Art Hitherto, a frame phase change circuit of this kind of a phase synchronization circuit generally uses a frame phase change circuit via a memory such as an elastic store which is a buffer memory capable of performing writing and reading independently. It is.

However, it is required to add a slip control circuit for detecting a slip which occurs when the input phase fluctuates to exceed the memory capacity and forcibly changing the relationship between writing and reading of the memory. You. Here, the slip refers to a phenomenon that, when the timings of writing and reading match or approach each other in the above-mentioned memory, data duplication or loss occurs.

In order to meet this demand, for example, a method of adding a circuit for monitoring the relationship between writing and reading of a memory and providing a circuit for forcibly shifting the relationship between writing and reading when a slip is likely to occur. Has been proposed. This method is disclosed in JP-A-5-268684.

In the method described in this publication, as shown in FIG. 5, an input frame is written in a memory 62 in accordance with a write address generated by a write counter 61 operated by an input clock. Further, in this method, an output frame is read from the memory 62 in accordance with a read address generated from a read counter 64 operated by a clock obtained by dividing the output clock by the frequency dividing counter 63.

The slip control circuit 65 compares the write address with the read address and forcibly changes the relationship between the write address and the read address when a slip is likely to occur.

In FIG. 5, 66 is a phase comparator, 6
7 is a VCO, 68 is a clock input terminal, 69 is an input frame terminal, 70 is a clock output terminal, and 71 is an output frame terminal.

[0008]

The above-described conventional phase locked loop circuit is effective when the fluctuation of the input phase is smaller than the memory capacity, but a slip occurs when the fluctuation of the input phase exceeds the memory capacity. However, there is a problem that the data of the slipped frame becomes invalid. Also,
There is also a problem that the read address compulsory control at the time of slip detection involves a rapid change in the frame phase.

When the amount of change in the input phase can be predicted, the occurrence of slip can be avoided by optimizing the memory capacity. However, in the case of a digital transmission line or the like, the amount of change in the phase generated in the transmission line is reduced. It is very difficult to predict.

Further, there is a problem that the power consumption of the counter circuit and the memory is larger than that of other circuits. Also,
A complicated circuit is required for the slip control circuit, and there is a problem that the circuit scale becomes large. A method using a microcomputer or the like for the slip control circuit is also conceivable, but the use of the microcomputer is more expensive than a logic circuit.

An object of the present invention is to provide a frame phase synchronizing circuit which can solve the above-mentioned problems, can prevent occurrence of a slip due to phase fluctuation of an input frame, and can perform higher quality synchronous data transmission. To provide.

[0012]

A frame phase synchronizing circuit according to the present invention includes a frequency divider for dividing an output clock signal to the frequency of an input clock signal, and a phase of the input clock signal and an output of the frequency divider. A phase comparator that compares the phase, a voltage-controlled oscillator that generates an output clock signal having a frequency proportional to the control voltage, an output frame generation counter that generates an output frame synchronized with the output clock signal, and an input frame. A frame phase difference control circuit that monitors a phase difference from the output frame generated by the output frame generation counter and controls the control voltage according to the monitoring result.

Another frame phase synchronization circuit according to the present invention is a frequency divider for dividing an output clock signal to a frequency of an input clock signal, and comparing a phase of the input clock signal with a phase of an output of the frequency divider. Phase comparator, a digital frequency control oscillator for generating an output clock signal having a frequency corresponding to control data, an output frame generation counter for generating an output frame synchronized with the output clock signal, an input frame and the output frame generation A frame phase difference control circuit that monitors a phase difference from the output frame generated by the counter and outputs a signal corresponding to the monitoring result; and generates the control data based on an output signal of the frame phase difference control circuit. And a digital signal processor.

That is, the frame phase synchronization circuit of the present invention comprises a phase comparator and a VCO (Voltage Cont).
In a general phase-locked loop composed of a rolled oscillator and a frequency divider, an output frame generation counter that operates on the output side clock, and a phase difference between the phase of the input frame and the phase of the output frame And a frame phase difference control circuit for switching the signal supplied to the VCO.

The frame phase difference control circuit monitors whether or not the phase difference between the phase of the input frame and the phase of the output frame is within a predetermined range (for example, ± 1 clock width of the output clock). The VCO control voltage in the direction to reduce the frame phase difference when the
Output to CO.

Therefore, even if the phase of the input frame fluctuates, the phase of the output frame can follow the phase of the input frame, and the occurrence of slip can be prevented.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a frame phase synchronization circuit according to one embodiment of the present invention.
In the figure, a frame phase synchronization circuit according to an embodiment of the present invention includes a phase comparator 1 and a VCO (Voltage Co.).
controlled oscillator (voltage controlled oscillator) 2, frequency divider 3, output frame generation counter 4
, A frame phase difference control circuit 5 and a clock input terminal 1
1, an input frame terminal 12, and a clock output terminal 13
And an output frame terminal 14.

The phase comparator 1 comprises a circuit (for example, an exclusive OR circuit) for comparing the phase of the input clock with the phase of the output of the frequency divider 3, and outputs a phase difference signal to the frame phase difference control circuit 5. I do. The VCO 2 supplies a clock signal having a frequency proportional to the voltage of the VCO control signal output from the frame phase difference control circuit 5 to the clock output terminal 13, the output frame generation counter 4, and the frequency divider 3 as an output clock.

The output frame generation counter 4 generates an output frame synchronized with the output clock and supplies the output frame to the output frame terminal 14 and the frame phase difference control circuit 5. The frequency divider 3 divides the output clock signal up to the input clock frequency and supplies it to the phase comparator 1.

The frame phase difference control circuit 5 monitors whether or not the difference between the phase of the input frame and the phase of the output frame is within a predetermined range (for example, the range from the input frame to the output clock + 1 clock width). If it is within, the output of the phase comparator 1 is output to the VCO 2 as it is,
When it exceeds the range, it operates to output the VCO control voltage in the direction of reducing the frame phase difference to VCO2.

FIG. 2 is a block diagram showing the configuration of the frame phase difference control circuit 5 of FIG. In the figure, a frame phase difference control circuit 5 includes flip-flop circuits 21 and 22,
A switching circuit 23, a phase comparator output signal terminal 24, an output frame terminal 25, an output clock terminal 26, an input frame terminal 27, fixed value input terminals 28 to 30,
And a control voltage output terminal 31.

The flip-flop circuit 21 generates a delayed output frame signal delayed by one clock from the output clock. Each is latched at the edge and supplied to the control input (SEL A, SEL B) of the switching circuit 23.

The four values representing the relationship between the phase of the input frame and the phase of the output frame are expressed by two switching control signals. The switching circuit 23 outputs “H” and “L” input to the fixed value input terminals 28 and 30 and the phase comparator 1 input to the phase comparator output signal terminal 24 in accordance with the values of the two switching control signals. And outputs the selected signal.

Note that "H" and "L" mean a VCO control voltage, "H" is a voltage value for increasing the VCO output frequency,
“L” means a voltage value that lowers the VCO output frequency.

The frame phase difference control circuit 5 shown in FIG. 2 shows a configuration example in which the difference between the phase of the output frame and the phase of the input frame is controlled to the width of the output clock + 1 clock from the input frame. By changing the configuration of the loop circuit 21, the phase range can be set arbitrarily.

FIG. 3 is a timing chart showing the operation of the frame phase difference control circuit 5 of FIG. The operation of the frame phase difference control circuit 5 will be described with reference to FIGS.

As shown in FIG. 3, the combination of High / Low between the output frame signal and the delayed output frame signal is 4
There are types, and they are divided into four sections a, b, c, and d in the figure.
On the other hand, by monitoring the section in which the rising edge of the input frame signal is located, and temporarily lowering the VCO output frequency when the phase of the output frame signal is ahead of the phase of the input frame signal, Adjust the phase. Conversely, when the phase of the output frame signal is behind the phase of the input frame signal, the phase is adjusted by temporarily increasing the VCO output frequency.

That is, the value (switching control signal) obtained by latching the output frame signal and the delayed output frame signal at the rising edge of the input frame signal means the phase relationship at that time, and the signal supplied to the VCO is accordingly determined. Switch as follows.

The rising edge of the input frame signal is in section a.
(When the switching control signal is "00"), the output frame signal is ahead of the input frame signal, and therefore, the fixed value "L" for lowering the VCO output frequency is selected.

The rising edge of the input frame signal is in section b
(When the switching control signal is “10”), since the output frame signal is in the same phase as the input frame signal, the frame phase difference control is not performed, and the output signal of the phase comparator 1 is It is supplied to VCO2 as it is.

When the rising edge of the input frame signal is in sections c and d (when the switching control signal is "11" or "0
In the case of "1"), since the output frame signal is behind the input frame signal, the fixed value "H" for increasing the VCO output frequency is selected.

FIG. 4 is a block diagram showing a configuration of a frame phase synchronization circuit according to another embodiment of the present invention. In the figure, a frame phase synchronization circuit according to another embodiment of the present invention includes a phase comparator 41, a phase difference counting counter 42, a DSP
(Digital Signal Process
r) 43, a digital frequency controlled oscillator 44, a frame phase difference control circuit 45, an output frame generation counter 46, a frequency divider 47, a clock input terminal 48, an input frame terminal 49, and a clock output terminal 50. , An output frame terminal 51.

That is, the frame phase locked loop according to another embodiment of the present invention shows a configuration in which the present invention is applied to a phase locked loop using a digital frequency controlled oscillator 44.

The phase difference signal output from the phase comparator 41 is quantized by the phase difference counter 42 and supplied to the DSP 43 as phase difference data. DSP4 in DSP43
3 executes smoothing, filter processing and the like by a program operating on 3 and outputs control data of the digital frequency control oscillator 44.

By adding the output frame generation counter 46 and the frame phase difference control circuit 45 to the phase synchronization circuit using the digital frequency control oscillator 44, the same effects and effects as those of the above configuration can be obtained. Can be. However, the output of the frame phase difference control circuit 45 is 2
And this is supplied to the DSP 43,
The control data switching processing to the digital frequency control oscillator 44 is configured to be incorporated in a program operating on the DSP 43.

FIG. 5 is a flowchart showing a control data switching process to the digital frequency control oscillator 44 by the DSP 43 of FIG. The control data switching process to the digital frequency control oscillator 44 will be described with reference to FIGS.

General Digital Frequency Controlled Oscillator 44
In a phase locked loop circuit using a filter, filter operation processing for realizing stability and jitter suppression characteristics and phase difference data
Calculation processing for scale conversion to a CO control value
Runs.

The switching circuit 23 shown in FIG.
When the processing operation is programmed and incorporated, the processing operation shown in FIG. 5 is performed. In this case, DSP4
3 operates based on the timing chart shown in FIG.

That is, the DSP 43 takes in the phase difference data from the phase difference data counter 42 (step S1 in FIG. 5), and takes in the frame phase difference data from the frame phase difference control circuit 45 (step S2 in FIG. 5). The phase difference data is subjected to digital filter operation processing (step S3 in FIG. 5).

The DSP 43 monitors whether or not the difference between the phase of the input frame and the phase of the output frame is within a predetermined range in the above calculation result (step S4 in FIG. 5). ("00"), a fixed value "L" for lowering the VCO output frequency is output (step S5 in FIG. 5).

When the rising edge of the input frame signal is in the section b (in the case of "10"), the DSP 43 does not perform the frame phase difference control, and outputs a filter output × α (step S6 in FIG. 5). Here, α is a loop gain.

Further, when the rising edge of the input frame signal is in the sections c and d (in the case of "11" or "01"), the DSP 43 outputs a fixed value "H" for increasing the VCO output frequency (step in FIG. 5). S7).

As described above, it is monitored whether or not the phase difference between the phase of the input frame and the phase of the output frame is within a predetermined range (for example, ± 1 clock width of the output side clock). When the phase of the input frame fluctuates, the phase of the output frame can be made to follow the phase of the input frame by outputting the VCO control voltage in the direction of reducing the frame phase difference to the VCO 2 at the time of occurrence. Can be prevented, so that higher quality synchronous data transmission can be performed.

[0044]

As described above, according to the present invention, it is monitored whether or not the phase difference between the phase of the input frame and the phase of the output frame is within a predetermined range. By outputting the control voltage in the direction of reducing the phase difference to the voltage-controlled oscillator, it is possible to prevent the occurrence of slip due to the phase fluctuation of the input frame, and it is possible to perform higher quality synchronous data transmission. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frame phase synchronization circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a frame phase difference control circuit of FIG. 1;

FIG. 3 is a timing chart showing an operation of the frame phase difference control circuit of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a frame phase synchronization circuit according to another embodiment of the present invention.

FIG. 5 is a flowchart showing a control data switching process to the digital frequency control oscillator by the DSP of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration of a frame phase synchronization circuit according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 phase comparator 2 VCO 3 frequency divider 4 output frame generation counter 5 frame phase difference control circuit 11 clock input terminal 12 input frame terminal 13 clock output terminal 14 output frame terminal 21, 22 flip-flop circuit 23 switching circuit 24 phase comparator Output signal terminal 25 Output frame terminal 26 Output clock terminal 27 Input frame terminal 28-30 Fixed value input terminal 31 VCO control voltage output terminal 41 Phase comparator 42 Phase difference count counter 43 DSP 44 Digital frequency control oscillator 45 Frame phase difference control circuit 46 output frame generation counter 47 frequency divider 48 clock input terminal 49 input frame terminal 50 clock output terminal 51 output frame terminal

Claims (8)

[Claims] A frequency divider for dividing an output clock signal to a frequency of an input clock signal; a phase comparator for comparing a phase of the input clock signal with a phase of an output of the frequency divider; A voltage-controlled oscillator that generates an output clock signal having a proportional frequency, an output frame generation counter that generates an output frame synchronized with the output clock signal, and an input frame and the output frame generated by the output frame generation counter. A frame phase difference control circuit for monitoring a phase difference and controlling the control voltage according to the monitoring result. 2. The frame phase difference control circuit is configured to output a control voltage for decreasing the phase difference to the voltage controlled oscillator when the phase difference exceeds a predetermined range. 2. The frame phase synchronization circuit according to claim 1, wherein 3. The frame phase difference control circuit according to claim 1, wherein the output of the phase comparator is directly output to the voltage controlled oscillator if the phase difference is within the predetermined range. Or a frame phase synchronization circuit according to claim 2. 4. The frame phase difference control circuit is configured to synchronize the phase of the input frame with the phase of the output frame by controlling the control voltage according to the monitoring result of the phase difference. Claim 1 characterized by the following:
The frame phase synchronization circuit according to any one of claims 1 to 3. 5. A frequency divider for dividing an output clock signal to a frequency of an input clock signal, a phase comparator for comparing a phase of the input clock signal with a phase of an output of the frequency divider, A digital frequency control oscillator that generates an output clock signal having a frequency corresponding to the output clock signal, an output frame generation counter that generates an output frame synchronized with the output clock signal, an input frame, and the output frame generated by the output frame generation counter. And a digital signal processor that generates the control data based on an output signal of the frame phase difference control circuit. Characteristic frame phase synchronization circuit. 6. The frame phase difference control circuit is configured to output a signal for generating control data in a direction to reduce the phase difference when the phase difference exceeds a predetermined range. The frame phase synchronization circuit according to claim 5, wherein: 7. The frame phase difference control circuit is configured to output a signal for generating the control data based on an output of the phase comparator if the phase difference is within the predetermined range. 7. The frame phase synchronization circuit according to claim 5, wherein: 8. The frame phase difference control circuit controls the control data generated by the digital signal processor in accordance with the monitoring result of the phase difference, thereby controlling the phase of the input frame and the phase of the output frame. 8. The frame phase synchronization circuit according to claim 5, wherein the frame phase synchronization circuit is configured to synchronize the frame phase.