JP2000029564A - High-speed phase synchronizing circuit and phase synchronizing method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase synchronizing circuit and a synchronizing method capable of compensating the delay time and reducing the power consumption. SOLUTION: The phases of an RCLK signal inputted from the outside and a fed back FCLK signal are measured by an enable signal, a measuring start signal (MB) and a measuring end signal (ME) are generated and while utilizing these two signals, delay time compensation cycle determine signals (MQ1, MQ 2...MQn) are outputted for the unit of each measuring unit. While receiving the RCLK dividing a frequency into two stages, RCLK signal, feedback FCLK signal and enable signal, delay time compensating signals (Q1, Q2...Qn) are generated corresponding to the delay time compensation cycle determine signals, RCLK is delayed and a phase synchronized clock signal (QCLK) is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase synchronization circuit for a semiconductor integrated circuit, and more particularly, to a feedback loop and a delay time measurement path which can compensate for delay time and reduce power consumption. The present invention relates to a high-speed phase locked loop circuit and a phase locked loop method using the circuit.

[0002]

2. Description of the Related Art In a phase-locked loop circuit which operates at a high speed with respect to an external clock, a PLL (Phase) is used as a method for compensating for a delay time caused by a clock used in an internal circuit driving a high load capacitance. -Loc
A ked Loop) circuit and a DLL (Delay-Locked Loop) circuit are used.

Hereinafter, a conventional high-speed phase locked loop circuit will be described with reference to the accompanying drawings. FIG. 1 shows a conventional RDL.
FIG. 2 is a configuration block diagram of a delay line of an RDLL, and FIG. 3 is a configuration block diagram and an operation timing diagram of a phase comparator of the RDLL. PLL and DL
Since L uses an analog circuit such as a charge pump circuit or a VCO to perform a phase synchronization operation between the input clock and the internal clock, many cycles are required to synchronize the phases. Therefore, it operates in synchronization with an input clock like an SDRAM, and operates in an active mode (read / read).
If a standby mode (standby or refresh) can be set in addition to the write operation), after shutting down the input clock for low-power operation in the standby mode,
When switching to the active mode, the phases cannot be synchronized quickly. Conversely, in order to quickly synchronize phases, the input clock cannot be cut off, so that low-power operation is difficult. Furthermore, since it takes a lot of time to synchronize the phases, power consumption also increases at this time.

As described above, in order to solve the problem of the phase synchronization, that is, the time required for the phase synchronization and the power consumption, the delay time is digitally adjusted, and the register is set again at the time of the phase synchronization operation after the initial synchronization. FIG. 1 shows a digital DLL that uses the phase synchronization information stored in the digital DLL. FIG. 1 is a diagram showing a configuration of an RDLL in which a 256 Mb SDRAM can stably supply an operation clock without being affected by temperature, voltage, and process variables. The RDLL comprises a clock buffer 1 for buffering an external clock (RCLK) and a 1/8 frequency divider for dividing the buffered external clock at a constant ratio (1/8).
A frequency divider 4, a phase comparator 8 that compares an output signal of the １ ／ frequency divider 4 with a clock signal input again through the replica circuit 10 and outputs the clock signal, and outputs a clock based on the comparison signal of the phase comparator 8. A shift register 9 for outputting a shift signal for delaying the clock signal, a logic gate chain, and a delay line 5 capable of changing the delay time of the １ ／ frequency-divided clock signal by the shift signal; and a logic gate chain. The clock signal output from the clock buffer 1 includes a delay line 2 that can similarly change the delay time by a shift signal, and an output buffer 3 that buffers and outputs the clock signal output from the delay line 2. You. Both the delay lines 2 and 5 select the delay time based on the output from the shift register 9.

The replica circuit 10 buffers the clock signal output from the delay line 5 after being delayed by the shift signal and outputs a dummy output buffer 6. The replica circuit 10 inputs the signal of the dummy output buffer 6 to the phase comparator 8. And a clock buffer 7. This circuit automatically tracks the external clock and can match the data output to the rising edge of the external clock.

FIG. 2 shows the relationship between the delay lines 2 and 5 of the RDLL constituted by a logic gate chain and the shift register 9. As shown in the figure, the delay time can be selected at the high position of the shift register 9. It is configured as follows. FIG. 3 is a diagram showing the configuration and operation timing of the RDLL phase comparator. The external clock RCLK is frequency-divided by 1/8 with a period of 4 and is made to logically match the internal clock. The phase comparator 8 has two comparators. The first comparator compares the signal A obtained by dividing the external clock with the internal clock B, and delays the external clock A by a unit delay with the external clock A by the second comparator. With the internal clock C. The output of each comparator is sent to an AND gate as shown, and the shift register is shifted left or right depending on the comparison result. In such an RDLL, the time required until phase synchronization is as follows. Minimum delay time of _loop (T _{min, loop} ) = t _D + t _CLKBUF +
t _REF Here, t _D is the delay time, t _CLKBUF the time required for a clock buffer, t _REF is the period time of the reference clock.

At this time, the unit delay time required until phase synchronization
Number of stages N and time T until phase synchronization_LOCKIs the following
It is. N = (T_CLKR-T_{min, loop}) / T_D, T_LOCK= CLK
S * N where CLKS is the trigger of the data flip-flop.
And CLKS cycle tCLKS = M * T_CLKR>
T_{min, loop}+ T_D・ N_LOCKCLKR is set to 2 so that
Frequency division or higher frequency division is used. M is frequency division
Indicates a number. Therefore, T_CLKR-T_{min, loop}> 0
Come, T_LOCK= M * T_CLKR* (T_{CL KR}-T_{min, loop}) / T
_DIt is. Synchronization time is T_CLKIs proportional to the square of
_{min, loop}When the frequency is determined, the lower frequency, that is, the clock
If the cycle time is long, the synchronization setting time becomes very long.
You. Also, at higher frequencies, one delay between loop delay times
M value must be increased to guarantee an increase in delay time
Therefore, the time until phase synchronization becomes longer.

In order to solve the problem of the RDLL, a method of monitoring a delay time in a clock driving buffer without a feedback loop and measuring the delay time through a unit delay time chain is used to perform phase synchronization in a second cycle. 4 and 5 show a clock synchronization delay circuit for achieving the following. 4 and 5 show a conventional SMD.
FIG. 2 is a configuration block diagram and an operation timing diagram of a (Synchronous Mirror Delay) circuit. SMD phase synchronization circuit is DMC
(Delay Monitor Circuits), FDA (Foward Delay Arra
y), BDA (Backward Delay Array), MCC (Mirror Co
The external clock (CLK) input through the input buffer is phase-synchronized in the second cycle, as shown in FIG.

In such an SMD phase locked loop circuit, the time required for phase synchronization is two cycles, which is fast. However, when a delay time in a unit delay element such as an FDA or a BDA changes due to an external factor such as a change in a power supply voltage and a temperature or a process, there is no loop for compensating for the change. In some cases, deviation from the input clock may occur. Due to this deviation, it may be difficult to compensate for the delay time of the internal clock buffer in the phase synchronization circuit. Therefore, it is necessary to pay attention to the production so that the delay times of the unit delay elements of the FDA and the BDA match.

[0010]

The conventional high-speed phase locked loop circuit has the following problems. Long synchronization times are required, resulting in increased power consumption. When the phase-locked loop is switched from non-operation to normal operation, it cannot be used as the internal clock of the circuit until the sync clock is stabilized. Keeps working. For this reason, power consumption in the phase locked loop cannot be prevented. When the data flip-flop stores the initial synchronization information, the time required for phase synchronization again can be one cycle. However, if the initial synchronization information is out of order due to external factors such as changes in the power supply voltage and temperature, changes in the phase of the input clock, etc., the phase synchronization operation must be performed again. is there. Although the SMD phase synchronization circuit can monitor the delay time of the clock input buffer to be compensated and the clock buffer delay time (by the DMC block), the result of the phase synchronization depends on the sensitivity of the clock input buffer and the waveform of the input clock. The difference is great. That is,
The timing error of the clock synchronized through the synchronization process is large. If the period of the input clock is longer than the delay time of the monitor circuit, an error occurs in the initial operation, and the use of the clock frequency is restricted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional phase synchronization circuit and synchronization method, and an object thereof is to compensate for a delay time.
Another object of the present invention is to provide a phase synchronization circuit and a synchronization method that can reduce power consumption.

[0012]

SUMMARY OF THE INVENTION A high-speed phase locked loop circuit of the present invention having a feedback loop and a self-delay time measurement path adapted to compensate for delay time and reduce power consumption is provided by an RCLK input by an enable signal. And the phase of the FCLK fed back is measured to generate a measurement start signal (MB) and a measurement end signal (ME). Using these two signals, a delay time compensation cycle determination signal ( MQ1, MQ2, ... MQ
n) Measurement Controlled Delay (Measure Controlled Delay)
Locked Loop Part), RCLK and RCL divided by 2
Receiving the K signal, the feedback FCLK, and the enable signal, generating delay time compensation signals (Q1, Q2,... Qn) according to the delay time compensation cycle determination signal, and variably delaying the input RCLK. A register control unit (r) that outputs a phase-synchronized clock signal (QCLK)
egister Controlled Delay Locked Loop Part).

According to the high-speed phase synchronization method of the present invention, when an enable signal is input, a self-phase measurement start pulse is started to form a phase-locked loop and input RCLK.
Feedback (FCLK) in a first stage;
Latching an enable signal at a rising edge of FCLK, outputting a measurement start signal (MB), outputting a measurement end signal (ME) using RCLK, and measuring a phase difference; When the phase difference measurement operation is completed, a delay time compensation cycle determination signal (MQs) is set, and when the MQs are set, delay time compensation cycle determination signals (MQ1, MQ2,.
MQn) to start a self-phase measurement end pulse, start a phase detection operation when the self-phase measurement end pulse starts, and delay time (i.e., one variable delay stage or one measurement delay stage). determining a delay time to be compensated in a phase detection section corresponding to 1.5 times of (tUNIT) within two cycles, and the state of the FCLK and the detection feedback clock (DFCLK) in the phase detection section and the synchronization signal (LOCK). ), The phase-locked state is maintained without switching the formed loop.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a high-speed phase locked loop circuit and method according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 6 is a configuration block diagram of the high-speed phase synchronizer according to the embodiment of the present invention. The high-speed phase locked loop circuit according to the present embodiment includes a measurement control unit 40 and a register control unit 41.
Reference numeral 0 denotes a self-phase measurement circuit section 42 and a measurement delay circuit section 43. The register control section 41 includes a phase detection section 44, a shift register array 45, a variable delay array 46, and a delay compensation section 47.

Next, their configurations will be described in more detail. The self-phase measuring circuit (SPMC) 42 first receives a rising edge of FCLK from the external clock RCLK input through the input buffer and the FCLK fed back from the delay compensator 47 after the enable signal is input. The enable signal is latched, the measurement start signal (MB) is output, and the measurement end signal (ME) is output at the subsequent rising edge of RCLK. That is, the interval between FCLK and RCLK is measured. The delay compensator 47 takes into account all delay causes and performs a delay time for compensation (in the illustrated embodiment, the input buffer delay d1 and the clock driver delay d1).
2. The delay d3) of the output buffer is determined. The measurement delay array 43 includes n measurement delay units connected in series, and outputs MBs output from the self-phase measurement circuit unit 42,
In response to the two signals of the ME, the delay time compensation cycle decision signals (MQ1, MQ
2,. . . MQn).

The phase detector 44 divides the frequency of the divided RCLK by 2
, RCLK itself, FCLK fed back from the delay compensator 47, and an enable signal, the delay time (tUNI) in one variable delay stage or one measurement delay stage.
T), a phase is detected at an interval corresponding to 1.5 times of T), and a comparison operation is performed. Output a signal. The shift register array 45 includes n unit shift register units connected in series, and the SHR, SHL, LOCK,
Upon receiving the SCLK signal, the delay time compensation cycle determination signals (MQ1, MQ2,... MQn) of the measurement delay array 43 are received.
(Q1, Q2,... Qn)
Is output. The variable delay array 46 includes delay time compensation signals (Q1, Q2) input from the shift register array 45.
2,. . . Qn), the input RCLK is delayed according to the compensation signal and output. The variable delay array 46 is connected to a clock driver 48 which receives the output of the delayed clock (DCLK) and outputs a phase-synchronized clock signal (QCLK). The delay compensator 47 receives the delay clock (DC
LK) to compensate and feed back FCLK.

Hereinafter, the detailed configuration of each component block of the high-speed phase locked loop circuit of the present embodiment configured as described above will be described. FIG. 7 is a configuration block diagram of the self-phase measurement circuit 42 according to the present embodiment, and FIG. 8 is a configuration diagram of the measurement delay array according to the present embodiment. First, as shown in FIG. 7, the self-phase measurement circuit unit 42 in the measurement control unit 40 includes three D flip-flops 50 to 51, and starts measurement at the rising edge of each clock after the enable signal is input. Signal (MB), Measurement end signal (ME)
Is output. The first D flip-flop 50 receives the enable signal and the feedback clock (FCLK) whose delay time for phase synchronization has been compensated, and receives the FCL.
At the rising edge of K, the enable signal is latched and the measurement start signal (MB) is output. The second D flip-flop 51 includes an enable signal and an input clock (RCLK).
And an enable signal is latched and output at the rising edge of RCLK. The third D flip-flop 52 receives the input clock RCLK and the output of the second D flip-flop 51 as inputs, latches the output of the second D flip-flop 51 at the rising edge of RCLK, and outputs a measurement end signal (ME).

In the measurement delay array 43, n measurement delay units shown in FIG. 8 are connected in series, and delay time compensation cycle determination signals (MQ1, MQ1) are output from each measurement delay unit.
2,. . . MQn). As shown in FIG. 8, the measurement start signal (MB) from the self-phase measurement circuit section 42 and V
a first NAND gate 60 that performs a NAND operation on the cc signal and outputs the same, and an output signal of the first NAND gate 60 and Vc
a second NAND gate 61 that performs a NAND operation on the c signal and outputs the same, and an output signal of the second NAND gate 61 and a measurement end signal (MEb) obtained by inverting the measurement end signal (ME) from the self-phase measurement circuit unit 42. Third NA for performing NAND operation and outputting delay time compensation cycle determination signal (MQ)
And an ND gate 62. The figure shows the ith unit, and the input MB (i) to the first NAND 60 is the second NAN of the unit connected before this unit.
Means the output of D61.

That is, the first measurement delay unit receives the measurement start signal (MB) directly from the self-phase measurement circuit section 42, but the subsequent measurement delay units receive the measurement start signal (MB) from the second NAND gate of the preceding measurement delay unit. M
B). Therefore, the output MQ of each unit
(I) are each delayed by a time corresponding to the number of previously connected units, their outputs,
That is, the compensation cycle determination signals MQ (1) to MQ (n)
Are shifted by the delay time of the unit up to the preceding stage and the delay time of the unit itself.
5 is input.

Next, each component block of the register control unit (DLL) 41 will be described. FIG. 9 shows the phase detector 44 of the present embodiment, FIG. 10 shows the shift register array 45 of the present embodiment, and FIG. 11 shows the variable delay array 46 of the present embodiment. First, the phase detection unit 44 shown in FIG. 9 will be described. The phase detection unit 44 receives four input signals as described above. The input clock signal (RCLK) is input to the first to third D flip-flops 80 to 82, and the feedback clock signal (FCLK) fed back from the delay compensator 47 is input to the first D flip-flop 80.
Are input to the second D flip-flop 81 via a delay unit that delays by a period corresponding to 1.5 times the delay time (tUNIT) in one variable delay stage or one measurement delay stage. The enable signal is connected to the reset terminals of the first to fourth D flip-flops 80 to 83. The other input is the signal of PCLK divided by two. The first D flip-flop 80 latches and outputs the feedback clock signal (FCLK) by the input clock (RCLK), and the second D flip-flop 1 outputs the delay time (tUNIT) in one variable delay stage or one measurement delay stage.
The feedback clock signal (FCLK) delayed by a period corresponding to 1.5 times of the above is latched by the input clock (RCLK) and output. 1D flip-flop 80
And the output signal (Q) of the second D flip-flop 81 are NANDed by the first NAND gate 86a. The second NAND gate 86b performs a NAND operation on the signal calculated by the first NAND gate 86a and the inverted feedback signal of its own output, and outputs the result to the third D flip-flop 82. The third D flip-flop 82 latches and outputs the output signal of the second NAND gate 86b by the input clock (RCLK). The inverted output signal (/ Q) of the first D flip-flop 80, the inverted output signal (/ Q) of the second D flip-flop 81, and the output signal (Q) of the third D flip-flop 82 are referred to as a third NAND.
The NAND operation is performed by the gate 86c. The operation signal and enable signal of the third NAND gate 86c are connected to the fourth NAN
A NAND operation is performed by the D gate 86d, and the operation output is output to the first
The signal is inverted by the inverter 87a to output a right shift (SHR) signal. The inverted output signal (/ Q) of the second D flip-flop 81, the output signal (Q) of the third D flip-flop 82, and the enable signal are output to the fifth NAND gate 86e.
, And outputs its output to the second inverter 87.
Invert at b to output a left shift (SHL) signal. On the other hand, the right shift and left shift signals are NANDed by the sixth NAND gate 86f, and the third inverter 87c
Is inverted. The fourth D flip-flop 83 has its third
The signal inverted by the inverter is latched by the input clock (RCLK) divided by two, and a synchronized clock signal (LOCK) is output. This synchronization signal (LOCK)
And the enable signal by the seventh NAND gate 86g.
The output is inverted by the fourth inverter 87d after the ND operation, and the inverted signal is output to the multiplexer (MU).
X) Used as a switching signal of 85. This MU
X85 multiplexes the divided-by-2 input clock (RCLK / 2) delayed by the delay circuit 84 and the ground signal, and outputs a shift-adjusted divided-by-2 clock (SCLK).

The shift register array 45 receives the delay time compensation signal (Q) in units of each shift register unit according to the delay time compensation cycle determination signals (MQ1, MQ2,... MQn) output from the measurement delay array 43.
1, Q2,. . . Qn). As shown in FIG. 10, the shift register unit 45 receives an output MQ (i) from the measurement delay array 40, left and right shift signals SHR and SHL from the phase detection unit 44, and a divide-by-2 clock SCLK. In addition, the output Q (i-1) of the preceding unit and the unit Q (i + 1) of the next stage are input. The right shift signal of the phase detector 44 and the delay time compensation signal Q (i + 1) of the next stage are connected to the first NAND gate 74.
To the left shift signal and the delay time compensation signal Q of the previous stage.
(I-1) are input to the second NAND gate 75, and are respectively NAND-operated, and their outputs are connected to the third NAND gate 75.
The gate 76 further performs a NAND operation. The third NAN
The operation signal of the D gate 76 is output via the first transmission gate 77. After its output is delayed, it is sent through a second transmission gate 78 to one input of a fourth NAND gate 79. Switching of the first and second transmission gates 77 and 78 is performed by the shift adjustment frequency-divided-by-2 clock (SCLK) and its inverted signal. 4th NAN
The other input of the D gate 79 is a delay time compensation cycle determination signal (MQ1, MQ2,...) Of the measurement delay array 43.
MQn) is one signal corresponding to this unit,
NAND them and output Q of this unit.
(I) is output. At the same time, it outputs an inverted delay time compensation signal Qb (i) obtained by inverting the output Q (i).

The variable delay array 46 has n variable delay units connected in series, and the configuration of each variable delay unit is shown in FIG. The delay time compensation signal (Qi) of the corresponding unit from the shift register array and the output signal X (i-1) of the preceding variable delay unit are converted to the first NA
An output obtained by performing a NAND operation in the ND gate 71 is output as an output X (i) of the present unit. Since the first stage variable delay unit does not have a preceding stage unit, the input clock (RCLK) is supplied to the first NAND gate 71 instead of X (i-1).
Is the other input. The output signal X (i) of the first NAND gate 71 and the inverted delay time compensation signals (Qb1, Qb)
2,. . . Qbn) corresponding to this unit is calculated by the second NAND gate 72, and its calculated output and the feedback signal Y (i) fed back from the next stage are NANDed and output by the third NAND gate 73. It goes without saying that the output is sent to the preceding unit as a feedback signal.

The phase synchronizing operation of the high-speed phase synchronizing circuit according to the present embodiment thus configured will be described below. FIG. 12 is a waveform diagram of the phase-locked clock according to the present embodiment. FIG. 13 is a clock timing chart showing a phase comparison detection section according to the present embodiment, and FIGS. 14 and 15 are a phase comparison detection logic diagram and a simulation diagram according to the present embodiment. First, the enable signal is input to the self-phase measuring circuit 42 to start the operation of the phase locked loop. That is,
When the enable signal goes high, the input clock (RCLK) is input to the phase locked loop. At this time, since Q (i) of the shift register array 45 is the first, Q (1)
Only high and the rest is low. Since the variable delay array 46 forms a loop while the Q (i) value is high, the input RCLK is fed back in the first stage. The delayed and fed-back signal is called an FCLK signal.

When the self-phase measurement start pulse starts, the self-phase measurement circuit section 42 performs a phase difference measurement operation between RCLK and FCLK. The self-phase measurement circuit section 42
The enable signal is latched at the rising edge of CLK to output a measurement start signal (MB), and RCLK is output as a measurement end signal (ME) via a two-stage flip-flop. The phase difference between the measurement start signal and the measurement end signal is
The phase difference between the first rising edge of FCLK fed back and the second rising edge of RCLK after being enabled. This phase difference is equal to the delay time to be compensated.

When the operation of measuring the phase difference between RCLK and FCLK is completed, the delay time compensation cycle determination signal of the measurement delay array 43 is set. Self-phase measurement circuit section 42
8 is inverted (MEb), and the measurement end signal (ME) of FIG.
Is input in common to each measurement delay unit as shown in
The measurement start signal (MB) is transmitted from each measurement delay unit to the next measurement delay unit via two NAND gates. At this time, until the measurement start signal becomes high, that is, the inverted measurement end signal (MEb) becomes low, the measurement end signal (MB (i)) transmitted from each measurement delay unit causes a low pulse through the remaining NAND gates. MQ
Generating (i). At this time, the transmission time from each measurement delay unit is the same as the variable delay time. Thus, M
If Qs is set, the shift register array 4
5 is a delay time compensation cycle determination signal (MQ1, MQ1).
2,. . . MQn) and start a self-phase measurement end pulse.

As described above, when the self-phase measurement end pulse starts, the operations of the self-phase measurement circuit section 42 and the measurement delay array 43 are stopped, and the phase detection section 44 is enabled. Each of the generated low pulses (MQ (i)) is input to the corresponding shift register unit to activate Q (i) to high, and when it becomes high to the i-th, i
Form a phase locked loop in stages. The FCLK delays the DCLK by a delay time to be compensated, and inputs the delayed DCLK to the phase detection unit 44. This is to determine the delay time to be compensated within two cycles, which corresponds to FCLK (2) in FIG.

The phase detection section 44 has a phase detection section as shown in FIG. 13, and performs a phase detection operation by the comparison detection logic of FIG. At this time, the phase detection period is 1.5 times the delay time (tUNIT) in one variable delay stage or one measurement delay stage.
It corresponds to double. When the activation start point of the feedback FCLK and the delayed feedback clock (DCLK) output from the variable delay array 46 is in the phase detection interval and the synchronization signal (LOCK) is generated, the formed loop stage is switched. And maintain phase synchronization.
The synchronization signal makes the output of the MUX 85 of the phase detector 44 low. The output of the MUX 85 becomes low, and the shift register array 45 stores a shift-adjusted divided-by-2 clock (SCLK).
Will be input. Therefore, the shift register array 4
5 subsequently maintains the same state and maintains phase synchronization without switching the formed loop stages. At this time, since the magnitude of the variable delay for maintaining the phase synchronization state is not changed, no jitter occurs.

Even if, for some reason, the self-phase measurement section does not coincide with the delay time to be compensated and does not immediately enter the phase-locked state, the FCLK has already approached the phase-locked detection area. Phase synchronization is performed within two cycles. When the phase synchronization is completed and the enable signal goes low, the shift register array 45 returns to the initial state and waits for the next phase synchronization operation command. FIG. 15 shows a simulation result of the movement synchronization operation.

[0029]

The high-speed phase locked loop circuit of the present invention described above has the following effects because it has a feedback loop and a self-delay time measurement path suitable for delay time compensation and reduction of the consumption electrodes. Synchronization is quickly performed by the self-delay time measurement path, and the phase synchronization operation is performed with low power. This has the effect of reducing power consumption of the entire integrated circuit and enabling high-speed access operation. Since the switching from the non-operation of the phase locked loop to the normal operation can be performed within several cycles, there is an effect of improving the performance of the memory when applied to a synchronous memory such as an SDRAM or an SGRAM. There is a self-delay time measuring circuit, and the phase synchronization operation is performed within two cycles even if the initial synchronization information is out of order. For this reason, the clock synchronization operation is stable.
Further, even when the timing error due to the synchronization is small and the cycle of the input clock is large, no error occurs in the initial operation. This has the effect of efficiently performing the access operation of the element.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a conventional RDLL.

FIG. 2 is a configuration block diagram of a delay line of an RDLL.

FIG. 3 is a configuration block diagram and operation timing diagram of an RDLL phase comparator;

FIG. 4 is a configuration block diagram of a conventional SMD circuit.

FIG. 5 is an operation timing chart of a conventional SMD circuit;

FIG. 6 is a configuration block diagram of a high-speed phase locked loop circuit according to an embodiment of the present invention.

FIG. 7 is a configuration block diagram of a self-phase measurement circuit according to the present embodiment;

FIG. 8 is a configuration diagram of a measurement delay array according to the present embodiment.

FIG. 9 is a configuration block diagram of a phase detection unit according to the present embodiment.

FIG. 10 is a configuration diagram of a shift register array according to the present embodiment.

FIG. 11 is a configuration diagram of a variable delay array according to the present embodiment.

FIG. 12 is a phase-locked clock waveform diagram according to the present embodiment.

FIG. 13 is an operation timing chart showing a phase comparison detection section according to the present embodiment.

FIG. 14 is a logic diagram of a phase comparison detection according to the present embodiment.

FIG. 15 is a simulation diagram according to the present embodiment.

[Explanation of symbols]

 Reference Signs List 40 measurement control unit 41 register control unit 42 self-phase measurement circuit unit 43 measurement delay array 44 phase detection unit 45 shift register array 46 variable delay array 47 delay compensation unit 48 clock driver

Claims (15)

[Claims] 1. A measurement start signal (MB) and a measurement end signal (ME) are generated by measuring phases of an externally input RCLK signal and a feedback FCLK signal by an enable signal, and these two signals are used. Then, the delay time compensation cycle determination signal (MQ
1, MQ2,. . . MQn), and a delay time compensation signal (Q1) according to a delay time compensation cycle determination signal in response to a signal obtained by dividing the frequency of the RCLK signal by two, the RCLK signal, the fed back FCLK signal, and the enable signal. , Q2,... Qn) and a register control unit for delaying the input RCLK and outputting a phase-locked clock signal (QCLK). 2. An RCLK signal input from the outside and a FCLK signal fed back are measured by an enable signal, a measurement start signal (MB) is output at a rising edge of the FCLK, and a measurement end signal is output by an RCLK clock. (ME) output self phase measurement circuit (SPM
C) and n measurement delay units connected in series, receiving two signals of MB and ME output from the self-phase measurement circuit unit and receiving a signal for determining a delay time compensation cycle for each measurement delay unit. (MQ1, MQ2,... MQn), and a right shift (SHR) receiving the signal obtained by dividing the frequency of the RCLK signal by two, the RCLK signal, the fed back FCLK signal 8, and the enable signal. A phase detector for outputting a left shift (SHL), a clock synchronization signal (LOCK), and a frequency-divided clock for shift adjustment (SCLK) signal, and n unit shift register units are connected in series.
Upon receiving the HR, SHL, LOCK, and SCLK signals, the delay time compensation signal (Q
1, Q2,. . . Qn), and a delay time compensation signal (Q1,
Q2,. . . Qn), a variable delay array capable of changing an output delay time by delaying the input RCLK, a delay compensator for receiving a delay clock (DCLK) of the variable delay array and feeding back an FCLK signal, A high-speed phase-locked loop comprising: a clock driver that receives a delay clock (DCLK) of a delay array and outputs a clock signal (QCLK) that is phase-locked. 3. The phase detection and comparison operation according to claim 1, wherein the phase detection and comparison operation is performed in a section corresponding to 1.5 times the delay time (tUNIT) in one variable delay stage or one measurement delay stage. Synchronous circuit. 4. A self-phase measuring circuit for latching an enable signal at a rising edge of a feedback clock (FCLK) compensated for a delay time for phase synchronization and outputting a measurement start signal (MB).
A D flip-flop (DF / F); a second D flip-flop that latches and outputs an enable signal at a rising edge of the input RCLK signal;
3. The high-speed phase-locked loop according to claim 2, further comprising a third de-flip-flop that latches at a rising edge of the LK signal and outputs a measurement end signal (ME). 5. A measurement delay array, comprising: a first NAND gate that performs a NAND operation on a measurement start signal (MB) and a Vcc signal and outputs the result; and outputs an output signal of the first NAND gate and a Vcc signal to N.
A second NAND gate for performing an AND operation and outputting; an output signal of the second NAND gate and a measurement end signal (M
E) is inverted with the measurement end signal (MEb)
3. The high-speed phase-locked loop according to claim 2, further comprising a third NAND gate for calculating and outputting a delay time compensation cycle determination signal (MQ). 6. The first measurement delay unit receives a measurement start signal (MB) from the self-phase measurement circuit unit, and the next measurement delay unit receives the second Nth of the preceding measurement delay unit.
6. The high-speed phase locked loop circuit according to claim 5, wherein a measurement start signal (MB) is received from an AND gate. 7. A phase detector, comprising: a first D flip-flop that latches and outputs a feedback clock FCLK signal by an input clock RCLK signal; and outputs a delay-compensated feedback FCLK signal to a first D flip-flop.
A second D flip-flop latched and output by a CLK signal; and an output signal (Q) of the first D flip-flop and a second D flip-flop.
A first NAND gate for performing a NAND operation on the output signal (Q) of the flip-flop, and a second NAN for performing another NAND operation on the operation signal of the first NAND gate and the inverted feedback signal and outputting the result.
A third D flip-flop that latches and outputs the output signal of the second NAND gate with the RCLK signal; an inverted output signal (/ Q) of the first D flip-flop and an inverted output signal of the second D flip-flop ( / Q) and 3rd
A third NAND gate that performs a NAND operation on the output signal (Q) of the D flip-flop and outputs the result, and outputs the operation signal and the enable signal of the third NAND gate to N
A fourth NAND gate for performing an AND operation and outputting the inverted signal; and inverting the output signal of the fourth NAND gate to shift right (S
A first inverter that outputs an HR) signal, a fifth NAND gate that performs a NAND operation on an inverted output signal (/ Q) of the second D flip-flop, an output signal (Q) of the third D flip-flop, and an enable signal, and outputs the result. The operation signal of the fifth NAND gate is inverted and shifted left (S
HL) a second inverter that outputs a signal, a sixth NAND gate that performs a NAND operation on the right shift and left shift signals and outputs the result, and an input obtained by dividing the operation signal of the sixth NAND gate inverted by the third inverter by two. 4D for latching with a clock (RCLK) and outputting a synchronization signal (LOCK)
A flip-flop, a seventh NAND gate for performing a NAND operation on the synchronization signal and the enable signal and outputting the same, and a fourth for inverting and outputting the operation signal of the seventh NAND gate
An inverter, a signal obtained by dividing the frequency of the RCLK signal by 2 and a ground signal into the fourth signal.
3. An MUX for multiplexing an output signal of the inverter as a switching signal and outputting a shift-divided-by-2 clock (SCLK) for shift adjustment.
A high-speed phase-locked loop as described. 8. The FCLK signal, which is a feedback clock input to the second D flip-flop, has a delay time (tUN) in one variable delay stage or one measurement delay stage.
8. The high-speed phase-locked loop according to claim 7, wherein the delay is performed within a section corresponding to 1.5 times IT). 9. A shifter register array, comprising: a first NAND gate in which each unit performs a NAND operation on a right shift signal of a phase detection unit and a delay time compensation signal (Q (i + 1)) of a next stage, and outputs the result; 2N which performs a NAND operation on the left shift signal of the section and the delay time compensation signal (Q (i−1)) of the preceding stage and outputs the result
An AND gate; a third NAND gate for performing a NAND operation on the operation signals of the first and second NAND gates;
A first transmission gate for switching and outputting the operation signal of the ND gate;
And a second transmission gate for switching and outputting the inverted signal, and a delay time compensation cycle determination signal (MQ) of the measurement delay array.
1, MQ2,. . . MQn) and the output signal of the second transmission gate are NAND-operated to perform delay time compensation signals (Q1, Q2).
2,. . . 3. The high-speed phase-locked loop according to claim 2, further comprising a fourth NAND gate for outputting Qn). 10. The variable delay array, wherein n serially connected variable delay units receive a delay time compensation signal (Q1, Q2,... Qn) and an input clock (RCLK) to perform a NAND operation.
AND the output signal (X) of the first NAND gate and the inverted delay time compensation signals (/ Q1, / Q2,... / Qn)
A second NAND gate for performing an arithmetic operation and outputting, and a third NAND gate for performing an NAND operation on an operation signal of the second NAND gate and a feedback signal (Y) fed back from a next stage and outputting the result. Item 3. A high-speed phase locked loop according to Item 2. 11. The unit according to claim 10, wherein RCLK is input to a first unit of the n variable delay units connected in series, and a unit output signal of a previous stage is input from a next unit. High-speed phase-locked loop. 12. A step of receiving an enable signal, starting a self-phase measurement start pulse to form a phase locked loop, and feeding back an externally input RCLK signal in a first step to obtain an FCLK signal. , The enable signal is latched at the rising edge of the FCLK signal, the measurement start signal (MB) is output, and the RCLK signal is passed through the two-stage flip-flop to the measurement end signal (M).
E) outputting the phase difference and measuring the phase difference between the RCLK signal and the FCLK signal, and setting the delay time compensation cycle decision signal (MQ) after the operation of measuring the phase difference between the RCLK signal and the FCLK signal is completed. Loading a time compensation cycle determination signal (MQ1, MQ2,... MQn) to start a self-phase measurement end pulse; and starting a self-phase measurement end pulse to start a phase detection operation. The delay time (tU) in the variable delay stage or one measurement delay stage
Determining a delay time to be compensated in a phase detection section corresponding to 1.5 times NIT) within two cycles; and determining whether the activation start point of the FCLK signal and the detected feedback clock (DFCLK) is in the phase detection section. A step of maintaining phase synchronization without switching between formed loop steps if a synchronization signal (LOCK) is generated in between. 13. The phase difference between the measurement start signal and the measurement end signal is determined by the rising edge of the first FCLK signal to be fed back and the second RCL after being enabled.
13. The high-speed phase synchronization method according to claim 12, wherein the phase difference is the same as the phase difference between the rising edge of the K signal. 14. The high-speed phase synchronization method according to claim 12, wherein the FCLK signal fed back by forming a phase locked loop is fed back after being delayed by a delay time to be compensated. 15. The high-speed phase synchronization method according to claim 12, wherein a transmission time at each measurement delay stage is equal to a variable delay time for delay time compensation.